HEADER_DATA_START
OBDATA_V002 https://openboarddata.org
TIMESTAMP 1732170223
BOARDPATH laptops/apple/820-3209
ID 820-3209
BRAND apple
CATEGORY laptops
COMMENT 
HEADER_DATA_END
### Released under the OBbL - https://opendatacommons.org/licenses/odbl/1-0/
DIAGNOSIS_DATA_START
DIAGNOSIS_DATA_END

COMPONENTS_DATA_START
### Component Category Value Comment
### v = value, p = package, c = manufacturer code, r = rating, m = misc, s = status
###
J24 v DC IN
Q156 m Needs Vgs = 25V
Q8 m Needs Vgs = 25V
R1603 m U41: Spannungsteiler 5V
R1604 m U41: Spannungsteiler 3V3
R402 m U41: Spannungsteiler 3V3
R525 m U41: Spannungsteiler 5V
S1 v ON/OFF
U12 v 5.4Gbps Dual-Mode DisplayPort 1:2 Demultiplexer
U148 m https://4donline.ihs.com/images/VipMasterIC/IC/ROHM/ROHM-S-A0003173230/ROHM-S-A0003173230-1.pdf?hkey=CECEF36DEECDED6468708AAF2E19C0C6
U148 v Tri-Axis Digital Accelerometer
U149 v 3.3 V, 2 differential channel, 2 : 1 multiplexer/demultiplexerswitch
U21 m https://www.alldatasheet.com/datasheet-pdf/download/89337/TOSHIBA/TC7SB385FU.html
U21 v Single Bus Switch
U31 m https://www.alldatasheet.com/datasheet-pdf/download/89337/TOSHIBA/TC7SB385FU.html
U31 v Single Bus Switch
U41 m Pin14=VIN, Pin13=5VLDO, Pin3=3V3LDO
U41 v Dual Synchronous Step-Down Controller with5V and 3.3V LDO's
U70 m https://www.ti.com/lit/ds/symlink/tps51206.pdf
U70 p WSON10_2020_400_01_35r433
U70 v DDR Voltage Regulator IC
COMPONENTS_DATA_END

NETS_DATA_START
### Network Valuetype Value Comment
### d = diode, v = voltage, r = resistance, a = alias, t = net comment
###
ALL_SYS_PWRGD/Default d 0.42 ''
CPUVSENSE_IN/Default d 0.00 ''
CPU_CATERR_L/Default d 0.31 ''
CPU_PECI_R/Default d 0.12 ''
CPU_PROCHOT_L/Default d 0.03 ''
CPU_THRMTRIP_3V3/Default d 1.06 ''
DP_TBTSNK1_HPD/Default d 0.00 ''
G3_POWERON_L/Default d 1.81 ''
GND_SMC_AVSS/Default d 0.00 ''
KBDLED_ANODE/Default d 0.587 ''
KBDLED_FB/Default d OL ''
LPC_AD<0>/Default d 0.48 ''
LPC_AD<1>/Default d 0.48 ''
LPC_AD<2>/Default d 0.48 ''
LPC_AD<3>/Default d 0.48 ''
LPC_CLK33M_SMC/Default d 0.51 ''
LPC_FRAME_L/Default d 0.49 ''
LPC_PWRDWN_L/Default d 0.50 ''
LPC_SERIRQ/Default d 0.53 ''
MEM_EVENT_L/Default d OL ''
N8809242/Default t VCC3M+Switching+VR+Dual+FET ''
N8935054/Default t VCC5M+Switching+VR+Dual+FET ''
NC/Default d - ''
PCIE_CLK100M_SSD_N/Default d 0.365 ''
PCIE_CLK100M_SSD_P/Default d 0.365 ''
PCIE_SSD_D2R_N<1>/Default d 0.287 ''
PCIE_SSD_D2R_P<1>/Default d 0.285 ''
PCIE_SSD_R2D_N<1>/Default d OL ''
PCIE_SSD_R2D_P<1>/Default d OL ''
PM_CLKRUN_L/Default d 0.54 ''
PM_DSW_PWRGD/Default d 0.71 ''
PM_PCH_SYS_PWROK/Default d 0.70 ''
PM_PWRBTN_L/Default d 0.52 ''
PM_SLP_S3_L/Default d 0.45 ''
PM_SLP_S4_L/Default d 0.45 ''
PM_SLP_S5_L/Default d 0.50 ''
PM_SYSRST_L/Default d 0.54 ''
PP1V2_S5_SMC_VDDC/Default d OL ''
PP3V3_S0_SSD_FLT/Default d 0.299 ''
PP3V3_S5_AVREF_SMC/Default d 0.54 ''
PP3V3_S5_SMC_VDDA/Default d 0.29 ''
PP3V3_TPAD_CONN/Default d OL ''
PP3V42_G3H/Default d 0.29 ''
PP5V_TPAD_FILT/Default d 0.430 ''
PPDCIN_G3H_OR_PBUS/Default d 1.030 ''
PPVCCSA_S0_REG_R/Default d 0.00 ''
S5_PWRGD/Default d 0.41 ''
SATA_PCIE_SEL/Default d 0.740 ''
SATA_SSD_D2R_N/Default d 0.739 ''
SATA_SSD_D2R_P/Default d 0.739 ''
SATA_SSD_R2D_N/Default d 0.740 ''
SATA_SSD_R2D_P/Default d 0.740 ''
SMBUS_SMC_0_S0_SCL/Default d 1.30 ''
SMBUS_SMC_0_S0_SDA/Default d 1.30 ''
SMBUS_SMC_1_S0_SCL/Default d 0.49 ''
SMBUS_SMC_1_S0_SDA/Default d 0.49 ''
SMBUS_SMC_2_S3_SCL/Default d 0.65 ''
SMBUS_SMC_2_S3_SDA/Default d 0.65 ''
SMBUS_SMC_3_SCL/Default d 0.58 ''
SMBUS_SMC_3_SDA/Default d 0.57 ''
SMBUS_SMC_5_G3_SCL/Default d 0.47 ''
SMBUS_SMC_5_G3_SDA/Default d 0.47 ''
SMC_1V5S3_ISENSE/Default d 1.50 ''
SMC_3V3S0_ISENSE/Default d OL ''
SMC_ADAPTER_EN/Default d 0.49 ''
SMC_ADC23/Default d OL ''
SMC_BATLOW_L/Default d 0.75 ''
SMC_BC_ACOK/Default d 0.49 ''
SMC_BIL_BUTTON_L/Default d 1.81 ''
SMC_BMON_ISENSE/Default d OL ''
SMC_CLK32K/Default d 0.51 ''
SMC_CPUVCCIO_ISENSE/Default d OL ''
SMC_CPU_ISENSE/Default d 1.44 ''
SMC_CPU_SA_ISENSE/Default d OL ''
SMC_CPU_VSENSE/Default d 1.10 ''
SMC_DCIN_ISENSE/Default d OL ''
SMC_DCIN_VSENSE/Default d 1.24 ''
SMC_DEBUGPRT_EN_L/Default d 0.50 ''
SMC_DEBUGPRT_RX_L/Default d 0.52 ''
SMC_DEBUGPRT_TX_L/Default d 0.54 ''
SMC_DELAYED_PWRGD/Default d 0.64 ''
SMC_EXTAL/Default d OL ''
SMC_FAN_0_CTL/Default d OL ''
SMC_FAN_0_TACH/Default d OL ''
SMC_GFX_ISENSE/Default d 1.44 ''
SMC_GFX_VSENSE/Default d 1.10 ''
SMC_HDD_ISENSE/Default d OL ''
SMC_HS_COMPUTING_ISENSE/Default d 1.50 ''
SMC_LCDBKLT_ISENSE/Default d OL ''
SMC_LID/Default d 0.439 ''
SMC_LRESET_L/Default d 0.39 ''
SMC_ODD_DETECT/Default d OL ''
SMC_ONOFF_L/Default d 0.608 ''
SMC_OOB1_RX_L/Default d 0.704 ''
SMC_OOB1_TX_L/Default d 0.704 ''
SMC_OTHER_HI_ISENSE/Default d OL ''
SMC_PBUS_VSENSE/Default d 1.23 ''
SMC_PECI_L/Default d OL ''
SMC_PME_S4_DARK_L/Default d 0.38 ''
SMC_PME_S4_WAKE_L/Default d 0.58 ''
SMC_PM_G2_EN/Default d 0.41 ''
SMC_PROCHOT/Default d OL ''
SMC_RESET_L/Default d 0.44 ''
SMC_RUNTIME_SCI_L/Default d 0.53 ''
SMC_RX_L/Default d OL ''
SMC_S4_WAKESRC_EN/Default d 0.67 ''
SMC_S5_PWRGD_VIN/Default d OL ''
SMC_SYS_KBDLED/Default d 0.62 ''
SMC_TCK/Default d 1.81 ''
SMC_TDI/Default d 1.82 ''
SMC_TDO/Default d 1.80 ''
SMC_THRMTRIP/Default d 1.69 ''
SMC_TMS/Default d 1.81 ''
SMC_TPAD_RST_L/Default d 0.617 ''
SMC_TX_L/Default d 1.81 ''
SMC_VCCIO_CPU_DIV2/Default d OL ''
SMC_VCCSA_VSENSE/Default d 1.10 ''
SMC_WAKE_L/Default d OL ''
SMC_WAKE_SCI_L/Default d 0.52 ''
SMC_WLAN_ISENSE/Default d OL ''
SMC_XTAL/Default d OL ''
SMS_INT_L/Default d 1.80 ''
SPI_DESCRIPTOR_OVERRIDE_L/Default d OL ''
SPI_SMC_CLK/Default d 0.51 ''
SPI_SMC_CS_L/Default d 0.50 ''
SPI_SMC_MISO/Default d 0.47 ''
SPI_SMC_MOSI/Default d 0.47 ''
SSD_CLKREQ_L/Default d 0.500 ''
SSD_RESET_L/Default d 0.600 ''
SYS_ONEWIRE/Default d OL ''
UNCONNECTED_269/Default d OL ''
UNCONNECTED_270/Default d - ''
USB_BT_WAKE_N/Default d 0.00 ''
USB_SMC_N/Default d OL ''
USB_SMC_P/Default d OL ''
USB_TPAD_N/Default d 0.668 ''
USB_TPAD_P/Default d 0.673 ''
WIFI_EVENT_L/Default d 0.68 ''
DOCK_PWR20/Normal v 20.000 ''
N8905060/Normal v 3.300 ''
VCC3M/Normal v 3.300 ''
VCC5M/Normal v 5.000 ''
VINT20/Normal v 20.000 ''
VL5/Normal v 5.000 ''

NETS_DATA_END

### END