HEADER_DATA_START OBDATA_V002 https://openboarddata.org TIMESTAMP 1701992239 BOARDPATH laptops/apple/820-3476 ID 820-3476 BRAND apple CATEGORY laptops COMMENT HEADER_DATA_END ### Released under the OBbL - https://opendatacommons.org/licenses/odbl/1-0/ DIAGNOSIS_DATA_START SECT_START Backlight NOTE_START Diagnosing Check your voltage on backlight output. If below 1V probably a bad fuse or MOSFET. If 8.4V check EN signal on [p:U7701:3], if present, check [n:BKL_PWM], if > 1V then replace [p:U7701] NOTE_END SECT_END SECT_START Overview NOTE_START Summary NOTE_END SECT_END SECT_START Power Rails NOTE_START S5 [n:PPBUS_G3H] [n:PPBUS_S5_HS_COMPUTING_ISNS] [n:PPBUS_S5_HS_OTHER_ISNS] [n:PPDCIN_G3H_ISOL] [n:PP3V42_G3H] [n:PPVRTC_G3H] [p:C1910:1] [n:PP5V_S5] [n:PP3V3_S5] NOTE_END NOTE_START S4/S3 [n:PP5V_S4RS3] [n:PP3V3_S4SW_SNS] [n:PP3V3_S4] [n:PP3V3_S3] [n:PP1V8_S3] [n:PP1V2_S3] NOTE_END NOTE_START S0 [n:PP1V05_SUS] ( needs [n:PP3V3_S5] -> [n:PP3V3_SUS_FET_R] ) [n:PP5V_S0] [n:PP3V3_S0] [n:PP3V3_S0SW_SSD] [n:PP1V5_S0] [n:PP0V6_S0_DDRVTT] [n:PP1V05_S0] [n:PP1V05_S0SW_PCH_HSIO] [n:PPVCC_S0_CPU] [n:PPHV_S0SW_LCDBKLT] NOTE_END NOTE_START Missing PM_SLP_S4_L Missing [n:PM_SLP_S4_L] can sometimes be diagnosed by going through and ensuring all the following signals are present; [n:PPVRTC_G3H] [n:RTC_RESET_L] [n:PCH_SRTCRST_L] [n:PCH_INTVRMEN] [n:PCH_DSWVRMEN] [n:PCH_CLK32K_RTCX1] [n:PP3V3_S5] [n:PM_DSW_PWRGD] [n:PP3V3_SUS] [n:PM_BATLOW_L] [n:PM_RSMRST_L] [n:PM_PWRBTN_L] NOTE_END SECT_END DIAGNOSIS_DATA_END COMPONENTS_DATA_START ### Component Category Value Comment ### v = value, p = package, c = manufacturer code, r = rating, m = misc, s = status ### COMPONENTS_DATA_END NETS_DATA_START ### Network Valuetype Value Comment ### d = diode, v = voltage, r = resistance, a = alias, t = net comment ### ADAPTER_SENSE/Default d 0.597 '' ADAPTER_SENSE/Default v 3.3 '' ALL_SYS_PWRGD/Default d 0.430 '' ALL_SYS_PWRGD/Default v 3.4 '' BKLT_EN_R/Default d 0.53 '' BKLT_ISET_KEYB/Default d 0.67 '' BKLT_KEYB1/Default d 0.64 '' BKLT_KEYB2/Default d 0.64 '' BKLT_PWM_KEYB/Default d 0.53 '' BKLT_SCL/Default d 0.53 '' BKLT_SD/Default d 0.57 '' BKLT_SDA/Default d 0.53 '' BKLT_SENSE_OUT/Default d 0.73 '' CAM_SENSOR_WAKE_L_CONN/Default d 0.00 '' CHGR_ACIN/Default d 0.52 '' CHGR_ACIN/Default v 3.9 '' CHGR_AGATE/Default d 0.63 '' CHGR_AGATE/Default v na '' CHGR_AMON/Default d 0.70 '' CHGR_BGATE/Default d 0.642 '+' CHGR_BMON/Default d 0.71 '+' CHGR_BOOT/Default d 0.554 '+' CHGR_CELL/Default d 0.69 '' CHGR_CSI_N/Default d 0.567 '+' CHGR_CSI_P/Default d 0.561 '+' CHGR_CSO_N/Default d 0.137 '+' CHGR_CSO_P/Default d 0.139 '+' CHGR_DCIN/Default d 0.61 '' CHGR_DCIN/Default r na '' CHGR_DCIN/Default t High+Resistance+between+K+and+M '' CHGR_DCIN/Default v 16.23 '' CHGR_ICOMP/Default d 0.72 '' CHGR_ICOMP/Default v 0 '' CHGR_LGATE/Default d .447 '+' CHGR_PHASE/Default d 0.135 '+' CHGR_RST_L/Default d 0.49 '' CHGR_SGATE/Default d 0.617 '+' CHGR_UGATE/Default d 0.57 '+' CHGR_VCOMP/Default d 0.71 '' CHGR_VFRQ/Default d 0.47 '' CHGR_VFRQ/Default v 0 '' CHGR_VNEG/Default d 0.52 '' CPUVR_BOOT1/Default d 0.60 '' CPUVR_COMP/Default d 0.57 '' CPUVR_DRSEL/Default d 0.00 '' CPUVR_FB/Default d 0.54 '' CPUVR_FB2/Default d 0.55 '' CPUVR_FCCM/Default d 0.57 '' CPUVR_IMON/Default d 0.57 '' CPUVR_ISEN1/Default d 0.58 '' CPUVR_ISEN2/Default d 0.58 '' CPUVR_ISUMN_R/Default d 0.36 '' CPUVR_ISUMP/Default d 0.48 '' CPUVR_LGATE1/Default d 0.43 '' CPUVR_NTC/Default d 0.58 '' CPUVR_PGOOD_R/Default d 0.70 '' CPUVR_PHASE1/Default d 0.00 '' CPUVR_PROG1/Default d 0.58 '' CPUVR_PROG2/Default d 0.57 '' CPUVR_PROG3/Default d 0.58 '' CPUVR_PWM1/Default d 0.57 '' CPUVR_PWM2/Default d 0.57 '' CPUVR_SLOPE/Default d 0.58 '' CPUVR_UGATE1/Default d -0.52 '' CPU_PROCHOT_L/Default d 0.20 '' CPU_RTN/Default d 0.00 '' CPU_VIDALERT_L/Default d 0.21 '' CPU_VIDSCLK/Default d 0.19 '' CPU_VIDSOUT/Default d 0.20 '' CPU_VR_EN/Default d 0.32 '' CPU_VR_READY/Default d 0.53 '' DDRREG_1V8_VREF/Default d 0.63 '' DDRREG_DRVH/Default d 0.57 '' DDRREG_DRVL/Default d 0.43 '' DDRREG_EN/Default d 0.53 '' DDRREG_FB/Default d 0.68 '' DDRREG_LL/Default d 0.11 '' DDRREG_MODE/Default d 0.52 '' DDRREG_PGOOD/Default d 0.49 '' DDRREG_TRIP/Default d 0.74 '' DDRREG_VBST/Default d 0.60 '' DDRREG_VDDQSNS/Default d 0.12 '' DDRREG_VTTSNS/Default d 0.16 '' EDP_BKLT_EN/Default d 0.68 '' EDP_BKLT_PSR_EN/Default d 0.53 '' EDP_PANEL_PWR/Default d 0.68 '' EDP_PANEL_PWR_OR_PSR_EN/Default d 0.67 '' FAN_RT_PWM/Default d 0.90 '' FAN_RT_TACH/Default d OL '' I2C_CAM_SCK/Default d 0.76 '' I2C_CAM_SDA/Default d 0.76 '' ISNS_1V05_S0_N/Default d 0.130 '' ISNS_1V05_S0_P/Default d 0.130 '' ISNS_LCDBKLT_N/Default d 0.14 '' ISNS_LCDBKLT_P/Default d 0.14 '' LCDBKLT_EN_L/Default d 0.00 '' LCDBKLT_FB/Default d 0.72 '' LCDBKLT_FET_DRV/Default d 0.49 '' LCDBKLT_SW/Default d 0.42 '' LCD_PSR_EN/Default d 0.58 '' LPCPLUS_RESET_L/Default d 0.57 '' LPC_AD<0>/Default d 0.56 '' LPC_AD<1>/Default d 0.56 '' LPC_AD<2>/Default d 0.56 '' LPC_AD<3>/Default d 0.56 '' LPC_CLK24M_LPCPLUS/Default d 0.49 '' LPC_FRAME_L/Default d 0.56 '' LPC_PWRDWN_L/Default d 0.64 '' LPC_SERIRQ/Default d 0.56 '' MEMVTT_PWR_EN/Default d 0.53 '' MIPI_CLK_CONN_N/Default d 0.40 '' MIPI_CLK_CONN_P/Default d 0.40 '' MIPI_DATA_CONN_N/Default d 0.40 '' MIPI_DATA_CONN_P/Default d 0.40 '' P1V05S0_DRVH/Default d 0.59 '' P1V05S0_DRVH_R/Default d 0.59 '' P1V05S0_DRVL/Default d 0.46 '' P1V05S0_EN/Default d 0.43 '' P1V05S0_FB/Default d 0.68 '' P1V05S0_LL/Default d 0.13 '' P1V05S0_MODE/Default d 0.52 '' P1V05S0_PGOOD/Default d 0.48 '' P1V05S0_TRIP/Default d 0.74 '' P1V05S0_VBST/Default d 0.60 '' P1V05S0_VDDQSNS/Default d 0.14 '' P1V05S0_VTT/Default d 0.55 '' P1V05S0_VTTREF/Default d 0.48 '' P1V05S3_EN/Default d 0.49 '' P1V05_S0_VREF/Default d 0.62 '' P1V5S0_EN/Default d 0.73 '' P1V5S0_PGOOD/Default d 0.55 '' P1V5_S0_FB/Default d 0.77 '' P1V5_S0_SW/Default d 0.36 '' P3V3S5_COMP2/Default d 0.73 '' P3V3S5_CSN2/Default d 0.14 '' P3V3S5_CSP2/Default d 1.29 '' P3V3S5_DRVH/Default d 0.67 '' P3V3S5_DRVL/Default d 0.52 '' P3V3S5_LL/Default d 0.14 '' P3V3S5_RF/Default d 0.58 '' P3V3S5_VBST/Default d 0.55 '' P3V3S5_VFB2/Default d 0.57 '' P5VP3V3_SKIPSEL/Default d 0.48 '' P5VP3V3_VREF2/Default d 0.48 '' P5VP3V3_VREG3/Default d 0.56 '' P5VS4RS3_EN/Default d 0.49 '' P5VS4RS3_PGOOD/Default d 0.49 '' P5VS4_COMP1/Default d 0.73 '' P5VS4_CSN1/Default d 0.40 '' P5VS4_CSP1/Default d 1.30 '' P5VS4_DRVH/Default d 0.94 '' P5VS4_DRVL/Default d 0.52 '' P5VS4_LL/Default d 0.40 '' P5VS4_VBST/Default d 0.62 '' P5VS4_VFB1/Default d 0.58 '' P5VS4_VSW/Default d 0.400 '' PBUSVSENS_EN_L/Default d 0.49 '' PBUSVSENS_EN_L_DIV/Default d OL '' PBUS_S0_VSENSE/Default d OL '' PBUS_S0_VSENSE_IN/Default d 0.14 '' PCH_CLK32K_RTCX1/Default d 0.46 '' PICKB_L/Default d 0.69 '' PLT_RESET_L/Default d 0.53 '' PLT_RST_BUF_L/Default d 0.54 '' PM_CLKRUN_L/Default d 0.59 '' PM_RSMRST_L/Default d OL '' PM_S0_PGOOD/Default d 0.66 '' PM_SLP_S3_BUF_L/Default d 0.43 '' PM_SLP_S3_R_L/Default d 0.67 '' PP0V675_S0_DDRVTT/Default d 0.15 '' PP1V05_S0/Default d 0.130 '' PP1V05_S0_REG_R/Default d 0.130 '' PP1V2_CAM_XTALPCIEVDD/Default d 0.34 '' PP1V35_S3/Default d 0.11 '' PP3V3_S0/Default d 0.35 '' PP3V3_S4/Default d 0.40 '' PP3V3_S5/Default d 0.14 '' PP3V3_S5RS3RS0_SYSCLKGEN/Default d 0.14 '' PP3V3_S5_AVREF_SMC/Default d 0.59 '' PP3V3_S5_SMC_VDDA/Default d 0.305 '' PP3V3_SUS/Default d 0.34 '' PP3V3_TBTLC/Default d 0.41 '' PP3V3_TPAD_CONN/Default d 0.43 '' PP3V42_G3H/Default d 0.305 '' PP3V42_G3H_SMC_SPVSR/Default d 0.31 '' PP5V1_CHGR_VDD/Default d 0.313 '+' PP5V1_CHGR_VDDP/Default d 0.31 '+' PP5VR3V3_SW_LCD/Default d 0.52 '' PP5VR3V3_SW_LCD_UF/Default d 0.52 '' PP5V_S0/Default d 0.40 '' PP5V_S0_BKLT_A/Default d 0.40 '' PP5V_S0_BKLT_D/Default d 0.40 '' PP5V_S0_CPUVR_VDD/Default d 0.40 '' PP5V_S0_KBDBKLT_SW/Default d 0.40 '' PP5V_S3RS0_ALSCAM_F/Default d 0.40 '' PP5V_S3_LTUSB_A_ILIM/Default d 0.51 '' PP5V_S4/Default d 0.40 '' PP5V_S4_CUMULUS/Default d 0.57 '' PP5V_S5/Default d 0.46 '' PPBUS_S5_HS_COMPUTING/Default d 0.14 '' PPBUS_S5_HS_OTHER3V3/Default d 0.14 '' PPDDR_S3_REG_R/Default d 0.110 '' PPVBAT_G3H_CHGR_REG/Default d 0.135 '' PPVIN_S0SW_LCDBKLT/Default d 0.87 '' PPVIN_S0SW_LCDBKLT_R/Default d 0.14 '' PPVIN_S0_CPUVR_VIN/Default d 0.15 '' PPVIN_SW_LCDBKLT_SW/Default d 0.870 '' PPVOUT_BKLT_FB2/Default d 0.60 '' PPVRTC_G3H/Default d 0.45 '' PPVTTDDR_S3/Default d 0.48 '' PSOC_F_CS_L/Default d 0.72 '' PSOC_MISO/Default d 0.72 '' PSOC_MOSI/Default d 0.72 '' PSOC_SCLK/Default d 0.72 '' S5_PWRGD/Default d 0.57 '' S5_PWR_EN/Default d 0.53 '' SMBUS_SMC_1_S0_SCL/Default d 0.58 '' SMBUS_SMC_1_S0_SDA/Default d 0.58 '' SMBUS_SMC_2_S3_SCL/Default d 0.75 '' SMBUS_SMC_2_S3_SDA/Default d 0.75 '' SMBUS_SMC_5_G3_SCL/Default d 0.51 '' SMBUS_SMC_5_G3_SDA/Default d 0.51 '' SMC_BC_ACOK/Default d 0.52 '' SMC_DELAYED_PWRGD/Default d 0.69 '' SMC_MANUAL_RST_L/Default d 0.66 '' SMC_ONOFF_L/Default d 0.65 '' SMC_PM_G2_EN/Default d 0.53 '' SMC_PROCHOT/Default d 0.74 '' SMC_RESET_L/Default d 0.51 '' SMC_ROMBOOT/Default d 1.40 '' SMC_RX_L/Default d 0.74 '' SMC_SENSOR_PWR_EN/Default d 0.67 '' SMC_TCK/Default d 0.74 '' SMC_TDI/Default d 0.74 '' SMC_TDO/Default d 0.74 '' SMC_TMS/Default d 0.74 '' SMC_TPAD_RST_L/Default d 0.46 '' SMC_TX_L/Default d 0.74 '' SPIROM_HOLD_L/Default d 0.49 '' SPIROM_USE_MLB/Default d 0.49 '' SPIROM_WP_L/Default d 0.64 '' SPI_ALT_CLK/Default d 0.58 '' SPI_ALT_CS_L/Default d 0.56 '' SPI_ALT_MISO/Default d 0.50 '' SPI_ALT_MOSI/Default d 0.51 '' SPI_MLB_CLK/Default d 0.58 '' SPI_MLB_CS_L/Default d 0.56 '' SPI_MLB_MISO/Default d 0.50 '' SPI_MLB_MOSI/Default d 0.51 '' SPKRCONN_R_ID/Default d 0.73 '' SPKRCONN_R_OUT_N/Default d 0.50 '' SPKRCONN_R_OUT_P/Default d 0.50 '' SPKRCONN_SR_OUT_N/Default d 0.62 '' SPKRCONN_SR_OUT_P/Default d 0.62 '' SUS_PGOOD_CT/Default d 0.63 '' SYSCLK_CLK25M_CAMERA/Default d 0.45 '' SYSCLK_CLK25M_TBT/Default d 0.44 '' SYSCLK_CLK25M_X1/Default d 0.45 '' SYSCLK_CLK25M_X2_R/Default d 0.45 '' SYS_PWROK_R/Default d 0.68 '' TP_SUS_PGOOD_MR_L/Default d 0.69 '' UNCONNECTED_50/Default d 0.45 '' UNCONNECTED_99/Default d OL '' USB_ILIM/Default d 0.54 '' USB_PWR_EN/Default d 0.49 '' XDP_LPCPLUS_GPIO/Default d 0.54 '' XDP_USB_EXTA_OC_L/Default d 0.49 '' Z2_CLKIN/Default d 0.73 '' Z2_CS_L/Default d 0.72 '' Z2_HOST_INTN/Default d 0.72 '' Z2_KEY_ACT_L/Default d 0.72 '' Z2_MISO/Default d 0.72 '' Z2_MOSI/Default d 0.72 '' Z2_SCLK/Default d 0.72 '' PCIE_WAKE_L/mes+donn%FF%FFes d - '' NETS_DATA_END ### END