Netname | Condition | Type | Value | Comment |
---|---|---|---|---|
4V5_NR | Default | d | 0.662 | |
4V5_REG_EN | Default | d | 0.358 | |
4V5_REG_IN | Default | d | 0.410 | |
ACDC_BURST | Default | d | 0.601 | |
ACDC_BURST_EN_L | Default | d | 0.761 | |
AGND_CPU | Default | d | 0.000 | |
AGND_GPUVDDQ | Default | d | 0.000 | |
AGND_P1V05S0 | Default | d | 0.000 | |
AGND_VDDQS3 | Default | d | 0.000 | |
ALL_SYS_PWRGD | Default | d | 0.501 | |
AP_CLKREQ_L | Default | d | 0.462 | |
AP_CLKREQ_Q_L | Default | d | 0.464 | |
AP_EVENT_L | Default | d | 0.753 | |
AP_RESET_CONN_L | Default | d | 0.467 | |
AP_RESET_L | Default | d | 0.432 | |
AP_WAKE_L | Default | d | 1.923 | |
AUD_CODEC_MICBIAS | Default | d | 0.551 | |
AUD_DMIC_CLK | Default | d | 0.730 | |
AUD_DMIC_CLK_CONN | Default | d | 0.736 | |
AUD_DMIC_SDA1 | Default | d | 0.712 | |
AUD_DMIC_SDA1_CONN | Default | d | 0.712 | |
AUD_GPIO_2 | Default | d | 0.622 | |
AUD_GPIO_3 | Default | d | 0.556 | |
AUD_HP_PORT_REF | Default | d | OL | |
AUD_HS_MIC_N | Default | d | OL | |
AUD_HS_MIC_P | Default | d | 1.559 | |
AUD_HS_MIC_RC_N | Default | d | OL | |
AUD_HS_MIC_RC_P | Default | d | OL | |
AUD_I2C_INT_L | Default | d | 0.562 | |
AUD_IPHS_SWITCH_EN | Default | d | 0.522 | |
AUD_IPHS_SWITCH_EN_PCH | Default | d | 0.527 | |
AUD_IP_PERIPHERAL_DET | Default | d | 0.586 | |
AUD_IP_PERPH_DET_DB | Default | d | 0.589 | |
AUD_IP_PERPH_DET_R | Default | d | OL | |
AUD_J1_DET_RC | Default | d | OL | |
AUD_J1_GND_ANALOG | Default | d | 0.000 | |
AUD_J1_HP_OUTL | Default | d | OL | |
AUD_J1_HP_OUTR | Default | d | OL | |
AUD_J1_HP_PORT_REF | Default | d | OL | |
AUD_J1_MIC_BIAS | Default | d | 0.572 | |
AUD_J1_MIC_N | Default | d | OL | |
AUD_J1_MIC_P | Default | d | 1.559 | |
AUD_J1_PP3V3_S0 | Default | d | 0.332 | |
AUD_J1_TIPDET1_R | Default | d | OL | |
AUD_J1_TIPDET2_R | Default | d | OL | |
AUD_J1_TYPEDET_R | Default | d | OL | |
AUD_LAMP_AVDD | Default | d | 0.525 | |
AUD_LAMP_BOOTLN | Default | d | 0.584 | |
AUD_LAMP_BOOTLP | Default | d | 0.585 | |
AUD_LAMP_BOOTRN | Default | d | 0.584 | |
AUD_LAMP_BOOTRP | Default | d | 0.586 | |
AUD_LAMP_EDGE | Default | d | 0.525 | |
AUD_LAMP_GAIN | Default | d | 0.595 | |
AUD_LAMP_LINC_N | Default | d | 0.730 | |
AUD_LAMP_LINC_P | Default | d | 0.725 | |
AUD_LAMP_LIN_N | Default | d | 0.600 | |
AUD_LAMP_LIN_P | Default | d | 0.600 | |
AUD_LAMP_MONO | Default | d | 0.000 | |
AUD_LAMP_OUTNL | Default | d | 0.553 | |
AUD_LAMP_OUTNR | Default | d | 0.554 | |
AUD_LAMP_OUTPL | Default | d | 0.553 | |
AUD_LAMP_OUTPR | Default | d | 0.555 | |
AUD_LAMP_RINC_N | Default | d | 0.725 | |
AUD_LAMP_RINC_P | Default | d | 0.724 | |
AUD_LAMP_RIN_N | Default | d | 0.595 | |
AUD_LAMP_RIN_P | Default | d | 0.594 | |
AUD_LI_COM | Default | d | 0.740 | |
AUD_LI_P_L | Default | d | 0.745 | |
AUD_LI_P_R | Default | d | 0.746 | |
AUD_LI_TIPDET | Default | d | 0.389 | |
AUD_LO1_L_C_N | Default | d | OL | |
AUD_LO1_L_C_P | Default | d | OL | |
AUD_LO1_L_N | Default | d | 0.724 | |
AUD_LO1_L_P | Default | d | 0.725 | |
AUD_LO1_R_C_N | Default | d | OL | |
AUD_LO1_R_C_P | Default | d | OL | |
AUD_LO1_R_N | Default | d | 0.723 | |
AUD_LO1_R_P | Default | d | 0.726 | |
AUD_LO2_L_N | Default | d | 0.725 | |
AUD_LO2_L_P | Default | d | 0.730 | |
AUD_LO2_R_N | Default | d | 0.726 | |
AUD_LO2_R_P | Default | d | 0.728 | |
AUD_MIC_INL_N | Default | d | 0.745 | |
AUD_MIC_INL_P | Default | d | 0.745 | |
AUD_MIC_INN_R | Default | d | 0.745 | |
AUD_MIC_INP_R | Default | d | 0.745 | |
AUD_OUTJACK_INSERT | Default | d | 0.618 | |
AUD_OUTJACK_INSERT_L | Default | d | 0.620 | |
AUD_PORTA_DET_L | Default | d | 0.609 | |
AUD_PORTB_DET_L | Default | d | 1.169 | |
AUD_PORTC_DET_L | Default | d | 0.612 | |
AUD_PORTD_DET_L | Default | d | 1.099 | |
AUD_RAMP_AVDD | Default | d | 0.526 | |
AUD_RAMP_BOOTLN | Default | d | 0.585 | |
AUD_RAMP_BOOTLP | Default | d | 0.588 | |
AUD_RAMP_BOOTRN | Default | d | 0.585 | |
AUD_RAMP_BOOTRP | Default | d | 0.587 | |
AUD_RAMP_EDGE | Default | d | 0.526 | |
AUD_RAMP_GAIN | Default | d | 0.591 | |
AUD_RAMP_LINC_N | Default | d | 0.723 | |
AUD_RAMP_LINC_P | Default | d | 0.726 | |
AUD_RAMP_LIN_N | Default | d | 0.593 | |
AUD_RAMP_LIN_P | Default | d | 0.599 | |
AUD_RAMP_MONO | Default | d | 0.000 | |
AUD_RAMP_OUTNL | Default | d | 0.558 | |
AUD_RAMP_OUTNR | Default | d | 0.557 | |
AUD_RAMP_OUTPL | Default | d | 0.558 | |
AUD_RAMP_OUTPR | Default | d | 0.558 | |
AUD_RAMP_RINC_N | Default | d | 0.728 | |
AUD_RAMP_RINC_P | Default | d | 0.726 | |
AUD_RAMP_RIN_N | Default | d | 0.591 | |
AUD_RAMP_RIN_P | Default | d | 0.591 | |
AUD_SDI_R | Default | d | 0.481 | |
AUD_SENSE_A | Default | d | 0.765 | |
AUD_SPDIF_CHIP | Default | d | 0.707 | |
AUD_SPDIF_OUT | Default | d | 0.730 | |
AUD_SPKRAMP_MAC_SHDN_L | Default | d | 0.551 | |
AUD_SPKRAMP_WIN_SHDN_L | Default | d | 0.556 | |
AUD_SPKR_LTWT_OUT_N | Default | d | 0.566 | |
AUD_SPKR_LTWT_OUT_P | Default | d | 0.565 | |
AUD_SPKR_LWFR_OUT_N | Default | d | 0.565 | |
AUD_SPKR_LWFR_OUT_P | Default | d | 0.564 | |
AUD_SPKR_RTWT_OUT_N | Default | d | 0.558 | |
AUD_SPKR_RTWT_OUT_P | Default | d | 0.559 | |
AUD_SPKR_RWFR_OUT_N | Default | d | 0.558 | |
AUD_SPKR_RWFR_OUT_P | Default | d | 0.557 | |
AUD_SPKR_VENDOR_ID_L | Default | d | OL | |
AUD_SPKR_VENDOR_ID_R | Default | d | OL | |
AUD_TIPDET1_R | Default | d | OL | |
AUD_TIPDET2_R | Default | d | OL | |
AUD_TIPDET_INV | Default | d | OL | |
AUD_TYPEDET_OD | Default | d | OL | |
AUD_TYPEDET_OD_INV | Default | d | 0.465 | |
AUD_TYPEDET_R | Default | d | OL | |
BKLT_BOOST | Default | d | 0.416 | |
BKLT_BOOST_1 | Default | d | 0.141 | |
BKLT_BOOST_2 | Default | d | 0.414 | |
BKLT_EN | Default | d | 0.569 | |
BKLT_EN_DIV | Default | d | 0.721 | |
BKLT_EN_L | Default | d | OL | |
BKLT_FB | Default | d | 0.706 | |
BKLT_FB_R | Default | d | 0.414 | |
BKLT_FB_XW | Default | d | 0.414 | |
BKLT_FLT | Default | d | 0.574 | |
BKLT_FLT_RC | Default | d | OL | |
BKLT_GATE | Default | d | 0.499 | |
BKLT_GATE_R | Default | d | 0.498 | |
BKLT_ISEN1 | Default | d | 0.655 | |
BKLT_ISEN1_R | Default | d | 1.120 | |
BKLT_ISEN2 | Default | d | 0.656 | |
BKLT_ISEN2_R | Default | d | 1.109 | |
BKLT_ISEN3 | Default | d | 0.656 | |
BKLT_ISEN3_R | Default | d | 1.100 | |
BKLT_ISEN4 | Default | d | 0.653 | |
BKLT_ISEN4_R | Default | d | 1.122 | |
BKLT_ISEN5 | Default | d | 0.653 | |
BKLT_ISEN5_R | Default | d | 1.104 | |
BKLT_ISEN6 | Default | d | 0.653 | |
BKLT_ISEN6_R | Default | d | 1.129 | |
BKLT_ISET | Default | d | 0.571 | |
BKLT_PHASE | Default | d | 0.169 | |
BKLT_SCL | Default | d | 0.509 | |
BKLT_SDA | Default | d | 0.519 | |
BKLT_SHUTDOWN | Default | d | 0.722 | |
BKLT_SNUBBER | Default | d | OL | |
BKLT_SW_N | Default | d | 0.000 | |
BKLT_SW_P | Default | d | 0.000 | |
BKLT_SW_R | Default | d | 0.000 | |
BKLT_VSYNC | Default | d | 0.574 | |
BKLT_VSYNC_R | Default | d | 0.574 | |
BT_PWR_EN | Default | d | 0.447 | |
BT_PWR_RST | Default | d | OL | |
BT_PWR_RST_L | Default | d | 0.733 | |
BT_RESET_MASK_L | Default | d | 0.456 | |
BURSTMODE_EN | Default | d | OL | |
BURSTMODE_EN_L | Default | d | 0.994 | |
BURSTMODE_EN_R_L | Default | d | 1.959 | |
CAM_AGND | Default | d | 0.000 | |
CAM_EXT_BOOT | Default | d | 0.529 | |
CAM_P1V2_RST_HOLDOFF | Default | d | 1.352 | |
CAM_P1V2_RST_HOLDOFF_L | Default | d | 1.373 | |
CAM_PLLGND | Default | d | 0.000 | |
CAM_PROC_RESET | Default | d | 0.682 | |
CAM_PROC_RESET_L | Default | d | 0.529 | |
CAM_RX | Default | d | 0.527 | |
CAM_SF_CLK | Default | d | 0.490 | |
CAM_SF_CLK_R | Default | d | 0.000 | |
CAM_SF_CS_L | Default | d | 0.492 | |
CAM_SF_DIN | Default | d | 0.519 | |
CAM_SF_DIN_R | Default | d | 0.538 | |
CAM_SF_DOUT | Default | d | 0.583 | |
CAM_SF_DOUT_R | Default | d | 0.536 | |
CAM_SF_HOLD_L | Default | d | 0.722 | |
CAM_SF_WP_L | Default | d | 0.535 | |
CAM_TEST | Default | d | 0.048 | |
CAM_TX | Default | d | 0.532 | |
CAM_USB_VRES | Default | d | 0.815 | |
CAM_XTAL_IN | Default | d | 0.484 | |
CAM_XTAL_OUT | Default | d | 0.548 | |
CAM_XTAL_OUT_R | Default | d | 0.596 | |
CORE_VOLTAGES_ON | Default | d | 0.594 | |
CORE_VOLTAGES_ON_R | Default | d | 1.332 | |
CPUVCC_COMP_RC | Default | d | OL | |
CPUVCC_DVC_RC | Default | d | 2.308 | |
CPUVCC_FB_RC | Default | d | 0.290 | |
CPUVCC_FB_RC_2 | Default | d | OL | |
CPUVCC_FB_R_1 | Default | d | 0.366 | |
CPUVCC_FB_R_2 | Default | d | 0.040 | |
CPUVCC_FB_R_2 | Default | r | 39.400R | |
CPUVCC_IMON_R | Default | d | 1.011 | |
CPUVCC_PSICOMP_RC | Default | d | 1.380 | |
CPU_CATERR_L | Default | d | 0.261 | |
CPU_CFG<0> | Default | d | 0.260 | |
CPU_CFG<17> | Default | d | 0.257 | |
CPU_CFG<19> | Default | d | 0.259 | |
CPU_CFG<1> | Default | d | 0.265 | |
CPU_CFG<2> | Default | d | 0.248 | |
CPU_CFG<3> | Default | d | 0.259 | |
CPU_CFG<4> | Default | d | 0.264 | |
CPU_CFG<5> | Default | d | 0.259 | |
CPU_CFG<6> | Default | d | 0.263 | |
CPU_CFG<7> | Default | d | 0.259 | |
CPU_CFG<9> | Default | d | 0.261 | |
CPU_CFG_RCOMP | Default | d | 0.051 | |
CPU_CLK135M_DPLLREF_N | Default | d | 0.292 | |
CPU_CLK135M_DPLLREF_P | Default | d | 0.295 | |
CPU_CLK135M_DPLLSS_N | Default | d | 0.297 | |
CPU_CLK135M_DPLLSS_P | Default | d | 0.299 | |
CPU_DIMMA_VREFDQ | Default | d | 0.771 | |
CPU_DIMM_VREFCA | Default | d | 0.770 | |
CPU_EDP_RCOMP | Default | d | 0.068 | |
CPU_MEM_RESET_L | Default | d | 0.352 | |
CPU_MEM_VREFCA_A_ISOL | Default | d | 0.585 | |
CPU_MEM_VREFCA_B_ISOL | Default | d | 0.584 | |
CPU_MEM_VREFDQ_A_ISOL | Default | d | 0.585 | |
CPU_MEM_VREFDQ_B_ISOL | Default | d | 0.586 | |
CPU_PECI | Default | d | 0.371 | |
CPU_PECI_R | Default | d | 0.333 | |
CPU_PEG_RCOMP | Default | d | 0.069 | |
CPU_PROCHOT_L | Default | d | 0.077 | |
CPU_PROCHOT_L | Default | r | 75.400R | |
CPU_PROCHOT_R_L | Default | d | 0.127 | |
CPU_PWRGD | Default | d | 0.381 | |
CPU_PWR_DEBUG | Default | d | 0.229 | |
CPU_RESET_L | Default | d | 0.383 | |
CPU_SKTOCC | Default | d | 0.612 | |
CPU_SKTOCC_L | Default | d | OL | |
CPU_SM_RCOMP<0> | Default | d | 0.101 | |
CPU_SM_RCOMP<1> | Default | d | 0.076 | |
CPU_SM_RCOMP<2> | Default | d | 0.101 | |
CPU_THRMTRIP_3V3 | Default | d | 0.732 | |
CPU_THRMTRIP_L | Default | d | OL | |
CPU_TT_OC_L | Default | d | OL | |
CPU_VCCSENSE_N | Default | d | 0.005 | |
CPU_VCCSENSE_N | Default | r | 2.600R | |
CPU_VCCSENSE_P | Default | r | 19.500R | |
CPU_VCCSENSE_R_N | Default | d | 0.000 | |
CPU_VCCSENSE_R_P | Default | d | 0.019 | |
CPU_VCCSENSE_R_P | Default | r | 19.500R | |
CPU_VIDALERT_L | Default | d | 0.098 | |
CPU_VIDALERT_R_L | Default | d | 0.594 | |
CPU_VIDSCLK | Default | d | 0.078 | |
CPU_VIDSCLK | Default | r | 77.400R | |
CPU_VIDSCLK_R | Default | d | 0.565 | |
CPU_VIDSOUT | Default | d | 0.078 | |
CPU_VIDSOUT | Default | r | 77.400R | |
CPU_VIDSOUT_R | Default | d | 0.080 | |
CS4206_DMIC_SCL | Default | d | 0.707 | |
CS4206_FLYC | Default | d | 0.443 | |
CS4206_FLYN | Default | d | 1.187 | |
CS4206_FLYP | Default | d | 0.627 | |
CS4206_FN | Default | d | 1.570 | |
CS4206_FP | Default | d | 0.467 | |
CS4206_HPREF | Default | d | 0.000 | |
CS4206_VCOM | Default | d | 0.637 | |
CS4206_VREF_ADC | Default | d | 0.761 | |
DEBUG_RESET_L | Default | d | 0.593 | |
DGND_BKLT | Default | d | 0.000 | |
DMI_CLK100M_CPU_N | Default | d | 0.292 | |
DMI_CLK100M_CPU_P | Default | d | 0.294 | |
DMI_N2S_N<0> | Default | d | 0.292 | |
DMI_N2S_N<1> | Default | d | 0.293 | |
DMI_N2S_N<3> | Default | d | 0.291 | |
DMI_S2N_N<0> | Default | d | 0.301 | |
DMI_S2N_N<3> | Default | d | 0.389 | |
DMI_S2N_P<0> | Default | d | 0.386 | |
DMI_S2N_P<1> | Default | d | 0.392 | |
DMI_S2N_P<3> | Default | d | 0.301 | |
DPMUX_UC_IRQ | Default | d | 0.737 | |
DP_AUXIO_EN | Default | d | 0.542 | |
DP_A_AUXCH_DDC_N | Default | d | 0.701 | |
DP_A_AUXCH_DDC_P | Default | d | 0.704 | |
DP_A_LSX_ML_N<1> | Default | d | 0.720 | |
DP_A_LSX_ML_P<1> | Default | d | 0.735 | |
DP_B_AUXCH_DDC_N | Default | d | 0.705 | |
DP_B_AUXCH_DDC_P | Default | d | 0.700 | |
DP_B_LSX_ML_N<1> | Default | d | 0.720 | |
DP_B_LSX_ML_P<1> | Default | d | 0.736 | |
DP_INTPNL_AUX_N | Default | d | 0.745 | |
DP_INTPNL_AUX_P | Default | d | 0.732 | |
DP_INTPNL_HPD | Default | d | 0.545 | |
DP_INTPNL_ML_C_N<0> | Default | d | 0.472 | |
DP_INTPNL_ML_C_N<1> | Default | d | 0.472 | |
DP_INTPNL_ML_C_P<0> | Default | d | 0.472 | |
DP_INTPNL_ML_C_P<1> | Default | d | 0.472 | |
DP_INTPNL_ML_N<0> | Default | d | OL | |
DP_INTPNL_ML_N<1> | Default | d | OL | |
DP_INTPNL_ML_P<0> | Default | d | OL | |
DP_INTPNL_ML_P<1> | Default | d | OL | |
DP_INT_EG_AUX_C_N | Default | d | 0.740 | |
DP_INT_EG_AUX_C_P | Default | d | 0.742 | |
DP_INT_EG_AUX_N | Default | d | 0.805 | |
DP_INT_EG_AUX_P | Default | d | 0.806 | |
DP_INT_EG_HPD | Default | d | 0.535 | |
DP_INT_EG_ML_N<0> | Default | d | 0.419 | |
DP_INT_EG_ML_N<1> | Default | d | 0.417 | |
DP_INT_EG_ML_P<0> | Default | d | 0.420 | |
DP_INT_EG_ML_P<1> | Default | d | 0.417 | |
DP_INT_SPDIF_AUDIO | Default | d | 0.775 | |
DP_TBTPA_AUXCH_C_P | Default | d | 0.594 | |
DP_TBTPA_AUXCH_N | Default | d | 0.736 | |
DP_TBTPA_AUXCH_P | Default | d | 0.735 | |
DP_TBTPA_DDC_DATA | Default | d | 0.523 | |
DP_TBTPA_HPD | Default | d | 0.562 | |
DP_TBTPA_ML_C_N<1> | Default | d | 0.323 | |
DP_TBTPA_ML_C_N<3> | Default | d | 0.322 | |
DP_TBTPA_ML_C_P<1> | Default | d | 0.323 | |
DP_TBTPA_ML_C_P<3> | Default | d | 0.322 | |
DP_TBTPA_ML_N<1> | Default | d | 0.679 | |
DP_TBTPA_ML_N<3> | Default | d | OL | |
DP_TBTPA_ML_P<1> | Default | d | 0.695 | |
DP_TBTPA_ML_P<3> | Default | d | OL | |
DP_TBTPB_AUXCH_C_N | Default | d | 0.515 | |
DP_TBTPB_AUXCH_C_P | Default | d | 0.622 | |
DP_TBTPB_DDC_DATA | Default | d | 0.517 | |
DP_TBTPB_HPD | Default | d | 0.557 | |
DP_TBTPB_ML_C_N<1> | Default | d | 0.322 | |
DP_TBTPB_ML_C_N<3> | Default | d | 0.324 | |
DP_TBTPB_ML_C_P<1> | Default | d | 0.321 | |
DP_TBTPB_ML_C_P<3> | Default | d | 0.323 | |
DP_TBTPB_ML_N<1> | Default | d | 0.681 | |
DP_TBTPB_ML_N<3> | Default | d | OL | |
DP_TBTPB_ML_P<1> | Default | d | 0.701 | |
DP_TBTPB_ML_P<3> | Default | d | OL | |
DP_TBTSNK0_AUXCH_C_N | Default | d | 0.800 | |
DP_TBTSNK0_AUXCH_C_P | Default | d | 0.800 | |
DP_TBTSNK0_AUXCH_N | Default | d | 0.543 | |
DP_TBTSNK0_AUXCH_P | Default | d | 0.555 | |
DP_TBTSNK0_DDC_CLK | Default | d | 0.536 | |
DP_TBTSNK0_DDC_DATA | Default | d | 0.533 | |
DP_TBTSNK0_HPD | Default | d | 0.522 | |
DP_TBTSNK0_ML_C_N<0> | Default | d | 0.436 | |
DP_TBTSNK0_ML_C_N<1> | Default | d | 0.440 | |
DP_TBTSNK0_ML_C_N<2> | Default | d | 0.436 | |
DP_TBTSNK0_ML_C_N<3> | Default | d | 0.439 | |
DP_TBTSNK0_ML_C_P<0> | Default | d | 0.437 | |
DP_TBTSNK0_ML_C_P<1> | Default | d | 0.441 | |
DP_TBTSNK0_ML_C_P<2> | Default | d | 0.436 | |
DP_TBTSNK0_ML_C_P<3> | Default | d | 0.440 | |
DP_TBTSNK0_ML_N<0> | Default | d | 0.585 | |
DP_TBTSNK0_ML_N<1> | Default | d | 0.580 | |
DP_TBTSNK0_ML_N<2> | Default | d | 0.580 | |
DP_TBTSNK0_ML_N<3> | Default | d | 0.580 | |
DP_TBTSNK0_ML_P<0> | Default | d | 0.580 | |
DP_TBTSNK0_ML_P<1> | Default | d | 0.580 | |
DP_TBTSNK0_ML_P<2> | Default | d | 0.580 | |
DP_TBTSNK0_ML_P<3> | Default | d | 0.580 | |
DP_TBTSNK1_AUXCH_C_N | Default | d | 0.800 | |
DP_TBTSNK1_AUXCH_C_P | Default | d | 0.800 | |
DP_TBTSNK1_AUXCH_N | Default | d | 0.566 | |
DP_TBTSNK1_AUXCH_P | Default | d | 0.625 | |
DP_TBTSNK1_DDC_CLK | Default | d | 0.538 | |
DP_TBTSNK1_DDC_DATA | Default | d | 0.533 | |
DP_TBTSNK1_HPD | Default | d | 0.521 | |
DP_TBTSNK1_ML_C_N<0> | Default | d | 0.436 | |
DP_TBTSNK1_ML_C_N<1> | Default | d | 0.437 | |
DP_TBTSNK1_ML_C_N<2> | Default | d | 0.435 | |
DP_TBTSNK1_ML_C_N<3> | Default | d | 0.434 | |
DP_TBTSNK1_ML_C_P<0> | Default | d | 0.435 | |
DP_TBTSNK1_ML_C_P<1> | Default | d | 0.437 | |
DP_TBTSNK1_ML_C_P<2> | Default | d | 0.433 | |
DP_TBTSNK1_ML_C_P<3> | Default | d | 0.434 | |
DP_TBTSNK1_ML_N<0> | Default | d | 0.580 | |
DP_TBTSNK1_ML_N<1> | Default | d | 0.580 | |
DP_TBTSNK1_ML_N<2> | Default | d | 0.580 | |
DP_TBTSNK1_ML_N<3> | Default | d | 0.580 | |
DP_TBTSNK1_ML_P<0> | Default | d | 0.580 | |
DP_TBTSNK1_ML_P<1> | Default | d | 0.580 | |
DP_TBTSNK1_ML_P<2> | Default | d | 0.580 | |
DP_TBTSNK1_ML_P<3> | Default | d | 0.580 | |
DP_TBTSRC_AUXCH_N | Default | d | 0.560 | |
DP_TBTSRC_AUXCH_P | Default | d | 0.605 | |
DP_TBTSRC_AUX_C_N | Default | d | 0.735 | |
DP_TBTSRC_AUX_C_P | Default | d | 0.735 | |
DP_TBTSRC_HPD | Default | d | 0.536 | |
DP_TBTSRC_ML_C_N<0> | Default | d | 0.502 | |
DP_TBTSRC_ML_C_N<1> | Default | d | 0.501 | |
DP_TBTSRC_ML_C_P<0> | Default | d | 0.501 | |
DP_TBTSRC_ML_C_P<1> | Default | d | 0.502 | |
DP_TBTSRC_ML_N<0> | Default | d | 0.324 | |
DP_TBTSRC_ML_N<1> | Default | d | 0.324 | |
DP_TBTSRC_ML_P<0> | Default | d | 0.323 | |
DP_TBTSRC_ML_P<1> | Default | d | 0.322 | |
DP_TBT_SEL | Default | d | 0.388 | |
ENETCONN_MCT0 | Default | d | OL | |
ENETCONN_MCT1 | Default | d | OL | |
ENETCONN_MCT2 | Default | d | OL | |
ENETCONN_MCT3 | Default | d | OL | |
ENETCONN_MCT_BS | Default | d | OL | |
ENETCONN_MDI_N<0> | Default | d | 0.384 | |
ENETCONN_MDI_N<1> | Default | d | 0.385 | |
ENETCONN_MDI_N<2> | Default | d | 0.385 | |
ENETCONN_MDI_N<3> | Default | d | 0.386 | |
ENETCONN_MDI_P<0> | Default | d | 0.384 | |
ENETCONN_MDI_P<1> | Default | d | 0.385 | |
ENETCONN_MDI_P<2> | Default | d | 0.384 | |
ENETCONN_MDI_P<3> | Default | d | 0.385 | |
ENETCONN_MDI_T_N<0> | Default | d | OL | |
ENETCONN_MDI_T_N<1> | Default | d | OL | |
ENETCONN_MDI_T_N<2> | Default | d | OL | |
ENETCONN_MDI_T_N<3> | Default | d | OL | |
ENETCONN_MDI_T_P<0> | Default | d | OL | |
ENETCONN_MDI_T_P<1> | Default | d | OL | |
ENETCONN_MDI_T_P<2> | Default | d | OL | |
ENETCONN_MDI_T_P<3> | Default | d | OL | |
ENETCONN_TCT | Default | d | 0.384 | |
ENET_ACT | Default | d | OL | |
ENET_ASF_GPIO | Default | d | 0.747 | |
ENET_CLKREQ_L | Default | d | 0.818 | |
ENET_CR_DATA<0> | Default | d | 0.554 | |
ENET_CR_DATA<1> | Default | d | 0.552 | |
ENET_CR_DATA<2> | Default | d | 0.556 | |
ENET_CR_DATA<3> | Default | d | 0.557 | |
ENET_CR_DATA<4> | Default | d | 0.765 | |
ENET_CR_DATA<5> | Default | d | 0.765 | |
ENET_CR_DATA<6> | Default | d | 0.764 | |
ENET_CR_DATA<7> | Default | d | 0.764 | |
ENET_CR_PWREN | Default | d | 0.541 | |
ENET_CS_L | Default | d | 0.709 | |
ENET_LOW_PWR_PCH | Default | d | 0.660 | |
ENET_MEDIA_SENSE | Default | d | 0.450 | |
ENET_MISO | Default | d | 0.708 | |
ENET_MOSI | Default | d | 0.733 | |
ENET_RESET_L | Default | d | 0.460 | |
ENET_SCLK | Default | d | 0.733 | |
ENET_SD_CLK | Default | d | 0.559 | |
ENET_SD_CMD | Default | d | 0.550 | |
ENET_SD_DETECT_L | Default | d | 0.461 | |
ENET_SD_RESET_L | Default | d | 0.427 | |
ENET_SR_DISABLE | Default | d | 0.573 | |
ENET_SR_LX | Default | d | 0.297 | |
ENET_TRAFFICLED_L | Default | d | 0.760 | |
ENET_VMAIN_PRSNT | Default | d | 0.632 | |
ENET_WAKE_L | Default | d | 0.585 | |
ENET_XTALVDDH | Default | d | 0.366 | |
FAN_0_PWM_FET | Default | d | 1.230 | |
FAN_0_PWM_FILT | Default | d | 1.231 | |
FAN_0_TACH_FET | Default | d | OL | |
FAN_0_TACH_FILT | Default | d | OL | |
FBA1_CK_MID | Default | d | 0.510 | |
FBB1_CK_MID | Default | d | 0.507 | |
FBVDD_ALTVO | Default | d | 0.517 | |
FB_A0_A<2> | Default | d | 0.413 | |
FB_A0_A<6> | Default | d | 0.408 | |
FB_A0_ABI_L | Default | d | 0.407 | |
FB_A0_CAS_L | Default | d | 0.407 | |
FB_A0_CKE_L | Default | d | 0.406 | |
FB_A0_CLK_N | Default | d | 0.510 | |
FB_A0_CS_L | Default | d | 0.409 | |
FB_A0_DBI_L<0> | Default | d | 0.380 | |
FB_A0_DBI_L<1> | Default | d | 0.379 | |
FB_A0_DQ<11> | Default | d | 0.385 | |
FB_A0_DQ<12> | Default | d | 0.380 | |
FB_A0_DQ<13> | Default | d | 0.379 | |
FB_A0_DQ<16> | Default | d | 0.379 | |
FB_A0_DQ<19> | Default | d | 0.381 | |
FB_A0_DQ<22> | Default | d | 0.381 | |
FB_A0_DQ<23> | Default | d | 0.380 | |
FB_A0_DQ<24> | Default | d | 0.380 | |
FB_A0_DQ<26> | Default | d | 0.379 | |
FB_A0_DQ<29> | Default | d | 0.380 | |
FB_A0_DQ<2> | Default | d | 0.385 | |
FB_A0_DQ<31> | Default | d | 0.378 | |
FB_A0_DQ<3> | Default | d | 0.379 | |
FB_A0_DQ<7> | Default | d | 0.384 | |
FB_A0_DQ<8> | Default | d | 0.385 | |
FB_A0_DQ<9> | Default | d | 0.384 | |
FB_A0_EDC<0> | Default | d | 0.390 | |
FB_A0_EDC<1> | Default | d | 0.385 | |
FB_A0_EDC<3> | Default | d | 0.380 | |
FB_A0_MF | Default | d | 0.122 | |
FB_A0_RAS_L | Default | d | 0.408 | |
FB_A0_SEN | Default | d | 0.121 | |
FB_A0_VREFC | Default | d | 0.320 | |
FB_A0_VREFD | Default | d | 0.330 | |
FB_A0_WCLK_N<0> | Default | d | 0.574 | |
FB_A0_WCLK_P<0> | Default | d | 0.592 | |
FB_A0_WCLK_P<1> | Default | d | 0.566 | |
FB_A0_WE_L | Default | d | 0.407 | |
FB_A1_A<0> | Default | d | 0.414 | |
FB_A1_A<6> | Default | d | 0.411 | |
FB_A1_ABI_L | Default | d | 0.412 | |
FB_A1_CAS_L | Default | d | 0.407 | |
FB_A1_CLK_N | Default | d | 0.506 | |
FB_A1_CLK_P | Default | d | 0.506 | |
FB_A1_CS_L | Default | d | 0.411 | |
FB_A1_DBI_L<2> | Default | d | 0.377 | |
FB_A1_DQ<11> | Default | d | 0.377 | |
FB_A1_DQ<12> | Default | d | 0.382 | |
FB_A1_DQ<13> | Default | d | 0.380 | |
FB_A1_DQ<14> | Default | d | 0.382 | |
FB_A1_DQ<15> | Default | d | 0.381 | |
FB_A1_DQ<16> | Default | d | 0.383 | |
FB_A1_DQ<19> | Default | d | 0.381 | |
FB_A1_DQ<21> | Default | d | 0.382 | |
FB_A1_DQ<22> | Default | d | 0.380 | |
FB_A1_DQ<23> | Default | d | 0.377 | |
FB_A1_DQ<24> | Default | d | 0.380 | |
FB_A1_DQ<25> | Default | d | 0.377 | |
FB_A1_DQ<26> | Default | d | 0.377 | |
FB_A1_DQ<2> | Default | d | 0.382 | |
FB_A1_DQ<30> | Default | d | 0.381 | |
FB_A1_DQ<31> | Default | d | 0.382 | |
FB_A1_DQ<4> | Default | d | 0.383 | |
FB_A1_DQ<5> | Default | d | 0.383 | |
FB_A1_DQ<6> | Default | d | 0.382 | |
FB_A1_DQ<7> | Default | d | 0.382 | |
FB_A1_DQ<8> | Default | d | 0.381 | |
FB_A1_EDC<0> | Default | d | 0.383 | |
FB_A1_EDC<1> | Default | d | 0.382 | |
FB_A1_EDC<2> | Default | d | 0.382 | |
FB_A1_EDC<3> | Default | d | 0.382 | |
FB_A1_MF | Default | d | 0.646 | |
FB_A1_RAS_L | Default | d | 0.413 | |
FB_A1_SEN | Default | d | 0.123 | |
FB_A1_VREFC | Default | d | 0.323 | |
FB_A1_VREFD | Default | d | 0.333 | |
FB_A1_WCLK_N<0> | Default | d | 0.572 | |
FB_A1_WCLK_N<1> | Default | d | 0.573 | |
FB_A1_WCLK_P<0> | Default | d | 0.574 | |
FB_A1_WE_L | Default | d | 0.411 | |
FB_A1_ZQ | Default | d | 0.123 | |
FB_B0_A<2> | Default | d | 0.417 | |
FB_B0_A<3> | Default | d | 0.431 | |
FB_B0_A<6> | Default | d | 0.415 | |
FB_B0_A<8> | Default | d | 0.415 | |
FB_B0_CKE_L | Default | d | 0.417 | |
FB_B0_CLK_P | Default | d | 0.514 | |
FB_B0_CS_L | Default | d | 0.418 | |
FB_B0_DBI_L<0> | Default | d | 0.389 | |
FB_B0_DBI_L<1> | Default | d | 0.389 | |
FB_B0_DQ<0> | Default | d | 0.387 | |
FB_B0_DQ<12> | Default | d | 0.388 | |
FB_B0_DQ<15> | Default | d | 0.391 | |
FB_B0_DQ<18> | Default | d | 0.388 | |
FB_B0_DQ<20> | Default | d | 0.387 | |
FB_B0_DQ<21> | Default | d | 0.389 | |
FB_B0_DQ<22> | Default | d | 0.388 | |
FB_B0_DQ<26> | Default | d | 0.389 | |
FB_B0_DQ<27> | Default | d | 0.391 | |
FB_B0_DQ<2> | Default | d | 0.388 | |
FB_B0_DQ<30> | Default | d | 0.388 | |
FB_B0_DQ<31> | Default | d | 0.388 | |
FB_B0_DQ<7> | Default | d | 0.388 | |
FB_B0_DQ<9> | Default | d | 0.388 | |
FB_B0_EDC<0> | Default | d | 0.390 | |
FB_B0_EDC<1> | Default | d | 0.391 | |
FB_B0_EDC<2> | Default | d | 0.390 | |
FB_B0_EDC<3> | Default | d | 0.391 | |
FB_B0_SEN | Default | d | 0.123 | |
FB_B0_VREFC | Default | d | 0.321 | |
FB_B0_VREFD | Default | d | 0.335 | |
FB_B0_WCLK_N<0> | Default | d | 0.586 | |
FB_B0_WCLK_N<1> | Default | d | 0.587 | |
FB_B0_WCLK_P<0> | Default | d | 0.590 | |
FB_B0_WCLK_P<1> | Default | d | 0.581 | |
FB_B1_A<0> | Default | d | 0.420 | |
FB_B1_A<2> | Default | d | 0.416 | |
FB_B1_A<3> | Default | d | 0.413 | |
FB_B1_A<6> | Default | d | 0.416 | |
FB_B1_A<8> | Default | d | 0.417 | |
FB_B1_CAS_L | Default | d | 0.413 | |
FB_B1_CS_L | Default | d | 0.414 | |
FB_B1_DBI_L<2> | Default | d | 0.384 | |
FB_B1_DQ<10> | Default | d | 0.385 | |
FB_B1_DQ<11> | Default | d | 0.385 | |
FB_B1_DQ<12> | Default | d | 0.385 | |
FB_B1_DQ<15> | Default | d | 0.385 | |
FB_B1_DQ<16> | Default | d | 0.384 | |
FB_B1_DQ<19> | Default | d | 0.384 | |
FB_B1_DQ<22> | Default | d | 0.385 | |
FB_B1_DQ<24> | Default | d | 0.385 | |
FB_B1_DQ<26> | Default | d | 0.386 | |
FB_B1_DQ<27> | Default | d | 0.385 | |
FB_B1_DQ<28> | Default | d | 0.385 | |
FB_B1_DQ<31> | Default | d | 0.385 | |
FB_B1_DQ<3> | Default | d | 0.384 | |
FB_B1_DQ<5> | Default | d | 0.384 | |
FB_B1_DQ<6> | Default | d | 0.384 | |
FB_B1_DQ<7> | Default | d | 0.385 | |
FB_B1_DQ<9> | Default | d | 0.386 | |
FB_B1_EDC<0> | Default | d | 0.386 | |
FB_B1_EDC<1> | Default | d | 0.385 | |
FB_B1_MF | Default | d | 0.640 | |
FB_B1_RAS_L | Default | d | 0.418 | |
FB_B1_RESET_L | Default | d | 0.415 | |
FB_B1_SEN | Default | d | 0.123 | |
FB_B1_VREFC | Default | d | 0.319 | |
FB_B1_VREFD | Default | d | 0.332 | |
FB_B1_WCLK_N<0> | Default | d | 0.576 | |
FB_B1_WCLK_P<0> | Default | d | 0.575 | |
FB_B1_WCLK_P<1> | Default | d | 0.571 | |
FB_B1_WE_L | Default | d | 0.413 | |
FB_CLAMP | Default | d | 0.540 | |
FB_CLAMP_TOGGLE_REQ_L | Default | d | 0.557 | |
FB_SW_LEG | Default | d | 0.213 | |
FB_VREF | Default | d | 0.670 | |
FDI_INT | Default | d | 0.426 | |
FET_EN_P12V_S5 | Default | d | 0.679 | |
FET_EN_P12V_S5_R | Default | d | OL | |
FET_RAMP_P3V3_S0 | Default | d | 0.738 | |
FET_RAMP_P3V3_S4 | Default | d | 0.739 | |
FW_PME_L | Default | d | 0.757 | |
FW_PWR_EN_PCH | Default | d | 0.540 | |
G3_POWERON_L | Default | d | 0.754 | |
GFXIMVP6_IMON | Default | d | 0.542 | |
GFXIMVP6_IMON_R | Default | d | 0.680 | |
GFXIMVP_VID<0> | Default | d | 0.513 | |
GFXIMVP_VID<1> | Default | d | 0.512 | |
GFXIMVP_VID<2> | Default | d | 0.509 | |
GFXIMVP_VID<3> | Default | d | 0.514 | |
GFXIMVP_VID<4> | Default | d | 0.542 | |
GFXIMVP_VID<5> | Default | d | 0.543 | |
GFXIMVP_VID<6> | Default | d | 0.544 | |
GND | Default | d | 0.000 | |
GND_AUDIO_HPAMP | Default | d | 0.000 | |
GPU_ALT_VREF | Default | d | 0.710 | |
GPU_BUFRSTN | Default | d | 0.776 | |
GPU_FBA_DEBUG0 | Default | d | 0.420 | |
GPU_FBB_DEBUG1 | Default | d | 0.416 | |
GPU_GOOD | Default | d | 0.552 | |
GPU_IFPAB_PLLVDD | Default | d | 0.310 | |
GPU_IFPA_IOVDD | Default | d | 0.565 | |
GPU_IFPB_IOVDD | Default | d | 0.579 | |
GPU_IFPC_IOVDD | Default | d | 0.281 | |
GPU_IFPX_PLLVDD | Default | d | 0.577 | |
GPU_JTAG_TCK | Default | d | 0.785 | |
GPU_JTAG_TDI | Default | d | 0.785 | |
GPU_JTAG_TDO | Default | d | 0.784 | |
GPU_JTAG_TMS | Default | d | 0.787 | |
GPU_JTAG_TRST_L | Default | d | 0.842 | |
GPU_MLS_STRAP0 | Default | d | 0.775 | |
GPU_MLS_STRAP2 | Default | d | 0.781 | |
GPU_MLS_STRAP3 | Default | d | 0.776 | |
GPU_MLS_STRAP4 | Default | d | 0.782 | |
GPU_OSC_27M_XTALIN | Default | d | 0.837 | |
GPU_OSC_27M_XTALOUT | Default | d | 0.818 | |
GPU_PEX_TERMP | Default | d | 0.829 | |
GPU_PRESENT_DRAIN | Default | d | 0.593 | |
GPU_PRESENT_R | Default | d | 1.350 | |
GPU_RESET_L | Default | d | 0.459 | |
GPU_RESET_R_L | Default | d | 0.459 | |
GPU_ROM_SCLK | Default | d | 0.780 | |
GPU_ROM_SI | Default | d | 0.783 | |
GPU_ROM_SO | Default | d | 0.780 | |
GPU_SMB_CLK | Default | d | 0.623 | |
GPU_SMB_DAT | Default | d | 0.623 | |
GPU_SSC_SMB_CLK | Default | d | 0.711 | |
GPU_SSC_SMB_DAT | Default | d | 0.720 | |
GPU_TESTMODE | Default | d | 0.842 | |
GPU_VCORE_VID0 | Default | d | 0.512 | |
GPU_VCORE_VID1 | Default | d | 0.511 | |
GPU_VCORE_VID2 | Default | d | 0.509 | |
GPU_VCORE_VID3 | Default | d | 0.514 | |
GPU_VCORE_VID4 | Default | d | 0.542 | |
GPU_VCORE_VID5 | Default | d | 0.542 | |
GPU_XTAL_SSIN | Default | d | 0.776 | |
HDA_BIT_CLK | Default | d | 0.511 | |
HDA_BIT_CLK_R | Default | d | 0.478 | |
HDA_RST_L | Default | d | 0.496 | |
HDA_RST_R_L | Default | d | 0.466 | |
HDA_SDIN0 | Default | d | 0.460 | |
HDA_SDOUT | Default | d | 0.502 | |
HDA_SDOUT_R | Default | d | 0.467 | |
HDA_SYNC | Default | d | 0.497 | |
HDA_SYNC_R | Default | d | 0.463 | |
HDD_OOB1_D2R_L | Default | d | 0.627 | |
HDD_OOB_1V00_REF | Default | d | 0.708 | |
HDD_PWR_EN | Default | d | 0.536 | |
HS_HDET | Default | d | 2.018 | |
HS_MIC_BIAS | Default | d | 0.572 | |
HS_RX_BP | Default | d | 0.611 | |
HS_SW_DET | Default | d | 0.563 | |
I2C_CAMSENSOR_SCL | Default | d | 0.524 | |
I2C_CAMSENSOR_SDA | Default | d | 0.524 | |
I2C_TBTRTR_SCL | Default | d | 0.670 | |
I2C_TBTRTR_SDA | Default | d | 0.670 | |
ICT_JTAG_EN | Default | d | 0.994 | |
IFPD_RSET | Default | d | 0.805 | |
ISNS_CPUVCC | Default | d | 0.743 | |
ISNS_CPUVCC_FB | Default | d | 0.684 | |
ISNS_CPUVCC_FB_R | Default | d | 0.675 | |
ISNS_GPUCORE_ALT | Default | d | 0.732 | |
ISNS_GPUCORE_FB | Default | d | 0.691 | |
ISNS_GPUCORE_R | Default | d | 0.676 | |
ISNS_HDDS0 | Default | d | 0.000 | |
ISNS_HDDS0_R | Default | d | OL | |
ISNS_P12VG3H | Default | d | 0.743 | |
ISNS_P12VG3H_R | Default | d | 0.709 | |
ISNS_P12VS0_FBVDDQ | Default | d | 0.749 | |
ISNS_P12VS0_GPUCORE | Default | d | 0.745 | |
ISNS_P12VS0_GPUCORE_R | Default | d | 0.712 | |
ISNS_P1V5S0 | Default | d | 0.743 | |
ISNS_P1V5S0_R | Default | d | 0.716 | |
ISNS_SSDS0 | Default | d | 0.747 | |
ISNS_SSDS0_R | Default | d | 0.671 | |
ISNS_VDDQS3_DDR | Default | d | 0.743 | |
ISNS_VDDQS3_DDR_R | Default | d | 0.715 | |
ISOLATE_CPU_MEM_L | Default | d | 0.565 | |
ISOLATE_MEM_5V | Default | d | 0.587 | |
ITS_PLUGGED_IN | Default | d | 1.140 | |
JTAG_ISP_TCK | Default | d | 0.527 | |
JTAG_ISP_TDI | Default | d | 0.555 | |
JTAG_ISP_TDO | Default | d | 0.550 | |
JTAG_TBT_TCK | Default | d | 0.566 | |
JTAG_TBT_TDI | Default | d | 0.645 | |
JTAG_TBT_TDO | Default | d | 0.644 | |
JTAG_TBT_TMS | Default | d | 0.645 | |
JTAG_TBT_TMS_PCH | Default | d | 0.537 | |
LCD_SHOULD_ON_R | Default | d | 1.136 | |
LDO_DDRVTTS0_SNS | Default | d | 0.544 | |
LED_RETURN_1 | Default | d | 1.121 | |
LED_RETURN_2 | Default | d | 1.090 | |
LED_RETURN_3 | Default | d | 1.100 | |
LED_RETURN_4 | Default | d | 1.125 | |
LED_RETURN_5 | Default | d | 1.106 | |
LED_RETURN_6 | Default | d | 1.132 | |
LGND_BKLT | Default | d | 0.000 | |
LPCPLUS_GPIO | Default | d | - | |
LPC_AD<0> | Default | d | 0.596 | |
LPC_AD<1> | Default | d | 0.593 | |
LPC_AD<2> | Default | d | 0.595 | |
LPC_AD<3> | Default | d | 0.595 | |
LPC_AD_R<0> | Default | d | 0.558 | |
LPC_AD_R<1> | Default | d | 0.557 | |
LPC_AD_R<2> | Default | d | 0.560 | |
LPC_AD_R<3> | Default | d | 0.563 | |
LPC_CLK33M_LPCPLUS | Default | d | 0.654 | |
LPC_CLK33M_LPCPLUS_R | Default | d | 0.621 | |
LPC_CLK33M_SMC | Default | d | 0.643 | |
LPC_CLK33M_SMC_R | Default | d | 0.614 | |
LPC_FRAME_L | Default | d | 0.588 | |
LPC_FRAME_R_L | Default | d | 0.558 | |
LPC_PWRDWN_L | Default | d | 0.663 | |
LPC_SERIRQ | Default | d | 0.697 | |
LVDS_BKLT_PWM_RC | Default | d | 0.569 | |
MAX9119_POS | Default | d | 0.698 | |
MAX97220_C1N | Default | d | 0.902 | |
MAX97220_C1P | Default | d | 0.674 | |
MAX97220_INL_N | Default | d | OL | |
MAX97220_INL_P | Default | d | OL | |
MAX97220_INR_N | Default | d | OL | |
MAX97220_INR_P | Default | d | OL | |
MAX97220_OUTL | Default | d | OL | |
MAX97220_OUTL_ZOBEL | Default | d | 0.036 | |
MAX97220_OUTR | Default | d | OL | |
MAX97220_OUTR_ZOBEL | Default | d | 0.037 | |
MAX97220_PVSS | Default | d | 1.249 | |
MAX97220_SHDN_L | Default | d | 0.622 | |
MEMRESET_ISOL_LS5V_L | Default | d | 0.596 | |
MEM_A_A<15> | Default | d | 0.243 | |
MEM_A_A<1> | Default | d | 0.242 | |
MEM_A_A<6> | Default | d | 0.242 | |
MEM_A_A<7> | Default | d | 0.240 | |
MEM_A_A<8> | Default | d | 0.249 | |
MEM_A_A<9> | Default | d | 0.240 | |
MEM_A_CAS_L | Default | d | 0.250 | |
MEM_A_CLK_N<1> | Default | d | 0.283 | |
MEM_A_CLK_P<0> | Default | d | 0.287 | |
MEM_A_CS_L<1> | Default | d | 0.246 | |
MEM_A_DQ<13> | Default | d | 0.281 | |
MEM_A_DQ<14> | Default | d | 0.282 | |
MEM_A_DQ<15> | Default | d | 0.277 | |
MEM_A_DQ<16> | Default | d | 0.278 | |
MEM_A_DQ<17> | Default | d | 0.277 | |
MEM_A_DQ<18> | Default | d | 0.280 | |
MEM_A_DQ<1> | Default | d | 0.285 | |
MEM_A_DQ<21> | Default | d | 0.281 | |
MEM_A_DQ<22> | Default | d | 0.280 | |
MEM_A_DQ<23> | Default | d | 0.282 | |
MEM_A_DQ<24> | Default | d | 0.283 | |
MEM_A_DQ<26> | Default | d | 0.287 | |
MEM_A_DQ<29> | Default | d | 0.285 | |
MEM_A_DQ<2> | Default | d | 0.278 | |
MEM_A_DQ<31> | Default | d | 0.280 | |
MEM_A_DQ<32> | Default | d | 0.291 | |
MEM_A_DQ<34> | Default | d | 0.290 | |
MEM_A_DQ<39> | Default | d | 0.290 | |
MEM_A_DQ<3> | Default | d | 0.280 | |
MEM_A_DQ<42> | Default | d | 0.289 | |
MEM_A_DQ<45> | Default | d | 0.291 | |
MEM_A_DQ<46> | Default | d | 0.288 | |
MEM_A_DQ<48> | Default | d | 0.290 | |
MEM_A_DQ<4> | Default | d | 0.281 | |
MEM_A_DQ<50> | Default | d | 0.292 | |
MEM_A_DQ<51> | Default | d | 0.290 | |
MEM_A_DQ<52> | Default | d | 0.289 | |
MEM_A_DQ<53> | Default | d | 0.289 | |
MEM_A_DQ<55> | Default | d | 0.289 | |
MEM_A_DQ<57> | Default | d | 0.289 | |
MEM_A_DQ<58> | Default | d | 0.285 | |
MEM_A_DQ<61> | Default | d | 0.287 | |
MEM_A_DQ<62> | Default | d | 0.287 | |
MEM_A_DQ<63> | Default | d | 0.289 | |
MEM_A_DQ<7> | Default | d | 0.277 | |
MEM_A_DQ<9> | Default | d | 0.280 | |
MEM_A_DQS_N<0> | Default | d | 0.280 | |
MEM_A_DQS_N<4> | Default | d | 0.290 | |
MEM_A_DQS_P<1> | Default | d | 0.280 | |
MEM_A_DQS_P<2> | Default | d | 0.282 | |
MEM_A_DQS_P<3> | Default | d | 0.281 | |
MEM_A_DQS_P<5> | Default | d | 0.291 | |
MEM_A_DQS_P<7> | Default | d | 0.289 | |
MEM_A_SA<0> | Default | d | OL | |
MEM_A_SA<1> | Default | d | OL | |
MEM_B_A<10> | Default | d | 0.241 | |
MEM_B_A<11> | Default | d | 0.240 | |
MEM_B_A<12> | Default | d | 0.240 | |
MEM_B_A<13> | Default | d | 0.242 | |
MEM_B_A<2> | Default | d | 0.244 | |
MEM_B_A<3> | Default | d | 0.243 | |
MEM_B_A<4> | Default | d | 0.242 | |
MEM_B_BA<0> | Default | d | 0.242 | |
MEM_B_BA<1> | Default | d | 0.243 | |
MEM_B_BA<2> | Default | d | 0.240 | |
MEM_B_CKE<0> | Default | d | 0.238 | |
MEM_B_CKE<1> | Default | d | 0.239 | |
MEM_B_CLK_N<1> | Default | d | 0.287 | |
MEM_B_CS_L<1> | Default | d | 0.245 | |
MEM_B_DQ<11> | Default | d | 0.280 | |
MEM_B_DQ<12> | Default | d | 0.279 | |
MEM_B_DQ<14> | Default | d | 0.274 | |
MEM_B_DQ<18> | Default | d | 0.277 | |
MEM_B_DQ<1> | Default | d | 0.278 | |
MEM_B_DQ<21> | Default | d | 0.277 | |
MEM_B_DQ<23> | Default | d | 0.578 | |
MEM_B_DQ<24> | Default | d | 0.280 | |
MEM_B_DQ<26> | Default | d | 0.279 | |
MEM_B_DQ<27> | Default | d | 0.280 | |
MEM_B_DQ<29> | Default | d | 0.280 | |
MEM_B_DQ<2> | Default | d | 0.278 | |
MEM_B_DQ<30> | Default | d | 0.280 | |
MEM_B_DQ<33> | Default | d | 0.290 | |
MEM_B_DQ<34> | Default | d | 0.286 | |
MEM_B_DQ<39> | Default | d | 0.284 | |
MEM_B_DQ<41> | Default | d | 0.291 | |
MEM_B_DQ<42> | Default | d | 0.290 | |
MEM_B_DQ<43> | Default | d | 0.289 | |
MEM_B_DQ<44> | Default | d | 0.286 | |
MEM_B_DQ<47> | Default | d | 0.285 | |
MEM_B_DQ<49> | Default | d | 0.289 | |
MEM_B_DQ<4> | Default | d | 0.279 | |
MEM_B_DQ<50> | Default | d | 0.288 | |
MEM_B_DQ<51> | Default | d | 0.287 | |
MEM_B_DQ<52> | Default | d | 0.285 | |
MEM_B_DQ<54> | Default | d | 0.284 | |
MEM_B_DQ<56> | Default | d | 0.286 | |
MEM_B_DQ<58> | Default | d | 0.289 | |
MEM_B_DQ<61> | Default | d | 0.285 | |
MEM_B_DQ<62> | Default | d | 0.283 | |
MEM_B_DQ<6> | Default | d | 0.276 | |
MEM_B_DQ<7> | Default | d | 0.279 | |
MEM_B_DQ<9> | Default | d | 0.278 | |
MEM_B_DQS_N<4> | Default | d | 0.292 | |
MEM_B_DQS_N<5> | Default | d | 0.285 | |
MEM_B_DQS_N<6> | Default | d | 0.289 | |
MEM_B_DQS_P<0> | Default | d | 0.277 | |
MEM_B_DQS_P<1> | Default | d | 0.280 | |
MEM_B_DQS_P<2> | Default | d | 0.277 | |
MEM_B_DQS_P<3> | Default | d | 0.280 | |
MEM_B_DQS_P<7> | Default | d | 0.282 | |
MEM_B_ODT<1> | Default | d | 0.246 | |
MEM_B_RAS_L | Default | d | 0.243 | |
MEM_B_SA<0> | Default | d | OL | |
MEM_B_SA<1> | Default | d | OL | |
MEM_RESET_L | Default | d | 0.818 | |
MEM_VDD_SEL_1V5_L | Default | d | 0.555 | |
MEM_VREFCA_A_RC | Default | d | 0.026 | |
MEM_VREFCA_B_RC | Default | d | 0.026 | |
MIPI_RESISTOR | Default | d | 0.791 | |
MULTI_STRAP_REF | Default | d | 0.834 | |
MUTE_CONTROL | Default | d | OL | |
NC | Default | d | OL | |
P12V_S0_FET_GATE | Default | d | 0.383 | |
P12V_S0_FET_GATE_R | Default | d | 0.683 | |
P1V2_S4_EN | Default | d | 0.782 | |
P1V5_S0_FET_GATE | Default | d | 0.683 | |
P1V8_S4_EN | Default | d | 0.782 | |
P3V3ENET_SS | Default | d | OL | |
P3V3_S0_OOB | Default | d | OL | |
P3V3_S0_SSD_FET_RAMP | Default | d | 0.657 | |
P3V42G3H_FB | Default | d | 0.720 | |
P3V42G3H_SHDN_L | Default | d | 0.719 | |
P3V42G3H_SW | Default | d | 0.328 | |
P5V_S0_FET_RAMP | Default | d | 0.660 | |
P5V_S0_HDD_FET_RAMP | Default | d | 0.734 | |
PCA9557D_RESET_L | Default | d | 0.592 | |
PCH_A20GATE | Default | d | 0.613 | |
PCH_CAM_EXT_BOOT_L | Default | d | 0.550 | |
PCH_CAM_EXT_BOOT_R_L | Default | d | 0.581 | |
PCH_CAM_RESET | Default | d | 0.549 | |
PCH_CAM_RESET_R | Default | d | 0.579 | |
PCH_CLK100M_SATAN | Default | d | 0.799 | |
PCH_CLK100M_SATAP | Default | d | 0.799 | |
PCH_CLK32K_RTCX1 | Default | d | 0.475 | |
PCH_CLK32K_RTCX2 | Default | d | 0.816 | |
PCH_CLK32K_RTCX2_R | Default | d | 0.806 | |
PCH_CLK33M_PCIIN | Default | d | 0.668 | |
PCH_CLK33M_PCIOUT | Default | d | 0.627 | |
PCH_CLK96M_DOTN | Default | d | 0.790 | |
PCH_CLK96M_DOTP | Default | d | 0.790 | |
PCH_CLKIN_GNDN | Default | d | 0.790 | |
PCH_CLKIN_GNDP | Default | d | 0.791 | |
PCH_CLKRQ3_L_GPIO25 | Default | d | 0.545 | |
PCH_CLKRQ5_L_GPIO44 | Default | d | 0.600 | |
PCH_CLKRQ7_L_GPIO46 | Default | d | 0.606 | |
PCH_DMI_RCOMP | Default | d | 0.746 | |
PCH_DSWVRMEN | Default | d | 0.797 | |
PCH_FDI_RCOMP | Default | d | 0.744 | |
PCH_GPIO10 | Default | d | 0.539 | |
PCH_GPIO16 | Default | d | 0.581 | |
PCH_GPIO31 | Default | d | 0.681 | |
PCH_GPIO32 | Default | d | 0.600 | |
PCH_GPIO36 | Default | d | 0.549 | |
PCH_GPIO41 | Default | d | 0.542 | |
PCH_GPIO42 | Default | d | 0.542 | |
PCH_GPIO49 | Default | d | 0.594 | |
PCH_GPIO72 | Default | d | 0.555 | |
PCH_INTRUDER_L | Default | d | 0.800 | |
PCH_INTVRMEN_L | Default | d | 0.801 | |
PCH_PCIE_RCOMP | Default | d | 0.787 | |
PCH_PECI | Default | d | 0.588 | |
PCH_PROCPWRGD | Default | d | 0.386 | |
PCH_RCIN_L | Default | d | 0.824 | |
PCH_SATALED_L | Default | d | 0.750 | |
PCH_SATA_RCOMP | Default | d | 0.756 | |
PCH_SMBALERT_L | Default | d | 0.666 | |
PCH_SML0ALERT_L | Default | d | 0.668 | |
PCH_SML1ALERT_L | Default | d | 0.666 | |
PCH_SPKR | Default | d | 0.611 | |
PCH_SRTCRST_L | Default | d | 0.798 | |
PCH_STRP_TOPBLK_SWP_L | Default | d | 0.495 | |
PCH_SUSACK_L | Default | d | 0.558 | |
PCH_SUSWARN_L | Default | d | 0.558 | |
PCH_TD_IREF | Default | d | 0.791 | |
PCH_USB_RBIAS | Default | d | 0.025 | |
PCIE_AP_D2R_N | Default | d | 0.383 | |
PCIE_AP_D2R_P | Default | d | 0.385 | |
PCIE_AP_R2D_C_N | Default | d | 0.386 | |
PCIE_AP_R2D_N | Default | d | OL | |
PCIE_AP_R2D_P | Default | d | OL | |
PCIE_CLK100M_AP_N | Default | d | 0.292 | |
PCIE_CLK100M_AP_P | Default | d | 0.291 | |
PCIE_CLK100M_ENET_N | Default | d | 0.293 | |
PCIE_CLK100M_ENET_P | Default | d | 0.293 | |
PCIE_CLK100M_PCHN | Default | d | 0.790 | |
PCIE_CLK100M_PCHP | Default | d | 0.791 | |
PCIE_CLK100M_SSD_N | Default | d | 0.288 | |
PCIE_CLK100M_SSD_P | Default | d | 0.294 | |
PCIE_ENET_D2R_C_N | Default | d | 0.515 | |
PCIE_ENET_D2R_C_P | Default | d | 0.516 | |
PCIE_ENET_D2R_N | Default | d | 0.386 | |
PCIE_ENET_D2R_P | Default | d | 0.386 | |
PCIE_ENET_R2D_C_N | Default | d | 0.390 | |
PCIE_ENET_R2D_C_P | Default | d | 0.390 | |
PCIE_ENET_R2D_N | Default | d | 0.500 | |
PCIE_ENET_R2D_P | Default | d | 0.500 | |
PCIE_TBT_D2R_N<0> | Default | d | 0.379 | |
PCIE_TBT_D2R_N<1> | Default | d | 0.382 | |
PCIE_TBT_D2R_N<2> | Default | d | 0.379 | |
PCIE_TBT_D2R_P<0> | Default | d | 0.385 | |
PCIE_TBT_D2R_P<1> | Default | d | 0.388 | |
PCIE_TBT_D2R_P<2> | Default | d | 0.382 | |
PCIE_TBT_D2R_P<3> | Default | d | 0.380 | |
PCIE_TBT_R2D_C_N<0> | Default | d | 0.389 | |
PCIE_TBT_R2D_C_N<1> | Default | d | 0.386 | |
PCIE_TBT_R2D_C_N<2> | Default | d | 0.387 | |
PCIE_TBT_R2D_C_N<3> | Default | d | 0.384 | |
PCIE_TBT_R2D_C_P<0> | Default | d | 0.387 | |
PCIE_TBT_R2D_C_P<1> | Default | d | 0.387 | |
PCIE_TBT_R2D_C_P<2> | Default | d | 0.387 | |
PCIE_TBT_R2D_C_P<3> | Default | d | 0.391 | |
PCIE_TBT_R2D_N<0> | Default | d | 0.395 | |
PCIE_TBT_R2D_N<1> | Default | d | 0.395 | |
PCIE_TBT_R2D_N<2> | Default | d | 0.395 | |
PCIE_TBT_R2D_N<3> | Default | d | 0.394 | |
PCIE_TBT_R2D_P<0> | Default | d | 0.394 | |
PCIE_TBT_R2D_P<1> | Default | d | 0.395 | |
PCIE_TBT_R2D_P<2> | Default | d | 0.392 | |
PCIE_TBT_R2D_P<3> | Default | d | 0.391 | |
PCIE_WAKE_L | Default | d | 0.516 | |
PCI_INTA_L | Default | d | 0.745 | |
PCI_INTB_L | Default | d | 0.737 | |
PCI_INTC_L | Default | d | 0.744 | |
PCI_INTD_L | Default | d | 0.748 | |
PEG_CLK100M_N | Default | d | 0.293 | |
PEG_CLK100M_P | Default | d | 0.296 | |
PEG_CLKREQ_L | Default | d | 0.576 | |
PEG_D2R_C_N<0> | Default | d | 0.365 | |
PEG_D2R_C_N<10> | Default | d | 0.359 | |
PEG_D2R_C_N<11> | Default | d | 0.357 | |
PEG_D2R_C_N<12> | Default | d | 0.358 | |
PEG_D2R_C_N<13> | Default | d | 0.357 | |
PEG_D2R_C_N<14> | Default | d | 0.358 | |
PEG_D2R_C_N<15> | Default | d | 0.356 | |
PEG_D2R_C_N<1> | Default | d | 0.358 | |
PEG_D2R_C_N<2> | Default | d | 0.366 | |
PEG_D2R_C_N<3> | Default | d | 0.358 | |
PEG_D2R_C_N<4> | Default | d | 0.367 | |
PEG_D2R_C_N<5> | Default | d | 0.360 | |
PEG_D2R_C_N<6> | Default | d | 0.363 | |
PEG_D2R_C_N<7> | Default | d | 0.358 | |
PEG_D2R_C_N<8> | Default | d | 0.367 | |
PEG_D2R_C_N<9> | Default | d | 0.359 | |
PEG_D2R_C_P<0> | Default | d | 0.366 | |
PEG_D2R_C_P<10> | Default | d | 0.359 | |
PEG_D2R_C_P<11> | Default | d | 0.358 | |
PEG_D2R_C_P<12> | Default | d | 0.358 | |
PEG_D2R_C_P<13> | Default | d | 0.357 | |
PEG_D2R_C_P<14> | Default | d | 0.359 | |
PEG_D2R_C_P<15> | Default | d | 0.357 | |
PEG_D2R_C_P<1> | Default | d | 0.359 | |
PEG_D2R_C_P<2> | Default | d | 0.366 | |
PEG_D2R_C_P<3> | Default | d | 0.358 | |
PEG_D2R_C_P<4> | Default | d | 0.368 | |
PEG_D2R_C_P<5> | Default | d | 0.360 | |
PEG_D2R_C_P<6> | Default | d | 0.365 | |
PEG_D2R_C_P<7> | Default | d | 0.359 | |
PEG_D2R_C_P<8> | Default | d | 0.370 | |
PEG_D2R_C_P<9> | Default | d | 0.359 | |
PEG_D2R_N<0> | Default | d | OL | |
PEG_D2R_N<10> | Default | d | 0.314 | |
PEG_D2R_N<11> | Default | d | 0.314 | |
PEG_D2R_N<12> | Default | d | 0.313 | |
PEG_D2R_N<13> | Default | d | 0.311 | |
PEG_D2R_N<14> | Default | d | 0.311 | |
PEG_D2R_N<15> | Default | d | 0.311 | |
PEG_D2R_N<1> | Default | d | 0.317 | |
PEG_D2R_N<2> | Default | d | OL | |
PEG_D2R_N<3> | Default | d | 0.316 | |
PEG_D2R_N<4> | Default | d | OL | |
PEG_D2R_N<5> | Default | d | 0.315 | |
PEG_D2R_N<6> | Default | d | OL | |
PEG_D2R_N<7> | Default | d | 0.313 | |
PEG_D2R_N<8> | Default | d | OL | |
PEG_D2R_N<9> | Default | d | 0.314 | |
PEG_D2R_P<0> | Default | d | OL | |
PEG_D2R_P<10> | Default | d | 0.314 | |
PEG_D2R_P<11> | Default | d | 0.314 | |
PEG_D2R_P<12> | Default | d | 0.312 | |
PEG_D2R_P<13> | Default | d | 0.312 | |
PEG_D2R_P<14> | Default | d | 0.130 | |
PEG_D2R_P<15> | Default | d | 0.311 | |
PEG_D2R_P<1> | Default | d | 0.316 | |
PEG_D2R_P<2> | Default | d | OL | |
PEG_D2R_P<3> | Default | d | 0.315 | |
PEG_D2R_P<4> | Default | d | OL | |
PEG_D2R_P<5> | Default | d | 0.315 | |
PEG_D2R_P<6> | Default | d | OL | |
PEG_D2R_P<7> | Default | d | 0.313 | |
PEG_D2R_P<8> | Default | d | OL | |
PEG_D2R_P<9> | Default | d | 0.314 | |
PEG_R2D_C_N<0> | Default | d | OL | |
PEG_R2D_C_N<10> | Default | d | OL | |
PEG_R2D_C_N<11> | Default | d | OL | |
PEG_R2D_C_N<12> | Default | d | OL | |
PEG_R2D_C_N<13> | Default | d | OL | |
PEG_R2D_C_N<14> | Default | d | OL | |
PEG_R2D_C_N<15> | Default | d | OL | |
PEG_R2D_C_N<1> | Default | d | OL | |
PEG_R2D_C_N<2> | Default | d | OL | |
PEG_R2D_C_N<3> | Default | d | OL | |
PEG_R2D_C_N<4> | Default | d | OL | |
PEG_R2D_C_N<5> | Default | d | OL | |
PEG_R2D_C_N<6> | Default | d | OL | |
PEG_R2D_C_N<7> | Default | d | OL | |
PEG_R2D_C_N<8> | Default | d | OL | |
PEG_R2D_C_N<9> | Default | d | OL | |
PEG_R2D_C_P<0> | Default | d | OL | |
PEG_R2D_C_P<10> | Default | d | OL | |
PEG_R2D_C_P<11> | Default | d | OL | |
PEG_R2D_C_P<12> | Default | d | OL | |
PEG_R2D_C_P<13> | Default | d | OL | |
PEG_R2D_C_P<14> | Default | d | OL | |
PEG_R2D_C_P<15> | Default | d | OL | |
PEG_R2D_C_P<1> | Default | d | OL | |
PEG_R2D_C_P<2> | Default | d | OL | |
PEG_R2D_C_P<3> | Default | d | OL | |
PEG_R2D_C_P<4> | Default | d | OL | |
PEG_R2D_C_P<5> | Default | d | OL | |
PEG_R2D_C_P<6> | Default | d | OL | |
PEG_R2D_C_P<7> | Default | d | OL | |
PEG_R2D_C_P<8> | Default | d | OL | |
PEG_R2D_C_P<9> | Default | d | OL | |
PEG_R2D_N<0> | Default | d | 0.394 | |
PEG_R2D_N<10> | Default | d | 0.393 | |
PEG_R2D_N<11> | Default | d | 0.395 | |
PEG_R2D_N<12> | Default | d | 0.395 | |
PEG_R2D_N<13> | Default | d | 0.394 | |
PEG_R2D_N<14> | Default | d | 0.396 | |
PEG_R2D_N<15> | Default | d | 0.397 | |
PEG_R2D_N<1> | Default | d | 0.394 | |
PEG_R2D_N<2> | Default | d | 0.393 | |
PEG_R2D_N<3> | Default | d | 0.394 | |
PEG_R2D_N<4> | Default | d | 0.395 | |
PEG_R2D_N<5> | Default | d | 0.395 | |
PEG_R2D_N<6> | Default | d | 0.393 | |
PEG_R2D_N<7> | Default | d | 0.394 | |
PEG_R2D_N<8> | Default | d | 0.394 | |
PEG_R2D_N<9> | Default | d | 0.394 | |
PEG_R2D_P<0> | Default | d | 0.396 | |
PEG_R2D_P<10> | Default | d | 0.395 | |
PEG_R2D_P<11> | Default | d | 0.393 | |
PEG_R2D_P<12> | Default | d | 0.393 | |
PEG_R2D_P<13> | Default | d | 0.394 | |
PEG_R2D_P<14> | Default | d | 0.394 | |
PEG_R2D_P<15> | Default | d | 0.393 | |
PEG_R2D_P<1> | Default | d | 0.395 | |
PEG_R2D_P<2> | Default | d | 0.394 | |
PEG_R2D_P<3> | Default | d | 0.393 | |
PEG_R2D_P<4> | Default | d | 0.394 | |
PEG_R2D_P<5> | Default | d | 0.394 | |
PEG_R2D_P<6> | Default | d | 0.392 | |
PEG_R2D_P<7> | Default | d | 0.394 | |
PEG_R2D_P<8> | Default | d | 0.394 | |
PEG_R2D_P<9> | Default | d | 0.395 | |
PGND_BKLT | Default | d | 0.000 | |
PLT_RESET_L | Default | d | 0.556 | |
PLT_RST_BUF_L | Default | d | 0.423 | |
PM_CLK32K_SUSCLK_R | Default | d | 0.697 | |
PM_CLKRUN_L | Default | d | 0.761 | |
PM_DSW_PWRGD | Default | d | 0.701 | |
PM_EN_ENET_L | Default | d | 0.578 | |
PM_EN_FET_P12V_S0 | Default | d | 0.582 | |
PM_EN_FET_P3V3_S0 | Default | d | 0.565 | |
PM_EN_FET_P3V3_S4 | Default | d | 0.502 | |
PM_EN_FET_P5V_S0 | Default | d | 0.448 | |
PM_EN_FET_REG_P1V5_S0 | Default | d | 0.546 | |
PM_EN_LDO_DDRVTT_S0 | Default | d | 0.542 | |
PM_EN_REG_CPUVCC_S0 | Default | d | 0.540 | |
PM_EN_REG_GPUCORE_S0 | Default | d | 0.541 | |
PM_EN_REG_GPU_VDDQ_S0 | Default | d | 0.517 | |
PM_EN_REG_P1V05_S0 | Default | d | 0.553 | |
PM_EN_REG_P1V05_S0_R | Default | d | 0.554 | |
PM_EN_REG_P3V3_S5 | Default | d | 0.518 | |
PM_EN_REG_P5V_S4 | Default | d | 0.508 | |
PM_EN_REG_VDDQ_S3 | Default | d | 0.504 | |
PM_EN_S0_R | Default | d | 0.492 | |
PM_EN_S4 | Default | d | 0.505 | |
PM_EN_USB_PWR | Default | d | 0.447 | |
PM_MEM_PWRGD | Default | d | 0.513 | |
PM_PCH_PWROK | Default | d | 0.501 | |
PM_PCH_SYS_PWROK | Default | d | 0.739 | |
PM_PCH_SYS_PWROK_R | Default | d | 0.542 | |
PM_PGOOD_FET_P12V_S0 | Default | d | 0.548 | |
PM_PGOOD_FET_P3V3_S0 | Default | d | 0.544 | |
PM_PGOOD_FET_P5V_S0 | Default | d | 0.564 | |
PM_PGOOD_FET_REG_P1V5_S0 | Default | d | 0.656 | |
PM_PGOOD_REG_CPUVCC_S0 | Default | d | 0.633 | |
PM_PGOOD_REG_GPU_P1V35_S0 | Default | d | 0.547 | |
PM_PGOOD_REG_GPU_VDDQ_S0 | Default | d | 0.546 | |
PM_PGOOD_REG_P1V05_S0 | Default | d | 0.536 | |
PM_PGOOD_REG_P3V3_S5 | Default | d | 0.536 | |
PM_PGOOD_REG_P5V_S4 | Default | d | 0.449 | |
PM_PGOOD_REG_VDDQ_S3 | Default | d | 0.572 | |
PM_PGOOD_SLP_S3_P1V05_S0 | Default | d | 0.692 | |
PM_PWRBTN_L | Default | d | 0.642 | |
PM_RSMRST_PCH_L | Default | d | 0.536 | |
PM_RSMRST_PCH_L_R | Default | d | 0.536 | |
PM_SLP_S3_BUF_L | Default | d | 0.566 | |
PM_SLP_S3_L | Default | d | 0.532 | |
PM_SLP_S4_L | Default | d | 0.657 | |
PM_SLP_S5_L | Default | d | 0.654 | |
PM_SLP_SUS_L | Default | d | 0.667 | |
PM_SYNC | Default | d | 0.390 | |
PM_SYSRST_L | Default | d | 0.672 | |
PM_THRMTRIP_L | Default | d | 0.136 | |
PM_THRMTRIP_L_R | Default | d | 0.524 | |
PP12V_ACDC | Default | d | 0.568 | |
PP12V_BKLT_FUSED | Default | d | 0.459 | |
PP12V_BKLT_SNS | Default | d | 0.459 | |
PP12V_G3H | Default | d | 0.568 | |
PP12V_LCD | Default | d | 0.464 | |
PP12V_LCD_F | Default | d | 0.465 | |
PP12V_S0 | Default | d | 0.459 | |
PP12V_S0_BKLT_FILT | Default | d | 0.459 | |
PP12V_S0_BKLT_PWR | Default | d | 0.169 | |
PP12V_S0_BKLT_PWR_R | Default | d | 0.167 | |
PP12V_S0_CPUVCC_FLT | Default | d | 0.463 | |
PP12V_S0_FAN_0_FILT | Default | d | 0.459 | |
PP12V_S0_FBVDDQ | Default | d | 0.463 | |
PP12V_S0_GPUCORE | Default | d | 0.461 | |
PP12V_S5 | Default | d | 0.541 | |
PP1V05_GPU_FB_DLL_AVDD | Default | d | 0.089 | |
PP1V05_GPU_FB_PLL_AVDD | Default | d | 0.090 | |
PP1V05_GPU_IFPD_IOVDD | Default | d | 0.090 | |
PP1V05_GPU_IFPEF_IOVDD | Default | d | 0.090 | |
PP1V05_GPU_PLLVDD | Default | d | 0.090 | |
PP1V05_GPU_SP_PLLVDD | Default | d | 0.089 | |
PP1V05_S0 | Default | d | 0.079 | |
PP1V05_S0 | Default | r | 78.500R | |
PP1V05_S0_PCH_VCC_CLK_F | Default | d | 0.079 | |
PP1V05_TBTCIO | Default | d | 0.176 | |
PP1V05_TBTLC | Default | d | 0.138 | |
PP1V2_ENET_INTREG | Default | d | 0.297 | |
PP1V2_ENET_PHY_AVDDL | Default | d | 0.297 | |
PP1V2_ENET_PHY_GPHYPLL | Default | d | 0.297 | |
PP1V2_ENET_PHY_PCIEPLL | Default | d | 0.297 | |
PP1V2_G3H_SMC_VDDC | Default | d | 0.520 | |
PP1V2_S4_CAMERA | Default | d | 0.337 | |
PP1V2_S4_CAMFILT | Default | d | 0.348 | |
PP1V2_S4_F_R | Default | d | 0.337 | |
PP1V5_S0 | Default | d | 0.142 | |
PP1V5_S0 | Default | r | 140.800 | |
PP1V5_S0_PCH | Default | d | 0.142 | |
PP1V5_S0_PCH | Default | r | 140.800 | |
PP1V8_S4_CAMERA | Default | d | 0.433 | |
PP1V8_S4_CAMERA_F | Default | d | 0.433 | |
PP3V3R1V8_ENET_LR_OUT | Default | d | 0.550 | |
PP3V3RHV_SW_TBTAPWR | Default | d | 0.562 | |
PP3V3RHV_SW_TBTBPWR | Default | d | 0.565 | |
PP3V3_DMIC_CONN | Default | d | 0.358 | |
PP3V3_ENET | Default | d | 0.366 | |
PP3V3_ENET_PHY_AVDDH | Default | d | 0.366 | |
PP3V3_ENET_PHY_BIASVDDH | Default | d | 0.366 | |
PP3V3_G3 | Default | d | 0.573 | |
PP3V3_G3H_AVREF_SMC | Default | d | 0.610 | |
PP3V3_G3H_BT_FLT | Default | d | 0.515 | |
PP3V3_G3H_SMC_VDDA | Default | d | 0.329 | |
PP3V3_GPU_IFPX_PLLVDD | Default | d | 0.364 | |
PP3V3_S0 | Default | d | 0.358 | |
PP3V3_S0_BKLT_VDDIO_R | Default | d | 0.359 | |
PP3V3_S0_SSD | Default | d | 0.453 | |
PP3V3_S0_SSD_FLT | Default | d | 0.453 | |
PP3V3_S0_SW_SD_PWR | Default | d | 0.564 | |
PP3V3_S3_VREFMRGN | Default | d | 0.341 | |
PP3V3_S4 | Default | d | 0.332 | |
PP3V3_S4_ALS_F | Default | d | 0.332 | |
PP3V3_S4_AP_FLT | Default | d | 0.501 | |
PP3V3_S4_CAMFILT | Default | d | 0.332 | |
PP3V3_S5 | Default | d | 0.145 | |
PP3V3_S5_XDP_R | Default | d | 0.107 | |
PP3V3_TBTLC | Default | d | 0.415 | |
PP3V42_G3H | Default | d | 0.329 | |
PP3V42_G3H_SMC_SPVSR | Default | d | 0.375 | |
PP4V5_AUDIO_ANALOG | Default | d | 0.503 | |
PP5V_AUDIO_HPAMP | Default | d | 0.410 | |
PP5V_S0 | Default | d | 0.410 | |
PP5V_S0_BKLT_R | Default | d | 0.408 | |
PP5V_S0_GFXIMVP_VDD | Default | d | 0.409 | |
PP5V_S0_HDD | Default | d | 0.600 | |
PP5V_S4 | Default | d | 0.158 | |
PP5V_S4_CAMERA_F | Default | d | 0.156 | |
PP5V_S4_EXTA_F | Default | d | 0.526 | |
PP5V_S4_EXTA_ILIM | Default | d | 0.526 | |
PP5V_S4_EXTB_F | Default | d | 0.525 | |
PP5V_S4_EXTB_ILIM | Default | d | 0.525 | |
PP5V_S4_EXTC_F | Default | d | 0.525 | |
PP5V_S4_EXTC_ILIM | Default | d | 0.525 | |
PP5V_S4_EXTD_F | Default | d | 0.523 | |
PP5V_S4_EXTD_ILIM | Default | d | 0.523 | |
PP5V_S5 | Default | d | 0.457 | |
PPCPUVCC_S0_CPU | Default | d | 0.018 | |
PPCPUVCC_S0_CPU | Default | r | 17.900R | |
PPCPUVCC_S0_SENSE_1 | Default | r | 17.900R | |
PPCPUVCC_S0_SENSE_2 | Default | r | 17.900R | |
PPCPUVCC_S0_SENSE_3 | Default | d | 0.018 | |
PPCPUVCC_S0_SENSE_3 | Default | r | 17.900R | |
PPCPUVCC_S0_SENSE_3 | Default | t | cpu removed 0.234 | |
PPDDRVTT_S0 | Default | d | 0.544 | |
PPHDD_S0 | Default | d | 0.600 | |
PPHV_SW_TBTAPWR | Default | d | 0.562 | |
PPHV_SW_TBTBPWR | Default | d | 0.565 | |
PPSSD_S0 | Default | d | 0.453 | |
PPVBATT_G3_RTC_R | Default | d | OL | |
PPVCCIO_S0_CPU | Default | d | 0.022 | |
PPVCCIO_S0_CPU | Default | r | 21.400R | |
PPVCOMP_S0_CPU | Default | d | 0.044 | |
PPVCORE_S0_GFX_PH1 | Default | d | 0.036 | |
PPVCORE_S0_GFX_PH1 | Default | r | 33.900R | |
PPVCORE_S0_GFX_PH2 | Default | d | 0.036 | |
PPVCORE_S0_GFX_PH2 | Default | r | 33.900R | |
PPVCORE_S0_GPU | Default | d | 0.036 | |
PPVCORE_S0_GPU | Default | r | 33.900R | |
PPVDDQ_S0_GPU | Default | d | 0.088 | |
PPVDDQ_S3 | Default | d | 0.321 | |
PPVDDQ_S3 | Default | r | 318.000 | |
PPVDDQ_S3_DDR | Default | r | 318.000 | |
PPVIN_S0_GFXIMVP_R | Default | d | 0.469 | |
PPVOUT_S0_PCH_DCPRTC | Default | d | 0.724 | |
PPVOUT_S5_PCH_DCPSUSBYP | Default | d | 0.419 | |
PPVOUT_S5_PCH_DCPSUSBYP_R | Default | d | 0.414 | |
PPVREF_S3_MEM_VREFCA_A | Default | d | 0.583 | |
PPVREF_S3_MEM_VREFCA_B | Default | d | 0.583 | |
PPVREF_S3_MEM_VREFDQ_A | Default | d | 0.582 | |
PPVREF_S3_MEM_VREFDQ_B | Default | d | 0.586 | |
PU_U8500 | Default | d | 0.715 | |
PWR_BTN_R | Default | d | 0.850 | |
Q6170_P_G | Default | d | OL | |
Q6170_P_S | Default | d | OL | |
REG_BOOT_CPUVCC_1 | Default | d | 0.606 | |
REG_BOOT_CPUVCC_1_RC | Default | d | 0.606 | |
REG_BOOT_CPUVCC_2 | Default | d | 0.608 | |
REG_BOOT_CPUVCC_2_RC | Default | d | 0.608 | |
REG_BOOT_CPUVCC_3 | Default | d | 0.607 | |
REG_BOOT_CPUVCC_3_RC | Default | d | 0.607 | |
REG_BOOT_GPUCORE_1 | Default | d | 0.548 | |
REG_BOOT_GPUCORE_1_RC | Default | d | 0.548 | |
REG_BOOT_GPUCORE_2 | Default | d | 0.549 | |
REG_BOOT_GPUCORE_2_RC | Default | d | 0.549 | |
REG_BOOT_GPUVDDQ | Default | d | 0.581 | |
REG_BOOT_GPUVDDQ_RC | Default | d | 0.582 | |
REG_BOOT_P1V05S0 | Default | d | 0.578 | |
REG_BOOT_P1V05S0_RC | Default | d | 0.578 | |
REG_BOOT_P3V3S5 | Default | d | 0.596 | |
REG_BOOT_P3V3S5_RC | Default | d | 0.596 | |
REG_BOOT_P5VS4 | Default | d | 0.600 | |
REG_BOOT_P5VS4_RC | Default | d | 0.600 | |
REG_BOOT_VDDQS3 | Default | d | 0.616 | |
REG_BOOT_VDDQS3_RC | Default | d | 0.616 | |
REG_CPUVCC_COMP | Default | d | 0.632 | |
REG_CPUVCC_DVC | Default | d | 0.631 | |
REG_CPUVCC_FB | Default | d | 0.572 | |
REG_CPUVCC_FDVID | Default | d | 0.632 | |
REG_CPUVCC_HFCOMP | Default | d | 0.608 | |
REG_CPUVCC_IMON | Default | d | 0.621 | |
REG_CPUVCC_IMON_R | Default | d | 0.677 | |
REG_CPUVCC_IMX | Default | d | 0.621 | |
REG_CPUVCC_MEMVRSEL | Default | d | 0.000 | |
REG_CPUVCC_NPSI | Default | d | 0.629 | |
REG_CPUVCC_PSICOMP | Default | d | 0.589 | |
REG_CPUVCC_RGND | Default | d | 0.013 | |
REG_CPUVCC_RGND | Default | r | 12.900R | |
REG_CPUVCC_RSET | Default | d | 0.628 | |
REG_CPUVCC_TM | Default | d | 0.606 | |
REG_CPUVCC_TMX | Default | d | 0.629 | |
REG_CPUVCC_VIN | Default | d | 0.661 | |
REG_CPUVCC_VRHOT_L | Default | d | 0.074 | |
REG_CPUVCC_VRHOT_L | Default | r | 73.200R | |
REG_CPUVCC_VSEN | Default | d | 0.031 | |
REG_CPUVCC_VSEN | Default | r | 30.000R | |
REG_GPUCORE_COMP | Default | d | 0.544 | |
REG_GPUCORE_COMP_R | Default | d | 0.544 | |
REG_GPUCORE_DPSLP_EN | Default | d | 0.547 | |
REG_GPUCORE_FB | Default | d | 0.337 | |
REG_GPUCORE_FB2 | Default | d | 0.544 | |
REG_GPUCORE_FB_GND_R | Default | d | OL | |
REG_GPUCORE_FB_SNS_R | Default | d | 0.387 | |
REG_GPUCORE_ISNS1_N | Default | d | 0.036 | |
REG_GPUCORE_ISNS1_N | Default | r | 33.900R | |
REG_GPUCORE_ISNS1_P | Default | d | 0.036 | |
REG_GPUCORE_ISNS1_P | Default | r | 33.900R | |
REG_GPUCORE_ISNS2_N | Default | d | 0.036 | |
REG_GPUCORE_ISNS2_N | Default | r | 33.900R | |
REG_GPUCORE_ISNS2_P | Default | d | 0.036 | |
REG_GPUCORE_ISNS2_P | Default | r | 33.900R | |
REG_GPUCORE_ISUMN | Default | d | 0.034 | |
REG_GPUCORE_ISUMN_R | Default | d | 0.396 | |
REG_GPUCORE_ISUMP | Default | d | 0.460 | |
REG_GPUCORE_ISUMP_C | Default | d | OL | |
REG_GPUCORE_NTC | Default | d | 0.543 | |
REG_GPUCORE_PSI_R_L | Default | d | 0.512 | |
REG_GPUCORE_RBIAS | Default | d | 0.546 | |
REG_GPUCORE_VR_TT_L | Default | d | 0.500 | |
REG_GPUCORE_VW | Default | d | 0.544 | |
REG_GPUVDDQ_FB | Default | d | 0.535 | |
REG_GPUVDDQ_FSEL | Default | d | 0.000 | |
REG_GPUVDDQ_OCSET | Default | d | 0.551 | |
REG_GPUVDDQ_RTN | Default | d | 0.540 | |
REG_GPUVDDQ_SET0 | Default | d | 0.552 | |
REG_GPUVDDQ_SET1 | Default | d | 0.549 | |
REG_GPUVDDQ_SET1_R | Default | d | 0.549 | |
REG_GPUVDDQ_SREF | Default | d | 0.548 | |
REG_GPUVDDQ_VO | Default | d | 0.550 | |
REG_ISENVCC_1_N | Default | r | 17.900R | |
REG_ISENVCC_1_NR | Default | d | 0.581 | |
REG_ISENVCC_1_P | Default | r | 17.900R | |
REG_ISENVCC_2_N | Default | r | 17.900R | |
REG_ISENVCC_2_NR | Default | d | 0.580 | |
REG_ISENVCC_2_P | Default | r | 17.900R | |
REG_ISENVCC_3_N | Default | d | 0.018 | |
REG_ISENVCC_3_N | Default | r | 17.900R | |
REG_ISENVCC_3_NR | Default | d | 0.581 | |
REG_ISENVCC_3_P | Default | d | 0.018 | |
REG_ISENVCC_3_P | Default | r | 17.900R | |
REG_ISEN_GPUCORE_1 | Default | d | 0.539 | |
REG_ISEN_GPUCORE_2 | Default | d | 0.540 | |
REG_LGATE_CPUVCC_1 | Default | d | 0.444 | |
REG_LGATE_CPUVCC_2 | Default | d | 0.440 | |
REG_LGATE_CPUVCC_3 | Default | d | 0.444 | |
REG_LGATE_GPUCORE_1 | Default | d | 0.469 | |
REG_LGATE_GPUCORE_2 | Default | d | 0.446 | |
REG_LGATE_GPUVDDQ | Default | d | 0.458 | |
REG_LGATE_P1V05S0 | Default | d | 0.465 | |
REG_LGATE_P3V3S5 | Default | d | 0.466 | |
REG_LGATE_P5VS4 | Default | d | 0.468 | |
REG_P1V05S0_FB | Default | d | 0.528 | |
REG_P1V05S0_FSEL | Default | d | 0.553 | |
REG_P1V05S0_OCSET | Default | d | 0.548 | |
REG_P1V05S0_RTN | Default | d | 0.530 | |
REG_P1V05S0_SREF | Default | d | 0.550 | |
REG_P1V05S0_VO | Default | d | 0.547 | |
REG_P3V3S5_FB | Default | d | 0.532 | |
REG_P3V3S5_FSET | Default | d | 0.537 | |
REG_P3V3S5_ISEN | Default | d | 0.538 | |
REG_P3V3S5_OCSET | Default | d | 0.537 | |
REG_P3V3S5_VOUT | Default | d | 0.140 | |
REG_P3V3S5_VOUT_R | Default | d | 1.122 | |
REG_P5VS4_FB | Default | d | 0.535 | |
REG_P5VS4_FSET | Default | d | 0.537 | |
REG_P5VS4_ISEN | Default | d | 0.543 | |
REG_P5VS4_OCSET | Default | d | 0.536 | |
REG_P5VS4_VOUT | Default | d | 0.154 | |
REG_P5VS4_VOUT_R | Default | d | 1.134 | |
REG_PHASE_CPUVCC_1 | Default | r | 17.900R | |
REG_PHASE_CPUVCC_2 | Default | r | 17.900R | |
REG_PHASE_CPUVCC_3 | Default | r | 17.900R | |
REG_PHASE_GPUCORE_1 | Default | d | 0.036 | |
REG_PHASE_GPUCORE_2 | Default | d | 0.036 | |
REG_PHASE_GPUVDDQ | Default | d | 0.088 | |
REG_PHASE_GPUVDDQ | Default | r | 87.000R | |
REG_PHASE_P1V05S0 | Default | d | 0.078 | |
REG_PHASE_P1V05S0 | Default | r | 77.400R | |
REG_PHASE_P1V05S0_L | Default | d | 0.079 | |
REG_PHASE_P3V3S5 | Default | d | 0.145 | |
REG_PHASE_P5VS4 | Default | d | 0.158 | |
REG_PHASE_VDDQS3 | Default | d | 0.320 | |
REG_PHASE_VDDQS3_L | Default | d | 0.321 | |
REG_PVCC_U7400 | Default | d | 0.410 | |
REG_PVCC_U7750 | Default | d | 0.412 | |
REG_PWM_CPUVCC_1 | Default | d | 0.533 | |
REG_PWM_CPUVCC_1_R | Default | d | 0.534 | |
REG_PWM_CPUVCC_2 | Default | d | 0.533 | |
REG_PWM_CPUVCC_2_R | Default | d | 0.532 | |
REG_PWM_CPUVCC_3 | Default | d | 0.532 | |
REG_PWM_CPUVCC_3_R | Default | d | 0.532 | |
REG_PWM_CPUVCC_4_R | Default | d | 0.409 | |
REG_SNUBBER_CPUVCC_1 | Default | d | OL | |
REG_SNUBBER_CPUVCC_2 | Default | d | OL | |
REG_SNUBBER_CPUVCC_3 | Default | d | OL | |
REG_SNUBBER_GPUCORE_1 | Default | d | OL | |
REG_SNUBBER_GPUCORE_2 | Default | d | OL | |
REG_SNUBBER_P1V05S0 | Default | d | OL | |
REG_SNUBBER_P3V3S5 | Default | d | OL | |
REG_SNUBBER_P5VS4 | Default | d | OL | |
REG_SNUBBER_VDDQS3 | Default | d | OL | |
REG_TD_1 | Default | d | 0.409 | |
REG_TD_2 | Default | d | 0.409 | |
REG_TD_3 | Default | d | 0.412 | |
REG_U7600_FCCM | Default | d | 0.544 | |
REG_U7600_FCCM_R | Default | d | OL | |
REG_UGATE_CPUVCC_1 | Default | d | 0.635 | |
REG_UGATE_CPUVCC_2 | Default | d | 0.631 | |
REG_UGATE_CPUVCC_3 | Default | d | 0.632 | |
REG_UGATE_GPUCORE_1 | Default | d | 0.502 | |
REG_UGATE_GPUCORE_2 | Default | d | 0.504 | |
REG_UGATE_P1V05S0 | Default | d | 0.605 | |
REG_UGATE_P1V05S0_R | Default | d | 0.605 | |
REG_UGATE_P3V3S5 | Default | d | 0.593 | |
REG_UGATE_P5VS4 | Default | d | 0.597 | |
REG_UGATE_VDDQS3 | Default | d | 0.780 | |
REG_UGATE_VDDQS3_R | Default | d | 0.604 | |
REG_V5IN_U7300 | Default | d | 0.159 | |
REG_VCC1_U7600 | Default | d | 0.511 | |
REG_VCC2_U7600 | Default | d | 0.458 | |
REG_VCC_U7000 | Default | d | 0.410 | |
REG_VCC_U7400 | Default | d | 0.418 | |
REG_VCC_U7750 | Default | d | 0.419 | |
REG_VDDQS3_MODE | Default | d | 0.488 | |
REG_VDDQS3_REFIN | Default | d | 0.688 | |
REG_VDDQS3_TRIP | Default | d | 0.751 | |
REG_VDDQS3_VDDQSNS | Default | d | 0.318 | |
REG_VDDQS3_VREF | Default | d | 0.631 | |
REG_VDDQS3_VTTREF | Default | d | 0.493 | |
REG_VIN_U7600 | Default | d | 0.538 | |
RTC_RESET_L | Default | d | 0.774 | |
RTC_RESET_L_R | Default | d | 0.625 | |
SATALED_R_L | Default | d | OL | |
SATARDRVR_EN | Default | d | 0.602 | |
SATA_HDD_D2R_C_N | Default | d | OL | |
SATA_HDD_D2R_C_P | Default | d | OL | |
SATA_HDD_D2R_N | Default | d | 0.384 | |
SATA_HDD_D2R_P | Default | d | 0.386 | |
SATA_HDD_R2D_C_N | Default | d | 0.392 | |
SATA_HDD_R2D_C_P | Default | d | 0.393 | |
SATA_HDD_R2D_N | Default | d | OL | |
SATA_HDD_R2D_P | Default | d | OL | |
SATA_PWR_L | Default | d | 0.609 | |
SDCONN_CLK | Default | d | 0.590 | |
SDCONN_CLK_R | Default | d | 0.590 | |
SDCONN_CMD | Default | d | 0.584 | |
SDCONN_DATA<0> | Default | d | 0.588 | |
SDCONN_DATA<1> | Default | d | 0.583 | |
SDCONN_DATA<2> | Default | d | 0.588 | |
SDCONN_DATA<3> | Default | d | 0.583 | |
SDCONN_DATA<4> | Default | d | 0.797 | |
SDCONN_DATA<5> | Default | d | 0.796 | |
SDCONN_DATA<6> | Default | d | 0.797 | |
SDCONN_DATA<7> | Default | d | 0.799 | |
SDCONN_DETECT_L | Default | d | 0.471 | |
SDCONN_ILIM_R | Default | d | OL | |
SDCONN_OC_L | Default | d | 0.532 | |
SDCONN_STATE_CHANGE | Default | d | 0.460 | |
SDCONN_WP | Default | d | 0.784 | |
SD_DETECT_LVL | Default | d | 0.470 | |
SLG_ENET_RESET_R_L | Default | d | 0.460 | |
SMBUS_PCH_CLK | Default | d | 0.506 | |
SMBUS_PCH_DATA | Default | d | 0.518 | |
SMB_0_S0_CLK | Default | d | 0.611 | |
SMB_0_S0_DATA | Default | d | 0.614 | |
SMB_1_S0_CLK | Default | d | 0.646 | |
SMB_1_S0_DATA | Default | d | 0.636 | |
SMB_2_S4_CLK | Default | d | 0.748 | |
SMB_2_S4_DATA | Default | d | 0.747 | |
SMB_3_CLK | Default | d | 0.758 | |
SMB_3_DATA | Default | d | 0.757 | |
SMB_ALS_F_SCL | Default | d | 0.747 | |
SMB_ALS_F_SDA | Default | d | 0.747 | |
SMB_DP_TCON_SCL | Default | d | 2.348 | |
SMB_DP_TCON_SDA | Default | d | 2.365 | |
SMB_ENET_SCL | Default | d | 0.738 | |
SMB_ENET_SDA | Default | d | 0.732 | |
SMC_ACDC_ID | Default | d | 0.750 | |
SMC_ASSERT_RTCRST | Default | d | 0.760 | |
SMC_CLK32K | Default | d | 0.710 | |
SMC_CPU_CATERR_L | Default | d | 0.259 | |
SMC_DEBUGPRT_EN_L | Default | d | 0.572 | |
SMC_DEBUGPRT_RX_L | Default | d | 0.676 | |
SMC_DEBUGPRT_TX_L | Default | d | 0.686 | |
SMC_DELAYED_PWRGD | Default | d | 0.642 | |
SMC_EXTAL | Default | d | 0.780 | |
SMC_FAN_0_CTL | Default | d | 0.748 | |
SMC_FAN_0_TACH | Default | d | 0.751 | |
SMC_G3_WAKESRC_EN | Default | d | 0.750 | |
SMC_GFX_OVERTEMP | Default | d | 0.694 | |
SMC_GFX_OVERTEMP_L | Default | d | 0.718 | |
SMC_GFX_OVERTEMP_Q | Default | d | 0.659 | |
SMC_GFX_THROTTLE_L | Default | d | 0.699 | |
SMC_LRESET_L | Default | d | 0.593 | |
SMC_MANUAL_RST_L | Default | d | 0.680 | |
SMC_ONOFF_L | Default | d | 0.752 | |
SMC_OOB1_D2R_L | Default | d | 0.676 | |
SMC_OOB1_R2D_L | Default | d | 0.751 | |
SMC_OOB1_R2D_R_L | Default | d | 1.279 | |
SMC_OOB2_D2R_L | Default | d | 0.751 | |
SMC_OOB2_R2D_L | Default | d | 0.751 | |
SMC_PECI_L | Default | d | 0.753 | |
SMC_PECI_L_R | Default | d | 0.753 | |
SMC_PME_S4_WAKE_L | Default | d | 0.618 | |
SMC_PM_G2_EN | Default | d | 0.580 | |
SMC_PM_PCH_SYS_PWROK | Default | d | 0.744 | |
SMC_PROCHOT | Default | d | 0.756 | |
SMC_RESET_L | Default | d | 0.592 | |
SMC_RESET_R_L | Default | d | 0.599 | |
SMC_ROMBOOT | Default | d | 1.740 | |
SMC_RUNTIME_SCI_L | Default | d | 0.699 | |
SMC_RX_L | Default | d | 0.756 | |
SMC_TCK | Default | d | 0.747 | |
SMC_TDI | Default | d | 0.747 | |
SMC_TDO | Default | d | 0.747 | |
SMC_THRMTRIP | Default | d | 0.753 | |
SMC_TMS | Default | d | 0.757 | |
SMC_TOPBLK_SWP_L | Default | d | 0.745 | |
SMC_VCCIO_CPU_DIV2 | Default | d | 0.728 | |
SMC_WAKE_SCI_L | Default | d | 0.556 | |
SMC_XTAL | Default | d | 0.766 | |
SMC_XTAL_R | Default | d | 0.770 | |
SMIA_CLK_P | Default | d | 0.660 | |
SMIA_DATA_N | Default | d | 0.468 | |
SML_PCH_0_CLK | Default | d | 0.645 | |
SML_PCH_0_DATA | Default | d | 0.652 | |
SNS1_ALERT_L | Default | d | 0.753 | |
SNS_ACDC_N | Default | d | 0.757 | |
SNS_ACDC_P | Default | d | 0.754 | |
SNS_GPUVDDQ_N | Default | d | 0.000 | |
SNS_GPUVDDQ_P | Default | d | 0.090 | |
SNS_GPUVDDQ_P | Default | r | 89.000R | |
SNS_GPU_CORE_N | Default | d | 0.000 | |
SNS_GPU_CORE_P | Default | d | 0.035 | |
SNS_GPU_PEX_IOVDD_N | Default | d | 0.000 | |
SNS_GPU_PEX_IOVDD_P | Default | d | 0.079 | |
SNS_GPU_PEX_IOVDD_P | Default | r | 77.900R | |
SNS_HDD_N | Default | d | 0.600 | |
SNS_HDD_P | Default | d | 0.600 | |
SNS_P12VG3H_N | Default | d | 0.568 | |
SNS_P12VG3H_P | Default | d | 0.568 | |
SNS_P12VS0_FBVDDQ_N | Default | d | 0.463 | |
SNS_P12VS0_FBVDDQ_P | Default | d | 0.463 | |
SNS_P12VS0_GPUCORE_N | Default | d | 0.461 | |
SNS_P12VS0_GPUCORE_P | Default | d | 0.461 | |
SNS_P1V5S0_N | Default | d | 0.142 | |
SNS_P1V5S0_N | Default | r | 140.800 | |
SNS_P1V5S0_P | Default | d | 0.142 | |
SNS_P1V5S0_P | Default | r | 140.800 | |
SNS_SSD_N | Default | d | 0.453 | |
SNS_SSD_P | Default | d | 0.453 | |
SNS_T1_1_N | Default | d | 0.779 | |
SNS_T1_1_P | Default | d | 0.786 | |
SNS_T1_2_N | Default | d | 0.757 | |
SNS_T1_2_P | Default | d | 0.756 | |
SNS_T2_1_N | Default | d | 0.671 | |
SNS_T2_2_N | Default | d | 0.671 | |
SNS_T2_2_P | Default | d | 0.673 | |
SNS_T2_3_N | Default | d | 0.671 | |
SNS_T2_DXN | Default | d | 0.671 | |
SNS_VCC_XW_N | Default | d | 0.000 | |
SNS_VCC_XW_N | Default | r | 1.000R | |
SNS_VCC_XW_P | Default | d | 0.018 | |
SNS_VDDQS3_DDR_N | Default | r | 318.000 | |
SNS_VDDQS3_DDR_P | Default | r | 318.000 | |
SPIROM_USE_MLB | Default | d | 0.638 | |
SPI_ALT_CLK | Default | d | 0.613 | |
SPI_ALT_CS_L | Default | d | 0.624 | |
SPI_ALT_MISO | Default | d | 0.533 | |
SPI_ALT_MOSI | Default | d | 0.581 | |
SPI_CLK | Default | d | 0.570 | |
SPI_CLK_R | Default | d | 0.553 | |
SPI_CS0_L | Default | d | 0.582 | |
SPI_CS0_R_L | Default | d | 0.564 | |
SPI_DESCRIPTOR_OVERRIDE_L | Default | d | 0.751 | |
SPI_DESCRIPTOR_OVERRIDE_R | Default | d | 0.789 | |
SPI_MISO | Default | d | 0.508 | |
SPI_MLB_CLK | Default | d | 0.608 | |
SPI_MLB_CS_L | Default | d | 0.612 | |
SPI_MLB_MISO | Default | d | 0.517 | |
SPI_MLB_MOSI | Default | d | 0.541 | |
SPI_MOSI | Default | d | 0.538 | |
SPI_MOSI_R | Default | d | 0.532 | |
SPI_SMC_CLK | Default | d | 0.624 | |
SPI_SMC_MISO | Default | d | 0.546 | |
SPI_SMC_MOSI | Default | d | 0.586 | |
SPI_WP_L | Default | d | 0.704 | |
SPKR_MATCH_DRV | Default | d | 0.741 | |
SPKR_MATCH_DRV_R | Default | d | 0.740 | |
SSD_CLKREQ_L | Default | d | 0.537 | |
SSD_D2R_N<0> | Default | d | 0.390 | |
SSD_D2R_N<1> | Default | d | 0.387 | |
SSD_D2R_P<0> | Default | d | 0.385 | |
SSD_D2R_P<1> | Default | d | 0.390 | |
SSD_EN | Default | d | 0.453 | |
SSD_R2D_C_N<0> | Default | d | OL | |
SSD_R2D_C_N<1> | Default | d | OL | |
SSD_R2D_C_P<0> | Default | d | OL | |
SSD_R2D_C_P<1> | Default | d | OL | |
SSD_R2D_N<0> | Default | d | 0.385 | |
SSD_R2D_N<1> | Default | d | 0.385 | |
SSD_R2D_P<0> | Default | d | 0.389 | |
SSD_R2D_P<1> | Default | d | 0.386 | |
SSD_RESET_L | Default | d | 0.596 | |
SYSCLK_CLK25M_ENET | Default | d | 0.488 | |
SYSCLK_CLK25M_ENET_R | Default | d | 0.456 | |
SYSCLK_CLK25M_SB | Default | d | 0.434 | |
SYSCLK_CLK25M_SB_R | Default | d | 0.564 | |
SYSCLK_CLK25M_TBT | Default | d | 0.440 | |
SYSCLK_CLK25M_TBT_R | Default | d | 0.669 | |
SYSCLK_CLK25M_X1 | Default | d | 0.451 | |
SYSCLK_CLK25M_X2 | Default | d | 0.454 | |
SYSCLK_CLK25M_X2_R | Default | d | 0.453 | |
TBTACONN_1_C | Default | d | OL | |
TBTACONN_20_RC | Default | d | 0.574 | |
TBTACONN_7_C | Default | d | OL | |
TBTAPWRSW_ISET_S0 | Default | d | 0.479 | |
TBTAPWRSW_ISET_S0_R | Default | d | OL | |
TBTAPWRSW_ISET_S3 | Default | d | 0.479 | |
TBTAPWRSW_ISET_S3_R | Default | d | OL | |
TBTAPWRSW_ISET_V3P3 | Default | d | 0.481 | |
TBTBCONN_1_C | Default | d | OL | |
TBTBCONN_20_RC | Default | d | 0.577 | |
TBTBCONN_7_C | Default | d | OL | |
TBTBPWRSW_ISET_S0 | Default | d | 0.450 | |
TBTBPWRSW_ISET_S0_R | Default | d | OL | |
TBTBPWRSW_ISET_S3 | Default | d | 0.479 | |
TBTBPWRSW_ISET_S3_R | Default | d | OL | |
TBTBPWRSW_ISET_V3P3 | Default | d | 0.482 | |
TBTPOCRST_CT | Default | d | 0.642 | |
TBTPOCRST_MR_L | Default | d | 0.668 | |
TBTROM_HOLD_L | Default | d | 0.745 | |
TBTROM_WP_L | Default | d | 0.743 | |
TBT_A_BIAS | Default | d | 0.770 | |
TBT_A_CIO_SEL | Default | d | 0.563 | |
TBT_A_CONFIG1_RC | Default | d | 0.839 | |
TBT_A_CONFIG2_RC | Default | d | 0.558 | |
TBT_A_D2R1_AUXDDC_N | Default | d | 0.701 | |
TBT_A_D2R1_AUXDDC_P | Default | d | 0.704 | |
TBT_A_D2R_C_N<0> | Default | d | 1.556 | |
TBT_A_D2R_C_N<1> | Default | d | OL | |
TBT_A_D2R_C_P<0> | Default | d | 1.818 | |
TBT_A_D2R_C_P<1> | Default | d | OL | |
TBT_A_D2R_N<0> | Default | d | 0.398 | |
TBT_A_D2R_N<1> | Default | d | 0.398 | |
TBT_A_D2R_P<0> | Default | d | 0.398 | |
TBT_A_D2R_P<1> | Default | d | 0.398 | |
TBT_A_DP_PWRDN | Default | d | 0.606 | |
TBT_A_HPD | Default | d | 0.841 | |
TBT_A_HV_EN | Default | d | 0.473 | |
TBT_A_LSRX | Default | d | 0.558 | |
TBT_A_LSRX_UNBUF | Default | d | 0.681 | |
TBT_A_LSTX | Default | d | 0.583 | |
TBT_A_R2D_C_N<0> | Default | d | 0.228 | |
TBT_A_R2D_C_N<1> | Default | d | 0.228 | |
TBT_A_R2D_C_P<0> | Default | d | 0.229 | |
TBT_A_R2D_C_P<1> | Default | d | 0.228 | |
TBT_A_R2D_N<0> | Default | d | OL | |
TBT_A_R2D_N<1> | Default | d | OL | |
TBT_A_R2D_P<0> | Default | d | OL | |
TBT_A_R2D_P<1> | Default | d | OL | |
TBT_B_BIAS | Default | d | 0.771 | |
TBT_B_CONFIG1_BUF | Default | d | 0.557 | |
TBT_B_CONFIG1_RC | Default | d | 0.841 | |
TBT_B_CONFIG2_RC | Default | d | 0.557 | |
TBT_B_D2R1_AUXDDC_N | Default | d | 0.705 | |
TBT_B_D2R1_AUXDDC_P | Default | d | 0.700 | |
TBT_B_D2R_C_N<0> | Default | d | OL | |
TBT_B_D2R_C_N<1> | Default | d | OL | |
TBT_B_D2R_C_P<0> | Default | d | OL | |
TBT_B_D2R_C_P<1> | Default | d | OL | |
TBT_B_D2R_N<0> | Default | d | 0.398 | |
TBT_B_D2R_N<1> | Default | d | 0.398 | |
TBT_B_D2R_P<0> | Default | d | 0.399 | |
TBT_B_D2R_P<1> | Default | d | 0.398 | |
TBT_B_DP_PWRDN | Default | d | 0.611 | |
TBT_B_HPD | Default | d | 0.842 | |
TBT_B_HV_EN | Default | d | 0.474 | |
TBT_B_LSRX | Default | d | 0.552 | |
TBT_B_R2D_C_N<0> | Default | d | 0.228 | |
TBT_B_R2D_C_N<1> | Default | d | 0.270 | |
TBT_B_R2D_C_P<0> | Default | d | 0.229 | |
TBT_B_R2D_C_P<1> | Default | d | 0.229 | |
TBT_B_R2D_N<0> | Default | d | OL | |
TBT_B_R2D_N<1> | Default | d | OL | |
TBT_B_R2D_P<0> | Default | d | OL | |
TBT_B_R2D_P<1> | Default | d | OL | |
TBT_CIO_PLUG_EVENT | Default | d | 0.558 | |
TBT_CIO_PLUG_EVENT_BUF | Default | d | 0.683 | |
TBT_CIO_PLUG_EVENT_ISOL | Default | d | 0.533 | |
TBT_CLKREQ_ISOL_L | Default | d | 0.464 | |
TBT_CLKREQ_L | Default | d | 0.447 | |
TBT_DDC_XBAR_EN_L | Default | d | 0.495 | |
TBT_EN_CIO_PWR | Default | d | 0.490 | |
TBT_EN_CIO_PWR_L | Default | d | 0.547 | |
TBT_EN_LC_ISOL | Default | d | 0.471 | |
TBT_EN_LC_PWR | Default | d | 0.557 | |
TBT_EN_LC_RC1V05 | Default | d | 0.466 | |
TBT_EN_LC_RC3V3 | Default | d | 0.698 | |
TBT_GO2SX_BIDIR | Default | d | 0.511 | |
TBT_GPIO_14 | Default | d | 0.560 | |
TBT_GPIO_9 | Default | d | 0.421 | |
TBT_MONOBSN | Default | d | 0.207 | |
TBT_MONOBSP | Default | d | 0.208 | |
TBT_PCIE_RESET_L | Default | d | 0.463 | |
TBT_PLT_RST_L | Default | d | 0.431 | |
TBT_PWR_EN | Default | d | 0.559 | |
TBT_PWR_EN_PCH | Default | d | 0.606 | |
TBT_PWR_ON_POC_RST_L | Default | d | 0.568 | |
TBT_RBIAS | Default | d | 0.800 | |
TBT_RSENSE | Default | d | 0.004 | |
TBT_SPI_CLK | Default | d | 0.562 | |
TBT_SPI_CS_L | Default | d | 0.665 | |
TBT_SPI_MISO | Default | d | 0.640 | |
TBT_SW_RESET_L | Default | d | 0.658 | |
TBT_TEST_EN | Default | d | 0.004 | |
TBT_TEST_PWR_GOOD | Default | d | 0.003 | |
TBT_TMU_CLK_IN | Default | d | 0.652 | |
TBT_TMU_CLK_OUT | Default | d | 0.560 | |
TMP006_DRDY | Default | d | OL | |
TP_AUD_LAMP_THERM | Default | d | 0.618 | |
TP_CLINK_CLK | Default | d | 0.570 | |
TP_CLINK_DATA | Default | d | 0.574 | |
TP_CLINK_RESET_L | Default | d | 0.632 | |
TP_CPU_CFG<12> | Default | d | 0.264 | |
TP_CPU_CFG<13> | Default | d | 0.262 | |
TP_CPU_RSVD_TP15 | Default | d | OL | |
TP_DMIC_SDA2 | Default | d | 0.708 | |
TP_PCH_SLP_LAN_L | Default | d | 0.693 | |
TP_PCH_SLP_WLAN_L | Default | d | 0.688 | |
TP_PCH_STRP_BBS1 | Default | d | 0.751 | |
TP_PCH_STRP_ESI_L | Default | d | 0.749 | |
TP_PCI_PME_L | Default | d | 0.547 | |
TP_PM_SLP_A_L | Default | d | 0.692 | |
TP_SMC_MD1 | Default | d | OL | |
TP_TBT_MONDC0 | Default | d | 0.370 | |
TP_TBT_MONDC1 | Default | d | 0.371 | |
TP_TBT_XTAL25OUT | Default | d | 0.292 | |
TP_XDP_PCH_TRST_L | Default | d | OL | |
UNCONNECTED_146 | Default | d | OL | |
UNCONNECTED_147 | Default | d | OL | |
USB2_EXTA_MUXED_N | Default | d | 0.651 | |
USB2_EXTA_MUXED_P | Default | d | 0.658 | |
USB2_EXTA_N | Default | d | 0.654 | |
USB2_EXTA_P | Default | d | 0.661 | |
USB2_EXTB_N | Default | d | 0.482 | |
USB2_EXTB_P | Default | d | 0.483 | |
USB2_EXTC_N | Default | d | 0.482 | |
USB2_EXTC_P | Default | d | 0.482 | |
USB2_EXTD_N | Default | d | 0.484 | |
USB2_EXTD_P | Default | d | 0.485 | |
USB3_EXTA_RX_F_N | Default | d | 0.390 | |
USB3_EXTA_RX_F_P | Default | d | 0.390 | |
USB3_EXTA_RX_N | Default | d | 0.390 | |
USB3_EXTA_RX_P | Default | d | 0.390 | |
USB3_EXTA_TX_C_N | Default | d | OL | |
USB3_EXTA_TX_C_P | Default | d | OL | |
USB3_EXTA_TX_F_N | Default | d | OL | |
USB3_EXTA_TX_F_P | Default | d | OL | |
USB3_EXTB_RX_F_N | Default | d | 0.390 | |
USB3_EXTB_RX_F_P | Default | d | 0.390 | |
USB3_EXTB_RX_N | Default | d | 0.390 | |
USB3_EXTB_RX_P | Default | d | 0.390 | |
USB3_EXTB_TX_C_N | Default | d | OL | |
USB3_EXTB_TX_C_P | Default | d | OL | |
USB3_EXTB_TX_F_N | Default | d | OL | |
USB3_EXTB_TX_F_P | Default | d | OL | |
USB3_EXTC_RX_F_N | Default | d | 0.390 | |
USB3_EXTC_RX_F_P | Default | d | 0.390 | |
USB3_EXTC_RX_N | Default | d | 0.390 | |
USB3_EXTC_RX_P | Default | d | 0.390 | |
USB3_EXTC_TX_C_N | Default | d | OL | |
USB3_EXTC_TX_C_P | Default | d | OL | |
USB3_EXTC_TX_F_N | Default | d | OL | |
USB3_EXTC_TX_F_P | Default | d | OL | |
USB3_EXTC_TX_N | Default | d | 0.390 | |
USB3_EXTD_RX_F_N | Default | d | 0.390 | |
USB3_EXTD_RX_F_P | Default | d | 0.390 | |
USB3_EXTD_RX_N | Default | d | 0.390 | |
USB3_EXTD_RX_P | Default | d | 0.390 | |
USB3_EXTD_TX_C_N | Default | d | OL | |
USB3_EXTD_TX_C_P | Default | d | OL | |
USB3_EXTD_TX_F_N | Default | d | OL | |
USB3_EXTD_TX_F_P | Default | d | OL | |
USB3_EXTD_TX_N | Default | d | 0.392 | |
USB3_EXTD_TX_P | Default | d | 0.390 | |
USB_BT_MUX_N | Default | d | 0.788 | |
USB_BT_MUX_P | Default | d | 0.788 | |
USB_BT_N | Default | d | 0.470 | |
USB_BT_P | Default | d | 0.476 | |
USB_CAMERA_P | Default | d | 0.476 | |
USB_EXTA_0_N | Default | d | 0.486 | |
USB_EXTA_0_P | Default | d | 0.484 | |
USB_EXTA_OC_L | Default | d | 0.478 | |
USB_EXTB_8_N | Default | d | 0.484 | |
USB_EXTB_8_P | Default | d | 0.479 | |
USB_EXTB_OC_L | Default | d | 0.490 | |
USB_EXTC_1_N | Default | d | 0.479 | |
USB_EXTC_1_P | Default | d | 0.479 | |
USB_EXTC_OC_L | Default | d | 0.480 | |
USB_EXTD_9_N | Default | d | 0.481 | |
USB_EXTD_9_P | Default | d | 0.481 | |
USB_EXTD_OC_L | Default | d | 0.478 | |
USB_ILIM1 | Default | d | 0.521 | |
USB_ILIM1_R | Default | d | OL | |
VBIAS_DAC | Default | d | 0.751 | |
VIDEO_ON | Default | d | 0.808 | |
VIDEO_ON_L | Default | d | 0.782 | |
VIDEO_ON_L_DLY | Default | d | 0.807 | |
VREFMRGN_CA_AB | Default | d | OL | |
VREFMRGN_CA_A_EN_RC | Default | d | OL | |
VREFMRGN_CA_A_RDIV | Default | d | OL | |
VREFMRGN_CA_B_EN | Default | d | OL | |
VREFMRGN_CA_B_EN_RC | Default | d | OL | |
VREFMRGN_CA_B_RDIV | Default | d | OL | |
VREFMRGN_DQ_A_EN_RC | Default | d | OL | |
VREFMRGN_DQ_A_RDIV | Default | d | OL | |
VREFMRGN_DQ_B | Default | d | OL | |
VREFMRGN_DQ_B_EN | Default | d | OL | |
VREFMRGN_DQ_B_EN_RC | Default | d | OL | |
VREFMRGN_DQ_B_RDIV | Default | d | OL | |
VREFMRGN_FRAMEBUF_BUF | Default | d | OL | |
VREFMRGN_MEMVREG_BUF | Default | d | OL | |
VSNS_CPUVCC | Default | d | 0.739 | |
VSNS_GPUCORE_ALT | Default | d | 0.749 | |
VSNS_HDDS0 | Default | d | 0.600 | |
VSNS_P12VG3H | Default | d | 0.742 | |
VSNS_P12VS0_FBVDDQ | Default | d | 0.741 | |
VSNS_P12VS0_GPUCORE | Default | d | 0.746 | |
VSNS_P1V05S0_PCH | Default | d | 0.749 | |
VSNS_P1V5S0 | Default | d | 0.750 | |
VSNS_P3V3S5 | Default | d | 0.748 | |
VSNS_VDDQS3_DDR | Default | d | 0.746 | |
VTTCLAMP_EN | Default | d | 0.596 | |
VTTCLAMP_L | Default | d | 0.544 | |
WOL_EN | Default | d | 0.590 | |
XDP_BPM_L<0> | Default | d | 0.258 | |
XDP_BPM_L<1> | Default | d | 0.259 | |
XDP_BPM_L<3> | Default | d | OL | |
XDP_BPM_L<5> | Default | d | 0.263 | |
XDP_BPM_L<6> | Default | d | 0.263 | |
XDP_BPM_L<7> | Default | d | 0.265 | |
XDP_CPURST_L | Default | d | 1.383 | |
XDP_CPU_PCH_TCK | Default | d | 0.897 | |
XDP_CPU_PCH_TMS | Default | d | 0.905 | |
XDP_CPU_PREQ_L | Default | d | 0.257 | |
XDP_CPU_PRESENT_L | Default | d | 1.256 | |
XDP_CPU_PWRBTN_L | Default | d | 0.640 | |
XDP_CPU_PWRGD | Default | d | 1.406 | |
XDP_CPU_TCK | Default | d | 0.052 | |
XDP_CPU_TCK | Default | r | 51.300R | |
XDP_CPU_TDI | Default | d | 0.273 | |
XDP_CPU_TDO | Default | d | 0.128 | |
XDP_CPU_TDO_PCH_TDI | Default | d | 0.875 | |
XDP_CPU_TMS | Default | d | 0.269 | |
XDP_CPU_TRST_L | Default | d | 0.054 | |
XDP_DA0_USB_EXTA_OC_L | Default | d | 0.486 | |
XDP_DA1_USB_EXTC_OC_L | Default | d | 0.490 | |
XDP_DA2_PCH_GPIO41 | Default | d | 0.540 | |
XDP_DA3_PCH_GPIO42 | Default | d | 0.542 | |
XDP_DB0_USB_EXTB_OC_L | Default | d | 0.488 | |
XDP_DB1_USB_EXTD_OC_L | Default | d | 0.480 | |
XDP_DB2_PCH_GPIO10 | Default | d | 0.539 | |
XDP_DB3_SDCONN_STATE_CHANGE_L | Default | d | 0.451 | |
XDP_DBRESET_L | Default | d | 0.676 | |
XDP_DC0_DP_AUXCH_ISOL_L | Default | d | 0.540 | |
XDP_DC1_SATARDRVR_EN | Default | d | 0.598 | |
XDP_DC2_PCH_GPIO36 | Default | d | 0.549 | |
XDP_DC3_JTAG_ISP_TCK | Default | d | 0.525 | |
XDP_DD0_PCH_GPIO16 | Default | d | 0.581 | |
XDP_DD1_PCH_GPIO49 | Default | d | 0.594 | |
XDP_DD2_ENET_CLKREQ_L | Default | d | 0.550 | |
XDP_DD3_AP_CLKREQ_L | Default | d | 0.464 | |
XDP_FC0_HDD_PWR_EN | Default | d | 0.535 | |
XDP_FC1_GPU_GOOD | Default | d | 0.554 | |
XDP_PCH_PWRBTN_L | Default | d | 0.432 | |
XDP_PCH_S5_PWRGD | Default | d | 1.547 | |
XDP_PCH_TCK | Default | d | 0.055 | |
XDP_PCH_TDI | Default | d | 0.081 | |
XDP_PCH_TDO | Default | d | 0.083 | |
XDP_PCH_TMS | Default | d | 0.082 | |
XDP_VR_READY | Default | d | 0.955 |
Component | Type | Value |
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