Netname | Condition | Type | Value | Comment |
---|---|---|---|---|
AGND_PMIC | Default | d | 0.000 | |
ALL_SYS_PWRGD | Default | d | 0.47 | |
ANI_VREF | Default | d | 0.48 | |
AP_CLKREQ_L | Default | d | 0.47 | |
AP_PCIE_DEV_WAKE | Default | d | 0.55 | |
AP_PCIE_WAKE_L | Default | d | 0.52 | |
AP_RESET_L | Default | d | 0.57 | |
AP_S0IX_WAKE_L | Default | d | 0.57 | |
AP_S0IX_WAKE_SEL | Default | d | 0.51 | |
AUD_LRCLK_A | Default | d | 0.53 | |
AUD_LRCLK_LEFT1 | Default | d | 0.534 | |
AUD_LRCLK_LEFT2 | Default | d | 0.535 | |
AUD_LRCLK_RIGHT2 | Default | d | 0.53 | |
AUD_PWR_EN | Default | d | 0.66 | |
AUD_SCLKA_LEFT1 | Default | d | 0.576 | |
AUD_SCLKA_LEFT2 | Default | d | 0.576 | |
AUD_SCLK_A | Default | d | 0.58 | |
AUD_SCLK_RIGHT2 | Default | d | 0.57 | |
AUD_SDOUT_A | Default | d | 0.53 | |
AUD_SDOUT_LEFT1 | Default | d | 0.534 | |
AUD_SDOUT_LEFT2 | Default | d | 0.534 | |
AUD_SDOUT_RIGHT1 | Default | d | 0.53 | |
AUD_SDOUT_RIGHT2 | Default | d | 0.53 | |
AUD_SPKRAMP_MODE | Default | d | 0.55 | |
AUD_SPKRAMP_MODE_LEFT2 | Default | d | 0.547 | |
AUD_SPKRAMP_MODE_RIGHT1 | Default | d | 0.56 | |
AUD_SPKRAMP_MODE_RIGHT2 | Default | d | 0.55 | |
BBPD_CON_DET_L | Default | d | 0.58 | |
BBPD_MISO_LS1V1 | Default | d | 0.12 | |
BBPD_PD_EN | Default | d | 0.54 | |
BBPD_PD_SEL_CC2 | Default | d | 0.60 | |
BBPD_RPD_EN | Default | d | 0.60 | |
BBPD_RX_L_TX_H | Default | d | 0.60 | |
BBPD_SPI_MISO | Default | d | 0.50 | |
BBPD_SPI_MISO_BUF | Default | d | 0.34 | |
BBPD_SPI_MOSI | Default | d | 0.63 | |
BBPD_VCONN1_EN | Default | d | 0.68 | |
BBPD_VCONN2_EN | Default | d | 0.68 | |
BBPD_VCONN_EN | Default | d | 0.587 | |
BKLT_EN_R | Default | d | 0.52 | |
BKLT_SCL_R | Default | d | 0.53 | |
BKLT_SD | Default | d | 0.60 | |
BKLT_SDA_R | Default | d | 0.53 | |
BKL_FB | Default | d | 0.63 | |
BTROM_HOLD_L | Default | d | 0.718 | |
BTROM_WP_L | Default | d | 0.720 | |
BT_SPI_CLK | Default | d | 0.589 | |
BT_SPI_CS_L | Default | d | 0.678 | |
BT_SPI_MOSI | Default | d | 0.585 | |
BT_UART_D2R | Default | d | 0.655 | |
BT_UART_R2D | Default | d | 0.660 | |
BT_UART_RTS_L | Default | d | 0.52 | |
CAMERA_PWR_EN | Default | d | 0.52 | |
CAMERA_RESET_L | Default | d | 0.47 | |
CHGR_ACIN | Default | d | 0.62 | |
CHGR_AMON | Default | d | 0.619 | |
CHGR_BGATE | Default | d | 0.67 | |
CHGR_BMON | Default | d | 0.62 | |
CHGR_BOOST_DH | Default | d | 0.90 | |
CHGR_BOOST_DL | Default | d | 0.46 | |
CHGR_BOOST_SW | Default | d | 0.472 | |
CHGR_BOOT1 | Default | d | 0.590 | |
CHGR_BOOT2 | Default | d | 0.619 | |
CHGR_BOOT2_RC | Default | d | 0.611 | |
CHGR_BUCK_DH | Default | d | 0.915 | |
CHGR_BUCK_DL | Default | d | 0.47 | |
CHGR_COMP | Default | d | 0.62 | |
CHGR_CSI_N | Default | d | 0.545 | |
CHGR_CSI_N | Default | r | 14.000R | |
CHGR_CSI_P | Default | d | 0.547 | |
CHGR_CSI_P | Default | r | 14.000R | |
CHGR_CSI_R_N | Default | d | 0.540 | |
CHGR_CSI_R_P | Default | d | 0.540 | |
CHGR_CSO_N | Default | d | 0.461 | |
CHGR_CSO_N | Default | r | 3.700R | |
CHGR_CSO_P | Default | d | 0.461 | |
CHGR_CSO_P | Default | r | 3.700R | |
CHGR_CSO_R_N | Default | d | 0.460 | |
CHGR_CSO_R_P | Default | d | 0.460 | |
CHGR_LDO_P3V0 | Default | d | 0.61 | |
CHGR_LDO_P5V0 | Default | d | 0.43 | |
CHGR_LDO_VDDA | Default | d | 0.436 | |
CHGR_LDO_VDDP | Default | d | 0.443 | |
CHGR_PHASE | Default | d | 0.452 | |
CHGR_PHASE1 | Default | d | 435.000 | |
CHGR_PHASE1 | Default | r | 127.000R | |
CHGR_PHASE2 | Default | d | 0.430 | |
CHGR_PHASE2 | Default | r | 127.000R | |
CPUBMONSNS_ALERT_L | Default | d | 0.763 | |
CPUCORE_SW1 | Default | d | 1.000 | |
CPUCORE_SW1 | Default | r | 1.600R | |
CPUCORE_SW2 | Default | d | 1.000 | |
CPUCORE_SW2 | Default | r | 1.600R | |
CPUCORE_SW3 | Default | d | 2.000 | |
CPUCORE_SW3 | Default | r | 1.700R | |
CPUGT_SW1 | Default | d | 3.000 | |
CPUGT_SW1 | Default | r | 5.000R | |
CPUGT_SW2 | Default | d | 3.000 | |
CPUGT_SW2 | Default | r | 5.000R | |
CPUTHMSNS_ADDR_SEL | Default | d | 0.004 | |
CPUTHMSNS_ALERT_L | Default | d | 0.699 | |
CPUTHMSNS_D2_N | Default | d | 0.75 | |
CPUTHMSNS_D2_P | Default | d | 0.75 | |
CPUTHMSNS_DUR_SEL | Default | d | 0.774 | |
CPUTHMSNS_TH_SEL | Default | d | 0.773 | |
CPUVR_BOOT1 | Default | d | 0.608 | |
CPUVR_BOOT2 | Default | d | 0.610 | |
CPUVR_COMP | Default | d | 0.615 | |
CPUVR_FB | Default | d | 0.588 | |
CPUVR_FB2 | Default | d | 0.628 | |
CPUVR_FCCM | Default | d | 0.60 | |
CPUVR_ISEN1 | Default | d | 0.633 | |
CPUVR_ISEN2 | Default | d | 0.634 | |
CPUVR_ISNS1_N | Default | d | 0.110 | |
CPUVR_ISNS1_P | Default | d | 0.110 | |
CPUVR_ISNS2_N | Default | d | 0.109 | |
CPUVR_ISNS2_P | Default | d | 0.109 | |
CPUVR_ISUMN_R | Default | d | 0.323 | |
CPUVR_ISUMP | Default | d | 0.520 | |
CPUVR_LGATE1 | Default | d | 0.432 | |
CPUVR_LGATE2 | Default | d | 0.433 | |
CPUVR_NTC | Default | d | 0.633 | |
CPUVR_PHASE1 | Default | d | 0.110 | |
CPUVR_PHASE1 | Default | r | 85.100R | |
CPUVR_PHASE2 | Default | d | 0.109 | |
CPUVR_PHASE2 | Default | r | 85.100R | |
CPUVR_PROG1 | Default | d | 0.62 | |
CPUVR_PROG2 | Default | d | 0.62 | |
CPUVR_PROG3 | Default | d | 0.63 | |
CPUVR_PWM1 | Default | d | 0.61 | |
CPUVR_PWM2 | Default | d | 0.61 | |
CPUVR_SWSA | Default | d | 11.000 | |
CPUVR_SWSA | Default | r | 16.700R | |
CPUVR_UGATE1 | Default | d | 0.540 | |
CPUVR_UGATE2 | Default | d | 0.541 | |
CPU_CATERR_L | Default | d | 0.32 | |
CPU_CFG<3> | Default | d | 0.33 | |
CPU_CFG_RCOMP | Default | d | 0.06 | |
CPU_DIMMA_VREFDQ | Default | d | 0.52 | |
CPU_DIMMB_VREFDQ | Default | d | 0.53 | |
CPU_DIMM_VREFCA | Default | d | 0.46 | |
CPU_PECI_R | Default | d | 0.325 | |
CPU_PROCHOT_L | Default | d | 0.23 | |
CPU_PWRGD | Default | d | 0.36 | |
CPU_PWR_DEBUG_L | Default | d | 0.33 | |
CPU_SM_RCOMP<0> | Default | d | 0.19 | |
CPU_SM_RCOMP<1> | Default | d | 0.12 | |
CPU_SM_RCOMP<2> | Default | d | 0.10 | |
CPU_VCCST_PWRGD | Default | d | 0.50 | |
CPU_VIDALERT_R_L | Default | d | 0.31 | |
CPU_VIDSCLK | Default | d | 0.23 | |
CPU_VIDSOUT | Default | d | 0.23 | |
CPU_VR_EN | Default | d | 0.32 | |
CPU_VR_READY | Default | d | 0.57 | |
DCINVSENS_EN_L | Default | d | 0.492 | |
DCIN_S5_VSENSE | Default | d | OL | |
DDRREG_DRVH | Default | d | 0.806 | |
DDRREG_DRVL | Default | d | 0.477 | |
DDRREG_LL | Default | d | 0.274 | |
DDRREG_VBST | Default | d | 0.613 | |
DDR_REG_ILIM | Default | d | 0.482 | |
DDR_VREF_CMD | Default | d | 0.43 | |
DDR_VREF_DATA | Default | d | 0.41 | |
DP_E85SNK_AUXCH_N | Default | d | 0.738 | |
DP_E85SNK_AUXCH_P | Default | d | 0.737 | |
DP_E85SNK_HPD | Default | d | 0.52 | |
DP_E85SNK_ML_N<0> | Default | d | 0.338 | |
DP_E85SNK_ML_N<1> | Default | d | 0.759 | |
DP_E85SNK_ML_N<2> | Default | d | OL | |
DP_E85SNK_ML_N<3> | Default | d | 0.34 | |
DP_E85SNK_ML_P<0> | Default | d | 0.338 | |
DP_E85SNK_ML_P<1> | Default | d | 0.754 | |
DP_E85SNK_ML_P<2> | Default | d | OL | |
DP_E85SNK_ML_P<3> | Default | d | 0.34 | |
DP_INT_AUX_N | Default | d | OL | |
DP_INT_AUX_P | Default | d | OL | |
DP_INT_HPD | Default | d | 0.79 | |
DP_INT_ML_N<0> | Default | d | OL | |
DP_INT_ML_N<1> | Default | d | OL | |
DP_INT_ML_N<2> | Default | d | OL | |
DP_INT_ML_N<3> | Default | d | OL | |
DP_INT_ML_P<0> | Default | d | OL | |
DP_INT_ML_P<1> | Default | d | OL | |
DP_INT_ML_P<2> | Default | d | OL | |
DP_INT_ML_P<3> | Default | d | OL | |
DP_TBTSNK0_AUXCH_C_N | Default | d | 0.444 | |
DP_TBTSNK0_AUXCH_C_P | Default | d | 0.445 | |
E85HSMUX_DPRDCI_EN | Default | d | 0.828 | |
E85HSMUX_DP_EN | Default | d | 0.619 | |
E85HSMUX_DP_EN_L | Default | d | 0.625 | |
E85HSMUX_HS_EN | Default | d | 0.60 | |
E85HSMUX_HS_FLIP | Default | d | 0.62 | |
E85HSMUX_USB_EN | Default | d | 0.60 | |
E85LSMUX_DEBUG_A_EN | Default | d | 0.505 | |
E85LSMUX_DEBUG_B_EN | Default | d | 0.506 | |
E85LSMUX_DEBUG_FLIP_L | Default | d | 0.494 | |
E85LSMUX_DX_FLIP | Default | d | 0.627 | |
E85LSMUX_HPM_SWD_EN | Default | d | 0.522 | |
E85LSMUX_M_EN | Default | d | 0.414 | |
E85LSMUX_M_SEL0 | Default | d | 0.417 | |
E85LSMUX_M_SEL1 | Default | d | 0.418 | |
E85LSMUX_RFU_EN_L | Default | d | 0.540 | |
E85LSMUX_SMC_SWD_EN | Default | d | 0.521 | |
E85_CC1 | Default | d | 0.556 | |
E85_CC2 | Default | d | 0.56 | |
E85_HS_DP_ML0_N | Default | d | 0.47 | |
E85_HS_DP_ML0_P | Default | d | 0.72 | |
E85_HS_DP_ML1_N | Default | d | 0.75 | |
E85_HS_DP_ML1_P | Default | d | 0.75 | |
E85_LS_DXDEBUG_RX_DAT | Default | d | 0.575 | |
E85_LS_DXDEBUG_TX_CLK | Default | d | 0.570 | |
E85_LS_MISSION_N | Default | d | 0.490 | |
E85_LS_MISSION_P | Default | d | 0.488 | |
E85_LS_N<1> | Default | d | 0.69 | |
E85_LS_N<2> | Default | d | 0.68 | |
E85_LS_P<1> | Default | d | 0.66 | |
E85_LS_P<2> | Default | d | 0.65 | |
E85_LS_RFUDEBUG_RX_DAT | Default | d | 0.583 | |
E85_LS_RFUDEBUG_TX_CLK | Default | d | 0.585 | |
E85_RFU<1> | Default | d | 0.67 | |
E85_RFU<2> | Default | d | 0.67 | |
E85_TEST_MODE_HPD | Default | d | 0.56 | |
E85_TEST_MODE_L | Default | d | 0.60 | |
EDP_BKLT_EN | Default | d | 0.42 | |
EDP_BKLT_PWM | Default | d | 0.66 | |
EDP_PANEL_PWR | Default | d | 0.65 | |
GFXIMVP_PHASE1 | Default | d | 1.000 | |
GFXIMVP_PHASE2 | Default | d | 1.000 | |
GFXIMVP_PHASE3 | Default | d | 1.000 | |
GFXIMVP_PHASE3 | Default | r | 1.800R | |
GPUFB_LL | Default | d | 207.000 | |
HDA_BIT_CLK | Default | d | 0.45 | |
HDA_RST_L | Default | d | 0.45 | |
HDA_SDIN0 | Default | d | 0.41 | |
HDA_SDOUT | Default | d | 0.45 | |
HDA_SYNC | Default | d | 0.45 | |
HPM_PIO0_7 | Default | d | 0.541 | |
HPM_POWER_GATE_EN | Default | d | 0.586 | |
HPM_RESET_L | Default | d | 0.65 | |
HPM_SWCLK | Default | d | 0.57 | |
HPM_SWCLK_R | Default | d | 0.572 | |
HPM_SWDIO_R | Default | d | 0.571 | |
HPM_SWITCH_EN_L | Default | d | 0.576 | |
HPM_UART_RX | Default | d | 0.54 | |
HPM_UART_TX | Default | d | 0.53 | |
HPM_VBUSFET_EN | Default | d | 0.586 | |
HPM_VBUS_VDET | Default | d | 0.575 | |
I2C_BKLT_SCL | Default | d | 0.52 | |
I2C_BKLT_SDA | Default | d | 0.53 | |
I2C_CAM_SCK | Default | d | 0.53 | |
I2C_CAM_SDA | Default | d | 0.76 | |
I2C_HPM_SCL | Default | d | 0.51 | |
I2C_HPM_SDA | Default | d | 0.53 | |
I2C_PCH_1_SCL | Default | d | 0.55 | |
I2C_PCH_1_SDA | Default | d | 0.550 | |
INLET_THMSNS_D1_N | Default | d | 0.75 | |
INLET_THMSNS_D1_P | Default | d | 0.75 | |
ISNS_1V2_S3_N | Default | d | 0.272 | |
ISNS_HS_COMPUTING_IOUT | Default | d | 0.709 | |
ISNS_HS_COMPUTING_N | Default | d | 0.460 | |
ISNS_HS_COMPUTING_P | Default | d | 0.460 | |
ISNS_HS_GAIN_N | Default | d | 0.66 | |
ISNS_HS_GAIN_OUT | Default | d | 0.710 | |
ISNS_HS_GAIN_P | Default | d | 0.346 | |
ISNS_LCDBKLT_N | Default | d | 0.46 | |
ISNS_LCDBKLT_P | Default | d | 0.46 | |
JTAG_WLAN_SEL | Default | d | 0.74 | |
JTAG_WLAN_TDI | Default | d | 0.76 | |
LCDBKLT_EN_L | Default | d | OL | |
LCD_IRQ_L | Default | d | 0.54 | |
LCD_PWR_SLEW | Default | d | 0.716 | |
LPC_PWRDWN_L | Default | d | 0.63 | |
MCP_EDP_RCOMP | Default | d | 0.18 | |
MCP_RSVD_CK13 | Default | d | 0.33 | |
MEM_A_ZQ_A | Default | d | 0.25 | |
MEM_A_ZQ_B | Default | d | 0.25 | |
MEM_B_CAA<0> | Default | d | 0.27 | |
MEM_B_CAA<2> | Default | d | 0.27 | |
MEM_B_CAA<3> | Default | d | 0.27 | |
MEM_B_CAB<1> | Default | d | 0.27 | |
MEM_B_CKE<1> | Default | d | 0.27 | |
MEM_B_CLK_N<0> | Default | d | 0.29 | |
MEM_B_CLK_P<0> | Default | d | 0.29 | |
MEM_B_CS_L<0> | Default | d | 0.27 | |
MEM_B_CS_L<1> | Default | d | 0.27 | |
MEM_B_DQ<0> | Default | d | 0.28 | |
MEM_B_DQS_N<0> | Default | d | 0.28 | |
MEM_B_DQS_P<0> | Default | d | 0.28 | |
MEM_B_ZQ_A | Default | d | 0.25 | |
MEM_B_ZQ_B | Default | d | 0.25 | |
MEM_CAM_A<8> | Default | d | 0.43 | |
MEM_CAM_CS_L | Default | d | 0.43 | |
MIPI_CLK_CONN_N | Default | d | 0.41 | |
MIPI_CLK_CONN_P | Default | d | 0.40 | |
MIPI_DATA_CONN_N | Default | d | 0.40 | |
MIPI_DATA_CONN_P | Default | d | 0.41 | |
NAND_OVERTMP_ALERT_L | Default | d | 0.590 | |
P0V8SLPDDR_SW0 | Default | d | 21.000 | |
P0V8SLPDDR_SW1 | Default | d | 21.000 | |
P0V9SLPDDR_SW0 | Default | d | 27.000 | |
P0V9SLPDDR_SW1 | Default | d | 27.000 | |
P0V9_LX0_SSD0 | Default | d | 251.000 | |
P0V9_LX1_SSD0 | Default | d | 250.000 | |
P1V05S0_EN | Default | d | 0.57 | |
P1V05S4SW_FB | Default | d | 0.777 | |
P1V05S4SW_PGOOD | Default | d | 0.769 | |
P1V05S4SW_SW | Default | d | 0.430 | |
P1V05SUS_DRVH | Default | d | 0.88 | |
P1V05SUS_DRVL | Default | d | 0.48 | |
P1V05SUS_LL | Default | d | 0.350 | |
P1V05_SUS_EN | Default | d | 0.48 | |
P1V05_SUS_IMON | Default | d | 0.45 | |
P1V05_SUS_MODE | Default | d | 0.48 | |
P1V05_SUS_PGOOD | Default | d | 0.50 | |
P1V05_SUS_PHASE | Default | d | 0.350 | |
P1V05_ULQ_L | Default | d | 0.570 | |
P1V1SLPS2R_SW0 | Default | d | 334.000 | |
P1V1SLPS2R_SW1 | Default | d | 333.000 | |
P1V1SSD_PGOOD | Default | d | 0.543 | |
P1V1SSD_PHASE | Default | d | 0.190 | |
P1V1SSD_SS | Default | d | 0.756 | |
P1V1SSD_VOS | Default | d | 0.203 | |
P1V1_SSD_REG_FB | Default | d | 1.408 | |
P1V2_CAM_SRVLXC_PHASE | Default | d | 0.335 | |
P1V2_PHASE | Default | d | 71.000 | |
P1V2_WLANBT_VLX | Default | d | 266.000 | |
P1V2_WLANBT_VLX | Default | r | 1.918k | |
P1V35_CAM_SRVLXD_PHASE | Default | d | 0.270 | |
P1V5S0_EN | Default | d | 0.55 | |
P1V5_WLANBT_VLX | Default | d | 300.000 | |
P1V8S3_PHASE | Default | d | 0.38 | |
P1V8SLPS2R_SW0 | Default | d | 378.000 | |
P1V8_LX0_SSD0 | Default | d | 327.000 | |
P2V5S3_REG | Default | d | 420.000 | |
P2V5_SW1_TPS62180_SSD0 | Default | d | 350.000 | |
P2V5_SW1_TPS62180_SSD1 | Default | d | 352.000 | |
P2V5_SW1_TPS62180_SSD1 | Default | v | 2.500 | |
P2V5_SW2_TPS62180_SSD0 | Default | d | 351.000 | |
P3V3G3HRTC_PHASE1 | Default | d | 403.000 | |
P3V3G3H_BOOT | Default | d | 0.586 | |
P3V3G3H_SW | Default | d | 0.39 | |
P3V3G3H_VSW | Default | d | 399.000 | |
P3V3S0_EN | Default | d | 0.55 | |
P3V3S0_PHASE | Default | d | 0.350 | |
P3V3S3_EN | Default | d | 0.48 | |
P3V3S5_PHASE | Default | d | 0.390 | |
P3V3SSD_PHASE | Default | d | 0.360 | |
P3V3_G3H_REG_FB | Default | d | 0.39 | |
P3V3_S0_EN | Default | d | 0.47 | |
P3V3_S0_IMON | Default | d | 0.45 | |
P3V3_S0_MODE | Default | d | 0.48 | |
P3V3_S0_PGOOD | Default | d | 0.50 | |
P3V3_S5_EN | Default | d | 0.48 | |
P3V3_S5_IMON | Default | d | 0.45 | |
P3V3_S5_MODE | Default | d | 0.48 | |
P5V1R3V4_AGND | Default | d | 0.003 | |
P5VG3S_VSW | Default | d | 381.000 | |
P5VOUT_EN | Default | d | 0.56 | |
P5VOUT_EN_L | Default | d | 0.622 | |
P5VOUT_FB | Default | d | 1.401 | |
P5VOUT_PGOOD | Default | d | 0.542 | |
P5VOUT_PHASE | Default | d | 0.480 | |
P5VOUT_SS | Default | d | 0.752 | |
P5VOUT_VOS | Default | d | 0.486 | |
P5VS0_BOOT | Default | d | 0.627 | |
P5VS0_EN | Default | d | 0.47 | |
P5VS0_PHASE | Default | d | 0.430 | |
P5VS4_PHASE | Default | d | 0.41 | |
P5VUSBCT_LL | Default | d | 473.000 | |
P5VUSBCT_R | Default | d | 472.000 | |
P5VUSBC_X_LL | Default | d | 479.000 | |
P5VUSBC_X_R | Default | d | 479.000 | |
P5V_S4_EN | Default | d | 0.48 | |
P5V_S4_IMON | Default | d | 0.45 | |
P5V_S4_MODE | Default | d | 0.48 | |
P5V_S4_PGOOD | Default | d | 0.48 | |
PAK_SMC_RESET | Default | d | 0.501 | |
PANEL_P5V_EN | Default | d | 0.569 | |
PBUSVSENS_EN_L | Default | d | 0.490 | |
PBUSVSENS_EN_L_DIV | Default | d | OL | |
PBUS_S0_VSENSE | Default | d | OL | |
PCH_BT_UART_CTS_L | Default | d | 0.480 | |
PCH_BT_UART_D2R | Default | d | 0.528 | |
PCH_BT_UART_R2D | Default | d | 0.537 | |
PCH_BT_UART_RTS_L | Default | d | 0.69 | |
PCH_CLK32K_PMIC | Default | d | 0.48 | |
PCH_INTRUDER_L | Default | d | 0.79 | |
PCH_INTVRMEN | Default | d | 0.79 | |
PCH_JTAGX | Default | d | 0.05 | |
PCH_OPI_COMP | Default | d | 0.05 | |
PCH_PCIEPHY_PC | Default | d | 0.51 | |
PCH_PCIE_RCOMP | Default | d | 0.78 | |
PCH_PMTEST_RST | Default | d | 0.40 | |
PCH_RTCRST_L | Default | d | 0.79 | |
PCH_SATAPHY_PC | Default | d | 0.500 | |
PCH_SATA_RCOMP | Default | d | 0.78 | |
PCH_SRTCRST_L | Default | d | 0.79 | |
PCH_STRP_TOPBLK_SWP_L | Default | d | 0.55 | |
PCH_TBT_PCIE_RESET_L | Default | d | 0.63 | |
PCH_UART1_D2R | Default | d | 0.51 | |
PCH_UART1_R2D | Default | d | 0.53 | |
PCH_UART_SSD_L_BT_H | Default | d | 0.528 | |
PCH_USB3PHY_PC | Default | d | 0.51 | |
PCIE_CLK100M_SSD_N | Default | d | 0.28 | |
PCIE_CLK100M_SSD_P | Default | d | 0.28 | |
PCIE_CLK100M_TBT_N | Default | d | 0.29 | |
PCIE_CLK100M_TBT_P | Default | d | 0.29 | |
PCIE_TBT_D2R_N<0> | Default | d | 0.38 | |
PCIE_TBT_D2R_P<0> | Default | d | 0.38 | |
PCIE_TBT_R2D_C_N<0> | Default | d | 0.37 | |
PCIE_TBT_R2D_C_P<0> | Default | d | 0.37 | |
PDCINVSENS_EN_L_DIV | Default | d | OL | |
PDCIN_E85_SS_DIV | Default | d | OL | |
PDDR_S3_PHASE | Default | d | 0.275 | |
PLT_RESET_L | Default | d | 0.52 | |
PMIC2_READY | Default | d | 0.49 | |
PMIC_ADC_EN | Default | d | 0.48 | |
PMIC_PWRBTN_L | Default | d | 0.48 | |
PMIC_V8_EN | Default | d | 0.46 | |
PMIC_VREF1V25 | Default | d | 0.478 | |
PMIC_VREF2V4 | Default | d | 0.484 | |
PMIC_VREF3V3 | Default | d | 0.432 | |
PMIC_VREF3V3_RC | Default | d | 0.425 | |
PM_BATLOW_L | Default | d | 0.53 | |
PM_CLK32K_SUSCLK_R | Default | d | 0.67 | |
PM_DSW_PWRGD | Default | d | 0.50 | |
PM_PCH_APWROK | Default | d | 0.52 | |
PM_PCH_PWROK | Default | d | 0.52 | |
PM_PCH_SYS_PWROK | Default | d | 0.50 | |
PM_PWRBTN_L | Default | d | 0.62 | |
PM_RSMRST_L | Default | d | 0.74 | |
PM_SLP_A_L | Default | d | 0.52 | |
PM_SLP_S0_L | Default | d | 0.46 | |
PM_SLP_S3_L | Default | d | 0.47 | |
PM_SLP_S4_L | Default | d | 0.49 | |
PM_SLP_S5_L | Default | d | 0.57 | |
PM_SLP_SUS_L | Default | d | 0.51 | |
PM_SYSRST_L | Default | d | 0.62 | |
PM_THRMTRIP_L | Default | d | 0.29 | |
PP0V675_CAM_VREF | Default | d | 0.56 | |
PP0V675_MEM_CAM_VREFCA | Default | d | 0.50 | |
PP0V82_SLPDDR | Default | d | 21.000 | |
PP0V95_S0_CPUVCCIO_REG_R | Default | d | 38.000 | |
PP0V95_S0_CPUVCCIO_REG_R | Default | r | 53.000R | |
PP0V9_SLPDDR | Default | d | 27.000 | |
PP0V9_SSD0 | Default | d | 252.000 | |
PP0V9_TBT_X_SVR | Default | d | 244.000 | |
PP0V9_TBT_X_SVR | Default | r | 646.000R | |
PP1V05_S0 | Default | d | 0.190 | |
PP1V05_S0SW_PCH_PCIE | Default | d | 0.30 | |
PP1V05_S0SW_PCH_SATA | Default | d | 0.325 | |
PP1V05_S0SW_PCH_USB3 | Default | d | 0.320 | |
PP1V05_S0SW_PCH_VCCSATA3PLL | Default | d | 0.325 | |
PP1V05_S0SW_PCH_VCCUSB3PLL | Default | d | 0.32 | |
PP1V05_S0_PCH_VCCACLKPLL | Default | d | 0.190 | |
PP1V05_S0_PCH_VCCACLKPLL_R | Default | d | 0.190 | |
PP1V05_S0_PCH_VCCAPLL_OPI | Default | d | 0.190 | |
PP1V05_S0_PCH_VCC_ICC | Default | d | 0.19 | |
PP1V05_S0_PCH_VCC_ICC_R | Default | d | 0.190 | |
PP1V05_S4SW | Default | d | 0.43 | |
PP1V05_SUS | Default | d | 0.35 | |
PP1V05_SUS_PCH_VCCAOSCSUS | Default | d | 0.34 | |
PP1V1_S0SW_SSD | Default | d | 0.190 | |
PP1V1_SLPS2R | Default | d | 334.000 | |
PP1V2_CAM | Default | d | 0.335 | |
PP1V2_CAM_PCIE_PVDD_FLT | Default | d | 0.346 | |
PP1V2_CAM_PCIE_VDD_FLT | Default | d | 0.346 | |
PP1V2_CAM_XTALPCIEVDD | Default | d | 0.346 | |
PP1V2_S0SW_SSD_COLD | Default | d | 0.30 | |
PP1V2_S0SW_SSD_HOT | Default | d | 0.34 | |
PP1V2_S3 | Default | d | 0.275 | |
PP1V2_S3 | Default | r | 128.000R | |
PP1V2_S3_CPUDDR | Default | d | 69.000 | |
PP1V2_S3_REG_R | Default | d | 71.000 | |
PP1V2_S5_SMC_VDDC | Default | d | 0.51 | |
PP1V2_WLANBT_C | Default | d | 266.000 | |
PP1V35_CAM | Default | d | 0.27 | |
PP1V35_DDR_CLK | Default | d | 0.27 | |
PP1V5R1V35_GPU_REG_R | Default | d | 207.000 | |
PP1V5_S0 | Default | d | 0.36 | |
PP1V8_CAM | Default | d | 0.50 | |
PP1V8_S0SW_SSD_COLD | Default | d | 0.35 | |
PP1V8_S0SW_SSD_HOT | Default | d | 0.50 | |
PP1V8_S0_GPU | Default | d | 233.000 | |
PP1V8_S3 | Default | d | 0.38 | |
PP1V8_SLPS2R | Default | d | 377.000 | |
PP1V8_SSD0 | Default | d | 327.000 | |
PP2V5_NAND_SSD0 | Default | d | 352.000 | |
PP2V5_NAND_SSD0 | Default | v | 2.500 | |
PP2V5_S0SW_SSD | Default | d | 0.44 | |
PP2V5_S3 | Default | d | 420.000 | |
PP3V0_S5_AVREF_SMC | Default | d | 0.58 | |
PP3V3R3V0_AON | Default | d | 0.32 | |
PP3V3_G3H | Default | d | 0.39 | |
PP3V3_G3H_KBD_F | Default | d | 0.39 | |
PP3V3_G3H_RTC_REG_R | Default | d | 403.000 | |
PP3V3_G3H_T | Default | d | 400.000 | |
PP3V3_S0 | Default | d | 0.35 | |
PP3V3_S0SW_LCD | Default | d | 0.65 | |
PP3V3_S0SW_S1X | Default | d | 0.59 | |
PP3V3_S0SW_SSD | Default | d | 0.36 | |
PP3V3_S0_CPUTHMSNS_R | Default | d | 0.39 | |
PP3V3_S4 | Default | d | 0.39 | |
PP3V3_S4_TPAD_F | Default | d | 0.40 | |
PP3V3_S5 | Default | d | 0.39 | |
PP3V3_S5_SMC_VDDA | Default | d | 0.38 | |
PP3V3_SUS | Default | d | 0.34 | |
PP5V1_S4SW | Default | d | 0.480 | |
PP5V1_S4SW_CC1 | Default | d | 0.55 | |
PP5V1_S4SW_CC2 | Default | d | 0.56 | |
PP5V_G3H_LDO | Default | d | 0.47 | |
PP5V_G3S | Default | d | 382.000 | |
PP5V_S0 | Default | d | 0.43 | |
PP5V_S0SW_LCD | Default | d | 0.57 | |
PP5V_S0_ALSCAM_F | Default | d | 0.43 | |
PP5V_S0_CPUVR_VDD | Default | d | 0.44 | |
PP5V_S0_KBD_F | Default | d | 0.42 | |
PP5V_S4 | Default | d | 0.41 | |
PP5V_S4_TPAD_F | Default | d | 0.45 | |
PPBUS_G3H | Default | d | 398.000 | |
PPBUS_G3H_SSD0_SNS | Default | d | 398.000 | |
PPBUS_G3H_TPAD_FLT | Default | d | 0.46 | |
PPBUS_G3H_TPAD_FUSED | Default | d | 0.46 | |
PPBUS_HS_OTH5V | Default | d | 399.000 | |
PPBUS_S0_LCDBKLT_FUSED | Default | d | 0.46 | |
PPBUS_S0_LCDBKLT_PWR_SW | Default | d | 0.44 | |
PPBUS_S5_HS_COMPUTING_ISNS | Default | d | 0.46 | |
PPBUS_SW_BKL | Default | d | 0.44 | |
PPBUS_SW_LCDBKLT_PWR | Default | d | 0.46 | |
PPDCIN_E85_SS | Default | d | 0.55 | |
PPDCIN_G3H | Default | d | 0.54 | |
PPDCIN_G3H_CHGR | Default | d | 534.000 | |
PPLCDBKLT_VDDA | Default | d | 0.43 | |
PPLCDBKLT_VDDD | Default | d | 0.42 | |
PPVBAT_G3H_CHGR_R | Default | d | 400.000 | |
PPVBAT_G3H_CHGR_REG | Default | d | 399.000 | |
PPVBAT_G3H_CONN | Default | d | 0.64 | |
PPVBUS_E85 | Default | d | 0.55 | |
PPVCCGT_CPU_PH1 | Default | d | 3.000 | |
PPVCCGT_CPU_PH1 | Default | r | 5.000R | |
PPVCCGT_CPU_PH2 | Default | d | 3.000 | |
PPVCCGT_CPU_PH2 | Default | r | 5.000R | |
PPVCCIO_S0_CPU | Default | d | 39.000 | |
PPVCCIO_S0_CPU | Default | r | 52.600R | |
PPVCCPRIMCORE_PRIM_REG | Default | d | 42.000 | |
PPVCCSA_CPU_R | Default | d | 11.000 | |
PPVCCSA_CPU_R | Default | r | 16.800R | |
PPVCC_CPU_PH1 | Default | d | 1.000 | |
PPVCC_CPU_PH1 | Default | r | 1.600R | |
PPVCC_CPU_PH2 | Default | d | 1.000 | |
PPVCC_CPU_PH2 | Default | r | 1.600R | |
PPVCC_CPU_PH3 | Default | d | 1.000 | |
PPVCC_CPU_PH3 | Default | r | 2.100R | |
PPVCC_S0_CPU | Default | d | 0.109 | |
PPVCC_S0_CPU_PH1 | Default | d | 0.110 | |
PPVCC_S0_CPU_PH1 | Default | r | 85.100R | |
PPVCC_S0_CPU_PH2 | Default | d | 0.109 | |
PPVCC_S0_CPU_PH2 | Default | r | 85.100R | |
PPVCOMP_S0_CPU | Default | d | 0.15 | |
PPVCORE_S0_GFX_PH1 | Default | d | 1.000 | |
PPVCORE_S0_GFX_PH2 | Default | d | 1.000 | |
PPVCORE_S0_GFX_PH3 | Default | d | 1.000 | |
PPVCORE_S0_GFX_PH3 | Default | r | 1.800R | |
PPVDDCI_S0_GPU | Default | d | 17.000 | |
PPVDDCPUSRAM_AWAKE | Default | d | 145.000 | |
PPVDDCPU_AWAKE | Default | d | 6.000 | |
PPVIN_G3H_P3V3G3H | Default | d | 0.52 | |
PPVIN_G3H_TPAD_FUSE | Default | d | 398.000 | |
PPVIN_S0SW_LCDBKLT | Default | d | 852.000 | |
PPVIN_S0_CPUVR_VIN | Default | d | 0.46 | |
PPVIN_SW_LCDBKLT_SW | Default | d | 852.000 | |
PPVOUT_S0_LCDBKLT | Default | d | 1158.000 | |
PPVOUT_S0_PCH_DCPRTC | Default | d | 0.70 | |
PPVREF_S3_MEM_VREFCA | Default | d | 0.45 | |
PPVREF_S3_MEM_VREFDQ_A | Default | d | 0.52 | |
PPVREF_S3_MEM_VREFDQ_B | Default | d | 0.27 | |
PPVRTC_G3H | Default | d | 0.48 | |
PVCCIO_PHASE | Default | d | 39.000 | |
PVCCIO_PHASE | Default | r | 53.000R | |
PVCCPRIMCORE_SW0 | Default | d | 42.000 | |
PVCCPRIMCORE_SW1 | Default | d | 42.000 | |
PVDDCPUAWAKE_SW0 | Default | d | 6.000 | |
PVDDCPUAWAKE_SW1 | Default | d | 6.000 | |
PVDDCPUAWAKE_SW2 | Default | d | 7.000 | |
PVDDCPUAWAKE_SW3 | Default | d | 6.000 | |
PVDDCPUSRAMAWAKE_SW0 | Default | d | 145.000 | |
PVIN_RFLDO_WLANBT_VLX | Default | d | 304.000 | |
PVIN_S0_P1V1SSD_RC | Default | d | 0.472 | |
PVIN_S4_P5VOUT_AIN | Default | d | 0.470 | |
QR_SWITCH_EN | Default | d | 0.52 | |
REG_PHASE_2V5S3 | Default | d | 420.000 | |
RF_0_ANT | Default | d | OL | |
RF_1_ANT | Default | d | - | |
R_AMP1_GAIN | Default | d | 0.60 | |
R_AMP2_GAIN | Default | d | 0.60 | |
S1X_DEBUG_UART_D2R | Default | d | 0.42 | |
S1X_DEBUG_UART_R2D | Default | d | 0.42 | |
S5_PWRGD | Default | d | 0.48 | |
SAK_PP1V8_REF_P1V | Default | d | 0.669 | |
SAK_SSD_COLD_BOOT_L | Default | d | 0.54 | |
SAK_SSD_P1V1_DISCHARGE_FB | Default | d | 0.001 | |
SAK_SSD_P1V2_EN | Default | d | 0.553 | |
SAK_SSD_P1V8_EN | Default | d | 0.553 | |
SAK_SSD_P3V3_DISCHARGE_FB | Default | d | 0.001 | |
SAK_SSD_PCIE_RESET_L | Default | d | 0.56 | |
SAK_SSD_PP1V1_EN | Default | d | 0.56 | |
SAK_SSD_SR_P1V2_EN | Default | d | 0.550 | |
SAK_SSD_SR_P1V8_EN | Default | d | 0.552 | |
SMBUS_PCH_CLK | Default | d | 0.57 | |
SMBUS_PCH_DATA | Default | d | 0.57 | |
SMBUS_SMC_0_S0_SCL | Default | d | 0.74 | |
SMBUS_SMC_0_S0_SDA | Default | d | 0.74 | |
SMBUS_SMC_1_S0_SCL | Default | d | 0.53 | |
SMBUS_SMC_1_S0_SDA | Default | d | 0.53 | |
SMBUS_SMC_2_G3_SCL | Default | d | 0.41 | |
SMBUS_SMC_2_G3_SDA | Default | d | 0.41 | |
SMBUS_SMC_3_SCL | Default | d | 0.74 | |
SMBUS_SMC_3_SDA | Default | d | 0.74 | |
SMBUS_SMC_5_G3_SCL | Default | d | 0.60 | |
SMBUS_SMC_5_G3_SDA | Default | d | 0.58 | |
SMC_ACTUATOR_DISABLE_L | Default | d | 0.74 | |
SMC_ADAPTER_EN | Default | d | 0.61 | |
SMC_BC_ACOK | Default | d | 0.61 | |
SMC_BMON_ISENSE | Default | d | 0.74 | |
SMC_CBC_ON | Default | d | 0.61 | |
SMC_CHGR_INT_L | Default | d | 0.60 | |
SMC_CLK12M_EN | Default | d | 0.46 | |
SMC_CLK32K_PMIC | Default | d | 0.69 | |
SMC_CPU_ISENSE | Default | d | 0.620 | |
SMC_DCIN_ISENSE | Default | d | 0.74 | |
SMC_DCIN_VSENSE | Default | d | 0.74 | |
SMC_DEBUGPRT_RX_L | Default | d | 0.515 | |
SMC_DEBUGPRT_TX_L | Default | d | 0.513 | |
SMC_HS_COMPUTING_ISENSE | Default | d | 0.74 | |
SMC_LID | Default | d | 0.75 | |
SMC_LRESET_L | Default | d | 0.52 | |
SMC_LSOC_RST | Default | d | 0.62 | |
SMC_ONOFF_L | Default | d | 0.75 | |
SMC_OOB1_R2D_L | Default | d | 0.576 | |
SMC_PBUS_VSENSE | Default | d | 0.74 | |
SMC_PCH_SUSACK_L | Default | d | 0.60 | |
SMC_PCH_SUSWARN_L | Default | d | 0.62 | |
SMC_PECI_L_R | Default | d | 0.749 | |
SMC_PME_S4_WAKE_L | Default | d | 0.49 | |
SMC_PROCHOT | Default | d | 0.74 | |
SMC_RESET_L | Default | d | 0.74 | |
SMC_RST_L | Default | d | 0.610 | |
SMC_SENSOR_PWR_EN | Default | d | 0.75 | |
SMC_SWCLK_R | Default | d | 0.626 | |
SMC_SWDIO_R | Default | d | 0.624 | |
SMC_TCK | Default | d | 0.62 | |
SMC_TDI | Default | d | 0.74 | |
SMC_TDO | Default | d | 0.46 | |
SMC_THRMTRIP | Default | d | 0.74 | |
SMC_TMS | Default | d | 0.62 | |
SMC_VCCIO_CPU_DIV2 | Default | d | 0.74 | |
SMC_WAKE_SCI_L | Default | d | 0.51 | |
SMC_WIFI_PWR_EN | Default | d | 0.45 | |
SPIROM_USE_MLB | Default | d | 0.52 | |
SPI_ALT_CLK | Default | d | 0.52 | |
SPI_ALT_CS_L | Default | d | 0.54 | |
SPI_ALT_IO<2> | Default | d | 0.52 | |
SPI_ALT_IO<3> | Default | d | 0.53 | |
SPI_ALT_MISO | Default | d | 0.52 | |
SPI_ALT_MOSI | Default | d | 0.53 | |
SPI_DESCRIPTOR_OVERRIDE | Default | d | 1.347 | |
SPI_DESCRIPTOR_OVERRIDE_L | Default | d | 0.751 | |
SPI_DESCRIPTOR_OVERRIDE_LS5V | Default | d | 0.609 | |
SPI_IO<2> | Default | d | 0.51 | |
SPI_IO<3> | Default | d | 0.52 | |
SPI_MLBROM_CS_L | Default | d | 0.65 | |
SPI_MLB_CLK | Default | d | 0.524 | |
SPI_MLB_CS_L | Default | d | 0.550 | |
SPI_MLB_IO<2> | Default | d | 0.511 | |
SPI_MLB_IO<3> | Default | d | 0.528 | |
SPI_MLB_MISO | Default | d | 0.502 | |
SPI_MLB_MOSI | Default | d | 0.529 | |
SPKRAMP_LOUT1_N | Default | d | 0.48 | |
SPKRAMP_LOUT1_P | Default | d | 0.49 | |
SPKRAMP_LOUT2_N | Default | d | 0.49 | |
SPKRAMP_LOUT2_P | Default | d | 0.49 | |
SPKRAMP_LT_OUTN | Default | d | 480.000 | |
SPKRAMP_LT_OUTP | Default | d | 481.000 | |
SPKRAMP_LW_OUTN | Default | d | 481.000 | |
SPKRAMP_LW_OUTP | Default | d | 479.000 | |
SPKRAMP_ROUT1_N | Default | d | 0.48 | |
SPKRAMP_ROUT1_P | Default | d | 0.48 | |
SPKRAMP_ROUT2_N | Default | d | 0.49 | |
SPKRAMP_ROUT2_P | Default | d | 0.49 | |
SPKRCONN_LT_OUTN | Default | d | 480.000 | |
SPKRCONN_LT_OUTP | Default | d | 481.000 | |
SPKRCONN_LW_OUTN | Default | d | 480.000 | |
SPKRCONN_LW_OUTP | Default | d | 479.000 | |
SPKRVNDR_L_ID | Default | d | OL | |
SPKRVNDR_R_ID | Default | d | OL | |
SSD_BOOT | Default | d | 0.62 | |
SSD_CLKREQ_L | Default | d | 0.49 | |
SSD_CORE_SHMOO<0> | Default | d | 0.45 | |
SSD_CORE_SHMOO<1> | Default | d | 0.50 | |
SSD_GPIO1_L | Default | d | 0.618 | |
SSD_GPIO2_L | Default | d | 0.615 | |
SSD_I2C_SCL | Default | d | 0.475 | |
SSD_I2C_SDA | Default | d | 0.466 | |
SSD_JTAG_MASTER_NRST | Default | d | 0.45 | |
SSD_JTAG_MASTER_TCK | Default | d | 0.45 | |
SSD_JTAG_MASTER_TDI | Default | d | 0.45 | |
SSD_JTAG_MASTER_TDO | Default | d | 0.49 | |
SSD_JTAG_MASTER_TMS | Default | d | 0.45 | |
SSD_P1V2_COLD_SW_CAP | Default | d | 0.707 | |
SSD_P1V8_COLD_SW_CAP | Default | d | 0.708 | |
SSD_PWR_EN | Default | d | 0.50 | |
SSD_RESET_L | Default | d | 0.52 | |
SSD_SPI_CS_L | Default | d | 0.47 | |
SSD_SPI_MISO | Default | d | 0.43 | |
SSD_SPI_MOSI | Default | d | 0.43 | |
SSD_SPI_SCLK | Default | d | 0.43 | |
SSD_SPI_SIO3 | Default | d | 0.668 | |
SSD_SPI_WP_L | Default | d | 0.601 | |
SSD_SR_EN_L | Default | d | 0.54 | |
SSD_UART_BOOT_L | Default | d | 0.44 | |
SSD_UART_D2R | Default | d | 0.471 | |
SSD_UART_R2D | Default | d | 0.468 | |
SYSCLK_CLK12M_SMC | Default | d | 0.47 | |
SYSCLK_CLK24M_CAMERA | Default | d | 0.46 | |
SYSCLK_CLK24M_SB | Default | d | 0.45 | |
SYSCLK_CLK24M_SB_R | Default | d | 0.57 | |
SYSCLK_CLK24M_X1 | Default | d | 0.455 | |
SYSCLK_CLK24M_X2 | Default | d | 0.455 | |
SYSCLK_CLK24M_X2_R | Default | d | 0.455 | |
SYSCLK_CLK32K_PMIC | Default | d | 0.44 | |
SYS_DETECT | Default | d | OL | |
SYS_DETECT_L | Default | d | 0.49 | |
TBT_CLKREQ_L | Default | d | 0.35 | |
TPAD_SPI_CLK_R | Default | d | 0.53 | |
TPAD_SPI_CS_L | Default | d | 0.55 | |
TPAD_SPI_IF_EN | Default | d | 0.53 | |
TPAD_SPI_INT_L | Default | d | 0.48 | |
TPAD_SPI_MISO_R | Default | d | 0.54 | |
TPAD_SPI_MOSI_R | Default | d | 0.52 | |
TP_IST_TRIGGER | Default | d | 0.33 | |
TP_IVR_ERROR | Default | d | 0.33 | |
TP_JTAG_WLAN_TCK | Default | d | 0.75 | |
TP_JTAG_WLAN_TDO | Default | d | 0.58 | |
TP_JTAG_WLAN_TRST | Default | d | 0.76 | |
TP_MCP_DC_A44 | Default | d | OL | |
TP_MCP_DC_C45 | Default | d | OL | |
TP_MCP_DC_CW1 | Default | d | 0.27 | |
TP_MCP_DC_CY3 | Default | d | 0.27 | |
TP_MCP_DC_CY44 | Default | d | 0.11 | |
TP_MCP_DC_D2 | Default | d | OL | |
TP_MCP_DC_F1 | Default | d | OL | |
TP_MCP_DC_H44 | Default | d | 0.50 | |
TP_MCP_RSVD_BJ14 | Default | d | 0.44 | |
TP_MCP_RSVD_BT15 | Default | d | 0.39 | |
TP_MCP_RSVD_Y18 | Default | d | 0.37 | |
TP_PCH_SLP_LAN_L | Default | d | 0.68 | |
TP_PCH_SLP_WLAN_L | Default | d | 0.68 | |
TP_SSD_JTAG_SLAVE_TCK | Default | d | 0.45 | |
TP_SSD_JTAG_SLAVE_TMS | Default | d | 0.45 | |
TS_HIPWR_EN | Default | d | 0.56 | |
TS_HOST_RST | Default | d | 0.625 | |
TS_POWER_GATE_EN | Default | d | 0.60 | |
UNCONNECTED_5 | Default | d | 0.490 | |
UNCONNECTED_6 | Default | d | 0.490 | |
UNUSED_ANI_VREF | Default | d | 0.68 | |
USB3_EXTA_D2R_N | Default | d | 0.39 | |
USB3_EXTA_D2R_P | Default | d | 0.39 | |
USB3_EXTA_R2D_N | Default | d | OL | |
USB3_EXTA_R2D_P | Default | d | OL | |
USB3_EXTD_R2D_N | Default | d | 0.755 | |
USB3_EXTD_R2D_P | Default | d | 0.758 | |
USB_EXTA_F_N | Default | d | 0.435 | |
USB_EXTA_F_P | Default | d | 0.436 | |
USB_EXTA_N | Default | d | 0.433 | |
USB_EXTA_P | Default | d | 0.433 | |
USB_HPM_R_N | Default | d | 0.522 | |
USB_HPM_R_P | Default | d | 0.522 | |
VBUSFET_EN | Default | d | 0.628 | |
VBUSFET_ILIM | Default | d | 0.537 | |
VCFET_ILIM1 | Default | d | 0.732 | |
VCFET_ILIM2 | Default | d | 0.732 | |
VR0V9_IND_TBT_X | Default | d | 245.000 | |
VR0V9_IND_TBT_X | Default | r | 651.000k | |
VRVDDCI_R | Default | d | 17.000 | |
VR_PHASE_GPU_VDDCI | Default | d | 17.000 | |
WLAN_ROM_CLK | Default | d | 0.677 | |
WLAN_ROM_CS | Default | d | 0.664 | |
WLAN_ROM_MISO | Default | d | 0.620 | |
WLAN_ROM_MOSI | Default | d | 0.677 | |
WLAN_ROM_ORG | Default | d | 0.690 | |
XDP_CPUPCH_TRST_L | Default | d | 0.30 | |
XDP_CPURST_L | Default | d | 1.51 | |
XDP_CPU_PRDY_L | Default | d | 0.30 | |
XDP_CPU_PREQ_L | Default | d | 0.30 | |
XDP_CPU_PRESENT_L | Default | d | 0.14 | |
XDP_CPU_PWRBTN_L | Default | d | 0.62 | |
XDP_CPU_TCK | Default | d | 0.06 | |
XDP_CPU_TDI | Default | d | 0.33 | |
XDP_CPU_TDO | Default | d | 0.23 | |
XDP_CPU_TMS | Default | d | 0.33 | |
XDP_CPU_VCCST_PWRGD | Default | d | 1.50 | |
XDP_DBRESET_L | Default | d | 0.63 | |
XDP_FW_PME_L | Default | d | 0.51 | |
XDP_JTAG_CPU_ISOL_L | Default | d | 0.71 | |
XDP_JTAG_ISP_TCK | Default | d | 0.50 | |
XDP_LPCPLUS_GPIO | Default | d | 0.51 | |
XDP_MLB_RAMCFG0 | Default | d | 0.50 | |
XDP_MLB_RAMCFG1 | Default | d | 0.50 | |
XDP_MLB_RAMCFG2 | Default | d | 0.50 | |
XDP_MLB_RAMCFG3 | Default | d | 0.50 | |
XDP_PCH_GPIO17 | Default | d | 0.49 | |
XDP_PCH_SATAPHY_PC | Default | d | 0.500 | |
XDP_PCH_TCK | Default | d | 0.33 | |
XDP_PCH_TDI | Default | d | 0.57 | |
XDP_PCH_TDO | Default | d | 0.37 | |
XDP_PCH_TMS | Default | d | 0.37 | |
XDP_SDCONN_STATE_CHANGE_L | Default | d | 0.51 | |
XDP_SYS_PWROK | Default | d | 0.50 | |
XDP_TRST_L | Default | d | 0.86 | |
XDP_USB_EXTA_OC_L | Default | d | 0.52 | |
XDP_USB_EXTB_OC_L | Default | d | 0.52 | |
XDP_USB_EXTC_OC_L | Default | d | 0.52 | |
XDP_USB_EXTD_OC_L | Default | d | 0.52 |
Component | Type | Value |
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