| Netname | Condition | Type | Value | Comment |
| 50_0_ANT | Default | d | 0.001 | |
| 50_1_ANT | Default | d | 0.001 | |
| 50_2_ANT | Default | d | 0.001 | |
| 5VG3S_VFB1_RR | Default | d | 0.609 | |
| ACT_GND | Default | d | 0.00 | |
| ADC1_REFCOMP | Default | d | OL | |
| ADC2_REFCOMP | Default | d | OL | |
| AGND_P1V8GPU | Default | d | 0.000 | |
| AGND_P2V5S3 | Default | d | 0.000 | |
| ALL_SYS_PWRGD | Default | d | 0.519 | |
| ALL_SYS_PWRGD_R | Default | d | 0.461 | |
| AON_SLEEP1_RESET_L | Default | d | 0.435 | |
| AP_PCIE_WAKE_L | Default | d | 0.533 | |
| AUD_CONN_HP_LEFT | Default | d | 0.57 | |
| AUD_CONN_HP_RIGHT | Default | d | 0.57 | |
| AUD_CONN_HP_SENSE_L | Default | d | 1.12 | |
| AUD_CONN_HP_SENSE_R | Default | d | 1.12 | |
| AUD_CONN_RING2 | Default | d | 0.00 | |
| AUD_CONN_RING2_XW | Default | d | 0.61 | |
| AUD_CONN_RING_SENSE | Default | d | 2.29 | |
| AUD_CONN_SLEEVE | Default | d | 0.00 | |
| AUD_CONN_SLEEVE_XW | Default | d | 0.61 | |
| AUD_CONN_TIP_SENSE | Default | d | OL | |
| AUD_DMIC0_CLK_CONN | Default | d | 0.518 | |
| AUD_DMIC0_DATA_CONN | Default | d | 0.52 | |
| AUD_DMIC1_CLK_CONN | Default | d | 0.47 | |
| AUD_DMIC1_DATA_CONN | Default | d | 0.52 | |
| AUD_HP_PORT_CH_GND | Default | d | 0.000 | |
| AUD_HP_PORT_L | Default | d | 0.703 | |
| AUD_HP_PORT_R | Default | d | 0.703 | |
| AUD_HS_MIC_N | Default | d | 0.628 | |
| AUD_HS_MIC_P | Default | d | 0.628 | |
| AUD_PWR_EN | Default | d | 0.776 | |
| AUD_RING_SENSE | Default | d | 0.642 | |
| AUD_TIP_SENSE | Default | d | 1.484 | |
| BKLT_EN_R | Default | d | 0.526 | |
| BKLT_PWM_KEYB | Default | d | 0.542 | |
| BKLT_PWM_MLB2TCON | Default | d | NA | |
| BKLT_SCL | Default | d | 0.537 | |
| BKLT_SD | Default | d | 0.587 | |
| BKLT_SDA | Default | d | 536.000 | |
| BKLT_SENSE_OUT | Default | d | 0.737 | |
| BTUARTMUX_OE_L | Default | d | 0.487 | |
| BTUARTMUX_SEL_PCH | Default | d | 0.477 | |
| BT_GPIO_3 | Default | d | 0.758 | |
| BT_GPIO_4 | Default | d | 0.730 | |
| BT_HOST_WAKE | Default | d | 0.488 | |
| BT_PWR_EN | Default | d | 0.490 | |
| BT_ROM_BOOT_HPN_L | Default | d | 0.586 | |
| BT_ROM_BOOT_L | Default | d | 0.480 | |
| BT_SFLASH_CS_L | Default | d | 0.702 | |
| BT_SFLASH_HOLD_L | Default | d | 0.711 | |
| BT_SFLASH_WP_L | Default | d | 0.710 | |
| BT_SPI2_CLK | Default | d | 0.686 | |
| BT_SPI2_CLK_R | Default | d | 0.639 | |
| BT_SPI2_CSN_R | Default | d | 0.599 | |
| BT_SPI2_MISO | Default | d | 0.689 | |
| BT_SPI2_MISO_R | Default | d | OL | |
| BT_SPI2_MOSI | Default | d | 0.685 | |
| BT_SPI2_MOSI_R | Default | d | OL | |
| CHGR_AUX_DET | Default | d | 0.635 | |
| CHGR_BGATE | Default | d | 0.636 | |
| CHGR_BMON | Default | d | 0.629 | |
| CHGR_BOOT1 | Default | d | 0.58 | |
| CHGR_BOOT1_RC | Default | d | 0.597 | |
| CHGR_BOOT2 | Default | d | 0.57 | |
| CHGR_BOOT2_RC | Default | d | 0.596 | |
| CHGR_COMP | Default | d | 0.61 | |
| CHGR_CSI_N | Default | d | 0.54 | |
| CHGR_CSI_N | Default | v | 20,000 | |
| CHGR_CSI_P | Default | d | 0.54 | |
| CHGR_CSI_P | Default | v | 20,000 | |
| CHGR_CSI_R_N | Default | d | 0.540 | |
| CHGR_CSI_R_N | Default | v | 20,000 | |
| CHGR_CSI_R_P | Default | d | 0.540 | |
| CHGR_CSI_R_P | Default | v | 20,000 | |
| CHGR_CSO_BMON_R_N | Default | d | OL | |
| CHGR_CSO_BMON_R_P | Default | d | OL | |
| CHGR_CSO_BMON_VREG | Default | d | OL | |
| CHGR_CSO_N | Default | d | 0.409 | |
| CHGR_CSO_N | Default | v | 12,600 | |
| CHGR_CSO_P | Default | d | 0.409 | |
| CHGR_CSO_P | Default | v | 12,600 | |
| CHGR_CSO_R_N | Default | d | 0.409 | |
| CHGR_CSO_R_N | Default | v | 12,600 | |
| CHGR_CSO_R_P | Default | d | 0.409 | |
| CHGR_CSO_R_P | Default | v | 12,600 | |
| CHGR_EN_MVR | Default | d | 0.612 | |
| CHGR_EN_MVR_R | Default | d | 0.59 | |
| CHGR_GATE_Q1 | Default | d | 0.944 | |
| CHGR_GATE_Q2 | Default | d | 0.470 | |
| CHGR_GATE_Q3 | Default | d | 0.471 | |
| CHGR_GATE_Q4 | Default | d | 0.720 | |
| CHGR_INT_L | Default | d | 0.614 | |
| CHGR_LX1 | Default | d | 0.47 | |
| CHGR_LX2 | Default | d | 0.47 | |
| CHGR_PHASE1 | Default | d | 0.466 | |
| CHGR_PHASE1 | Default | r | 223.800 | |
| CHGR_PHASE1 | Default | v | 12,600 | |
| CHGR_PHASE2 | Default | d | 0.466 | |
| CHGR_PHASE2 | Default | r | 223.800 | |
| CHGR_PHASE2 | Default | v | 12,600 | |
| CHGR_RST_IN | Default | d | 0.61 | |
| CHGR_RST_IN | Default | t | 0 volt is nomal | |
| CHGR_RST_IN_R | Default | d | OL | |
| CHGR_VBAT | Default | d | 0.62 | |
| CHGR_VDDA | Default | d | 0.44 | |
| CHGR_VDDP | Default | d | 0.44 | |
| CODEC_INT_L | Default | d | 0.493 | |
| CODEC_RESET_L | Default | d | 0.495 | |
| CODEC_WAKE_L | Default | d | 0.493 | |
| COMP_A_CPUCORE | Default | d | 0.625 | |
| COMP_A_CPUCORE_L | Default | d | OL | |
| COMP_B_CPUGT | Default | d | 0.624 | |
| COMP_B_CPUGT_L | Default | d | 0.630 | |
| COMP_C_CPUSA | Default | d | 0.624 | |
| COMP_C_CPUSA_L | Default | d | 1.967 | |
| CORE_ISUMN_R | Default | d | 1.007 | |
| CPUCORE_BOOT1 | Default | d | 0.609 | |
| CPUCORE_BOOT2 | Default | d | 0.610 | |
| CPUCORE_BOOT3 | Default | d | 0.607 | |
| CPUCORE_BP1 | Default | d | 0.610 | |
| CPUCORE_BP2 | Default | d | 0.607 | |
| CPUCORE_BP3 | Default | d | 0.607 | |
| CPUCORE_FCCM | Default | d | 0.598 | |
| CPUCORE_ISEN1 | Default | d | 0.625 | |
| CPUCORE_ISEN2 | Default | d | 0.626 | |
| CPUCORE_ISEN3 | Default | d | 0.626 | |
| CPUCORE_ISNS1_N | Default | d | 0.002 | |
| CPUCORE_ISNS1_N | Default | r | 2.100R | |
| CPUCORE_ISNS1_N | Default | v | 1,500 | |
| CPUCORE_ISNS1_P | Default | d | 0,002 | |
| CPUCORE_ISNS1_P | Default | r | 2.100R | |
| CPUCORE_ISNS1_P | Default | v | 1,500 | |
| CPUCORE_ISNS2_N | Default | d | 0.002 | |
| CPUCORE_ISNS2_N | Default | r | 2,100R | |
| CPUCORE_ISNS2_N | Default | v | 1,500 | |
| CPUCORE_ISNS2_P | Default | d | 0.002 | |
| CPUCORE_ISNS2_P | Default | r | 2,100R | |
| CPUCORE_ISNS2_P | Default | v | 1,500 | |
| CPUCORE_ISNS3_N | Default | d | 0.002 | |
| CPUCORE_ISNS3_N | Default | r | 2,100R | |
| CPUCORE_ISNS3_N | Default | v | 1,500 | |
| CPUCORE_ISNS3_P | Default | d | 0.002 | |
| CPUCORE_ISNS3_P | Default | r | 2,100R | |
| CPUCORE_ISNS3_P | Default | v | 1,500 | |
| CPUCORE_ISUMN | Default | d | 0.003 | |
| CPUCORE_ISUMN | Default | r | 2.800R | |
| CPUCORE_ISUMN_R | Default | d | 0.471 | |
| CPUCORE_ISUMP | Default | d | 0.382 | |
| CPUCORE_PHASE1 | Default | d | 0.000 | |
| CPUCORE_PHASE2 | Default | d | 0.000 | |
| CPUCORE_PHASE3 | Default | d | 0.000 | |
| CPUCORE_PROCHOT_R_L | Default | d | 0.525 | |
| CPUCORE_PSYS | Default | d | 0.623 | |
| CPUCORE_PWM1 | Default | d | 0.611 | |
| CPUCORE_PWM2 | Default | d | 0.611 | |
| CPUCORE_PWM3 | Default | d | 0.611 | |
| CPUCORE_SW1 | Default | d | 0.002 | |
| CPUCORE_SW1 | Default | r | 2.100R | |
| CPUCORE_SW1 | Default | v | 1,500 | |
| CPUCORE_SW1_SNUB | Default | d | OL | |
| CPUCORE_SW2 | Default | d | 0.002 | |
| CPUCORE_SW2 | Default | r | 2.100R | |
| CPUCORE_SW2 | Default | v | 1,500 | |
| CPUCORE_SW2_SNUB | Default | d | OL | |
| CPUCORE_SW3 | Default | d | 0.002 | |
| CPUCORE_SW3 | Default | r | 2.100R | |
| CPUCORE_SW3 | Default | v | 1,500 | |
| CPUCORE_SW3_SNUB | Default | d | OL | |
| CPUCORE_VIDALERT_R_L | Default | d | 0.284 | |
| CPUCORE_VIDSCLK_R | Default | d | 0.290 | |
| CPUCORE_VIDSOUT_R | Default | d | 0.245 | |
| CPUGT_BOOT1 | Default | d | 0.610 | |
| CPUGT_BOOT2 | Default | d | 0.609 | |
| CPUGT_BP1 | Default | d | 0.610 | |
| CPUGT_BP2 | Default | d | 0.609 | |
| CPUGT_FCCM | Default | d | 0.605 | |
| CPUGT_ISEN1 | Default | d | 0.626 | |
| CPUGT_ISEN2 | Default | d | 0.627 | |
| CPUGT_ISNS1_N | Default | d | 0.006 | |
| CPUGT_ISNS1_N | Default | r | 5,600R | |
| CPUGT_ISNS1_N | Default | v | 1,500 | |
| CPUGT_ISNS1_P | Default | d | 0.006 | |
| CPUGT_ISNS1_P | Default | r | 5,600R | |
| CPUGT_ISNS1_P | Default | v | 1,500 | |
| CPUGT_ISNS2_N | Default | d | 0.006 | |
| CPUGT_ISNS2_N | Default | r | 5,600R | |
| CPUGT_ISNS2_N | Default | v | 1,500 | |
| CPUGT_ISNS2_P | Default | d | 0.006 | |
| CPUGT_ISNS2_P | Default | r | 5,600R | |
| CPUGT_ISNS2_P | Default | v | 1,500 | |
| CPUGT_ISNS_N | Default | d | OL | |
| CPUGT_ISNS_P | Default | d | OL | |
| CPUGT_ISNS_R_N | Default | d | OL | |
| CPUGT_ISNS_R_P | Default | d | OL | |
| CPUGT_ISUMN | Default | d | 0.007 | |
| CPUGT_ISUMN | Default | r | 6.400R | |
| CPUGT_ISUMN_R | Default | d | 0.384 | |
| CPUGT_ISUMP | Default | d | 0.503 | |
| CPUGT_ISUM_IOUT | Default | d | OL | |
| CPUGT_PHASE1 | Default | d | 0.000 | |
| CPUGT_PHASE2 | Default | d | 0.000 | |
| CPUGT_PWM1 | Default | d | 0.611 | |
| CPUGT_PWM2 | Default | d | 0.611 | |
| CPUGT_SW1 | Default | d | 0.006 | |
| CPUGT_SW1 | Default | r | 5.600R | |
| CPUGT_SW1 | Default | v | 1,500 | |
| CPUGT_SW1_SNUB | Default | d | OL | |
| CPUGT_SW2 | Default | d | 0.006 | |
| CPUGT_SW2 | Default | r | 5,600R | |
| CPUGT_SW2 | Default | v | 1,500 | |
| CPUGT_SW2_SNUB | Default | d | OL | |
| CPUSAVSENSE_IN | Default | d | 0.025 | |
| CPUSAVSENSE_IN | Default | r | 23.200R | |
| CPUSA_BOOTSA | Default | d | 0.408 | |
| CPUSA_BPSA | Default | d | 0.620 | |
| CPUSA_FCCM | Default | d | 0.540 | |
| CPUSA_ISNS_N | Default | d | 0.022 | |
| CPUSA_ISNS_N | Default | r | 22,200R | |
| CPUSA_ISNS_N | Default | v | 1,150 | |
| CPUSA_ISNS_P | Default | d | 0.022 | |
| CPUSA_ISNS_P | Default | r | 22,200R | |
| CPUSA_ISNS_P | Default | v | 1,150 | |
| CPUSA_ISUMN | Default | d | 0.025 | |
| CPUSA_ISUMN | Default | r | 24.500R | |
| CPUSA_ISUMN_R | Default | d | 0.503 | |
| CPUSA_ISUMP | Default | d | 0.577 | |
| CPUSA_PHASESA | Default | d | 0.023 | |
| CPUSA_PWM | Default | d | 0.625 | |
| CPUSA_SW_SNUB | Default | d | OL | |
| CPUTHMSNS_ADD | Default | d | 0.639 | |
| CPUVR_ISNS_N | Default | d | OL | |
| CPUVR_ISNS_P | Default | d | OL | |
| CPUVR_ISNS_R_N | Default | d | OL | |
| CPUVR_ISNS_R_P | Default | d | OL | |
| CPUVR_ISUM_IOUT | Default | d | OL | |
| CPUVR_PGOOD | Default | d | 0.571 | |
| CPUVR_SWSA | Default | d | 0.022 | |
| CPUVR_SWSA | Default | r | 22.200R | |
| CPUVR_SWSA | Default | v | 1,150 | |
| CPUVSENSE_IN | Default | d | 0.000 | |
| CPU_C10_GATE_L | Default | d | 0.512 | |
| CPU_CATERR_L | Default | d | 0.228 | |
| CPU_CFG<0> | Default | d | 0.284 | |
| CPU_CFG<10> | Default | d | 0.283 | |
| CPU_CFG<11> | Default | d | 0.285 | |
| CPU_CFG<12> | Default | d | 0.284 | |
| CPU_CFG<13> | Default | d | 0.285 | |
| CPU_CFG<14> | Default | d | 0.284 | |
| CPU_CFG<15> | Default | d | 0.285 | |
| CPU_CFG<16> | Default | d | 0.287 | |
| CPU_CFG<17> | Default | d | 0.287 | |
| CPU_CFG<18> | Default | d | 0.286 | |
| CPU_CFG<19> | Default | d | 0.286 | |
| CPU_CFG<1> | Default | d | 0.284 | |
| CPU_CFG<2> | Default | d | 0.284 | |
| CPU_CFG<3> | Default | d | 0.284 | |
| CPU_CFG<4> | Default | d | 0.269 | |
| CPU_CFG<5> | Default | d | 0.268 | |
| CPU_CFG<6> | Default | d | 0.270 | |
| CPU_CFG<7> | Default | d | 0.285 | |
| CPU_CFG<8> | Default | d | 0.282 | |
| CPU_CFG<9> | Default | d | 0.283 | |
| CPU_CFG_RCOMP | Default | d | 0.051 | |
| CPU_CFG_RCOMP | Default | r | 50.100R | |
| CPU_DC_B2_C1 | Default | d | OL | |
| CPU_DC_B38_C38 | Default | d | OL | |
| CPU_DC_BR1_BR2 | Default | d | 0.341 | |
| CPU_DC_BR2_BR1 | Default | d | OL | |
| CPU_DC_C1_B2 | Default | d | OL | |
| CPU_DC_C38_B38 | Default | d | OL | |
| CPU_EDP_RCOMP | Default | d | 0.095 | |
| CPU_IST_TRIG | Default | d | 0.335 | |
| CPU_PCH_PM_DOWN | Default | d | 0.300 | |
| CPU_PCH_PM_DOWN_R | Default | d | 0.283 | |
| CPU_PCH_TRIGGER_R | Default | d | 0.280 | |
| CPU_PECI | Default | d | 0.403 | |
| CPU_PROCHOT_L | Default | d | 0.473 | |
| CPU_PROCHOT_OUT_L | Default | d | 0.489 | |
| CPU_PROCHOT_R_L | Default | d | 0.277 | |
| CPU_PWRGD | Default | d | 0.366 | |
| CPU_RESET_L | Default | d | 0.370 | |
| CPU_RSVD_AA14 | Default | d | 0.007 | |
| CPU_RSVD_AA14 | Default | r | 7.200R | |
| CPU_RSVD_AE29 | Default | d | 0.007 | |
| CPU_RSVD_AE29 | Default | r | 6.400R | |
| CPU_RSVD_N29 | Default | d | 0.007 | |
| CPU_RSVD_N29 | Default | r | 6.400R | |
| CPU_RSVD_R14 | Default | d | 0.007 | |
| CPU_RSVD_R14 | Default | r | 7.000R | |
| CPU_SMC_THRMTRIP_L | Default | d | 0.487 | |
| CPU_VCCGTSENSE_N | Default | d | 0.003 | |
| CPU_VCCGTSENSE_N | Default | r | 2.800R | |
| CPU_VCCGTSENSE_P | Default | d | 0.008 | |
| CPU_VCCGTSENSE_P | Default | r | 7.700R | |
| CPU_VCCIOSENSENEG_R | Default | d | 0.006 | |
| CPU_VCCIOSENSEPOS_R | Default | d | 0.156 | |
| CPU_VCCIOSENSE_N | Default | d | 0.000 | |
| CPU_VCCIOSENSE_P | Default | d | 0.087 | |
| CPU_VCCSASENSE_N | Default | d | 0.004 | |
| CPU_VCCSASENSE_N | Default | r | 3.300R | |
| CPU_VCCSASENSE_P | Default | d | 0.026 | |
| CPU_VCCSASENSE_P | Default | r | 25.500R | |
| CPU_VCCSENSE_N | Default | d | 0.004 | |
| CPU_VCCSENSE_N | Default | r | 3.300R | |
| CPU_VCCSENSE_P | Default | d | 0.005 | |
| CPU_VCCSENSE_P | Default | r | 4.700R | |
| CPU_VCCST_PWRGD | Default | d | 0.535 | |
| CPU_VIDALERT_L | Default | d | 0.272 | |
| CPU_VIDALERT_R_L | Default | d | 0.493 | |
| CPU_VIDSCLK | Default | d | 0.226 | |
| CPU_VIDSCLK_R | Default | d | 0.226 | |
| CPU_VIDSOUT | Default | d | 0.225 | |
| CPU_VIDSOUT | Default | r | 0.000R | |
| CPU_VIDSOUT_R | Default | d | 0.226 | |
| CPU_VR_EN_R | Default | d | 0.559 | |
| DBGLED_C10 | Default | d | OL | |
| DBGLED_GPU | Default | d | OL | |
| DBGLED_GPU_D | Default | d | OL | |
| DBGLED_S0I3 | Default | d | OL | |
| DBGLED_S0I3_D | Default | d | OL | |
| DBGLED_S5 | Default | d | OL | |
| DDR2V5_IOUT | Default | d | OL | |
| DDRREG_VTTSNS | Default | d | 0.126 | |
| DEBUG_CLKREQ_L | Default | d | 0.825 | |
| DEBUG_JTAG_SOC_TDI | Default | d | 0.495 | |
| DEBUG_JTAG_SOC_TDO | Default | d | 0.493 | |
| DFR_DISP_INT | Default | d | 0.46 | |
| DFR_DISP_RESET_L | Default | d | 0.46 | |
| DFR_DISP_TE | Default | d | 0.46 | |
| DFR_DISP_VSYNC | Default | d | OL | |
| DFR_LID_OPEN_L | Default | d | OL | |
| DFR_PWR_EN | Default | d | 0.45 | |
| DFR_PWR_EN_R | Default | d | 0.552 | |
| DFR_TOUCH_CLK32K_RESET_L | Default | d | 0.46 | |
| DFR_TOUCH_INT_L | Default | d | 0.45 | |
| DFR_TOUCH_RESET_L | Default | d | 0.46 | |
| DISP_GCON_INT_L | Default | d | 0.493 | |
| DISP_GCON_RESET_L | Default | d | 0.680 | |
| DISP_GCON_RESET_L_R | Default | d | 0.679 | |
| DP_INT_EG_HPD | Default | d | 0.427 | |
| DP_INT_EG_HPD_R | Default | d | 0.730 | |
| DP_INT_HPD | Default | d | 0.700 | |
| DP_INT_HPD_R | Default | d | 0.607 | |
| DP_INT_IG_HPD | Default | d | 0.611 | |
| DP_INT_IG_HPD_R | Default | d | 0.731 | |
| DP_TA_HPD | Default | d | 0.595 | |
| DP_TB_HPD | Default | d | 0.596 | |
| DP_T_SNK0_HPD | Default | d | 0.590 | |
| DP_T_SNK0_HPD_EG | Default | d | 0.412 | |
| DP_T_SNK1_HPD | Default | d | 0.590 | |
| DP_T_SNK1_HPD_EG | Default | d | 0.412 | |
| DP_XA_HPD | Default | d | 0.595 | |
| DP_XB_HPD | Default | d | 0.597 | |
| DP_X_SNK0_HPD | Default | d | 0.555 | |
| DP_X_SNK0_HPD_EG | Default | d | 0.414 | |
| DP_X_SNK1_HPD | Default | d | 0.589 | |
| DP_X_SNK1_HPD_EG | Default | d | 0.413 | |
| EADC1_CPUGT_ISENSE | Default | d | OL | |
| EADC1_CPUGT_VSENSE | Default | d | OL | |
| EADC1_CPUSA_ISENSE | Default | d | OL | |
| EADC1_CPUSA_VSENSE | Default | d | OL | |
| EADC1_LCDBKLT_ISENSE | Default | d | OL | |
| EADC1_LCDPANEL_ISENSE | Default | d | OL | |
| EADC1_TBT_X_ISENSE | Default | d | OL | |
| EADC1_VCCIO_ISENSE | Default | d | OL | |
| EADC2_DDR2V5_ISENSE | Default | d | OL | |
| EADC2_GPU_1V8_ISENSE | Default | d | OL | |
| EADC2_GPU_FBIC_ISENSE | Default | d | OL | |
| EADC2_GPU_VDDCI_VSENSE | Default | d | OL | |
| EADC2_PCH_1V0_ISENSE | Default | d | OL | |
| EADC2_PP3V3S5_T139_ISENSE | Default | d | OL | |
| EADC2_TBT_T_ISENSE | Default | d | OL | |
| EDP_BKLT_EN | Default | d | 0.526 | |
| EDP_INT_AUX_N | Default | d | 0.400 | |
| EDP_INT_AUX_P | Default | d | 0.400 | |
| EDP_INT_ML_N<0> | Default | d | 0.390 | |
| EDP_INT_ML_N<1> | Default | d | 0.390 | |
| EDP_INT_ML_N<2> | Default | d | 0.390 | |
| EDP_INT_ML_N<3> | Default | d | 0.390 | |
| EDP_INT_ML_P<0> | Default | d | 0.390 | |
| EDP_INT_ML_P<1> | Default | d | 390.000 | |
| EDP_INT_ML_P<2> | Default | d | 0.390 | |
| EDP_INT_ML_P<3> | Default | d | 0.390 | |
| EDP_MUXSEL_OVR | Default | d | 0.612 | |
| EDP_PANEL_PWR_BUF_EN | Default | d | 0.700 | |
| EDP_PANEL_PWR_DLY_EN | Default | d | 0.709 | |
| EDP_PANEL_PWR_EN | Default | d | 0.541 | |
| EG_BKLT_EN | Default | d | 0.413 | |
| EG_LCD_PWR_EN | Default | d | 0.411 | |
| EG_RESET_L_BUFF | Default | d | 0.514 | |
| EG_VR0_EN | Default | d | 0.523 | |
| EG_VR0_PGOOD | Default | d | 0.513 | |
| EG_VR1_EN | Default | d | 0.618 | |
| EG_VR2_EN | Default | d | 0.620 | |
| EG_VR3_EN | Default | d | 0.574 | |
| EG_VR4_EN | Default | d | 0.537 | |
| ESPI_CLK60M | Default | d | 0.488 | |
| ESPI_CLK60M_DBG | Default | d | OL | |
| ESPI_CLK60M_PCH | Default | d | 0.490 | |
| ESPI_CLK60M_PCH_R | Default | d | 0.507 | |
| ESPI_IO<0> | Default | d | 0.511 | |
| ESPI_IO<1> | Default | d | 0.520 | |
| ESPI_IO<2> | Default | d | 0.513 | |
| ESPI_IO<3> | Default | d | 0.513 | |
| ESPI_IO_PCH<0> | Default | d | 0.532 | |
| ESPI_IO_PCH<1> | Default | d | 0.533 | |
| ESPI_IO_PCH<2> | Default | d | 0.535 | |
| ESPI_IO_PCH<3> | Default | d | 0.539 | |
| ESPI_RESET_L | Default | d | 0.491 | |
| FAN_LT_PWM | Default | d | 0.77 | |
| FAN_LT_TACH | Default | d | OL | |
| FAN_LT_TACH | Default | v | 1.800 | |
| FAN_RT_PWM | Default | d | 0.82 | |
| FAN_RT_TACH | Default | d | OL | |
| FAN_RT_TACH | Default | v | 1.800 | |
| FBVDD_ALTVO | Default | d | 0.558 | |
| FB_A0_CLK_N | Default | d | 0.116 | |
| FB_A0_CLK_P | Default | d | 0.116 | |
| FB_A0_MF | Default | d | 0.121 | |
| FB_A0_SEN | Default | d | 0.121 | |
| FB_A0_VREFC | Default | d | 0.311 | |
| FB_A0_VREFD | Default | d | 0.582 | |
| FB_A0_ZQ | Default | d | 0.121 | |
| FB_A0_ZQ1 | Default | d | OL | |
| FB_A1_MF | Default | d | 0.121 | |
| FB_A1_SEN | Default | d | 0.120 | |
| FB_A1_VREFC | Default | d | 0.313 | |
| FB_A1_VREFD | Default | d | 0.590 | |
| FB_A1_ZQ | Default | d | 0.121 | |
| FB_A1_ZQ1 | Default | d | OL | |
| FB_A_CALR | Default | d | 0.463 | |
| FB_A_CORE_R | Default | d | 1.625 | |
| FB_A_CPUCORE | Default | d | 0.615 | |
| FB_A_CPUCORE_RC | Default | d | 1.184 | |
| FB_A_MVREFD | Default | d | 0.608 | |
| FB_A_RESET_L | Default | d | 0.471 | |
| FB_B0_CLK_N | Default | d | 0.115 | |
| FB_B0_CLK_P | Default | d | 0.115 | |
| FB_B0_MF | Default | d | 0.121 | |
| FB_B0_SEN | Default | d | 0.121 | |
| FB_B0_VREFC | Default | d | 0.312 | |
| FB_B0_VREFD | Default | d | 0.587 | |
| FB_B0_ZQ | Default | d | 0.121 | |
| FB_B0_ZQ1 | Default | d | OL | |
| FB_B1_CLK_N | Default | d | 0.116 | |
| FB_B1_CLK_P | Default | d | 0.116 | |
| FB_B1_MF | Default | d | 0.121 | |
| FB_B1_SEN | Default | d | 0.121 | |
| FB_B1_VREFC | Default | d | 0.311 | |
| FB_B1_VREFD | Default | d | 0.588 | |
| FB_B1_ZQ | Default | d | 0.121 | |
| FB_B1_ZQ1 | Default | d | OL | |
| FB_B_CALR | Default | d | 0.460 | |
| FB_B_CPUGT | Default | d | 0.597 | |
| FB_B_CPUGT_RC | Default | d | 1.169 | |
| FB_B_GT_R | Default | d | OL | |
| FB_B_MVREFD | Default | d | 0.688 | |
| FB_B_RESET_L | Default | d | 0.471 | |
| FB_B_RESET_PIN_L | Default | d | 0.432 | |
| FB_B_RESET_R_L | Default | d | 0.440 | |
| FB_CORE_R | Default | r | 4.700R | |
| FB_C_CPUSA | Default | d | 0.606 | |
| FB_C_CPUSA_RC | Default | d | 1.074 | |
| FB_C_SA_R | Default | d | 1.616 | |
| FB_GT_R | Default | d | 0.008 | |
| FB_GT_R | Default | r | 7.800R | |
| FB_SA_R | Default | d | 0.025 | |
| FB_SA_R | Default | r | 25.000R | |
| FB_SW_LEG | Default | d | 0.363 | |
| GFXIMVP_BOOT | Default | d | 0.609 | |
| GFXIMVP_BOOT1 | Default | d | 0.483 | |
| GFXIMVP_BOOT1_R | Default | d | 0.483 | |
| GFXIMVP_BOOT2 | Default | d | 0.483 | |
| GFXIMVP_BOOT2_R | Default | d | 0.483 | |
| GFXIMVP_BOOT_R | Default | d | 0.609 | |
| GFXIMVP_FCCM | Default | d | 0.407 | |
| GFXIMVP_ISEN1 | Default | d | 0.622 | |
| GFXIMVP_ISEN2 | Default | d | 0.622 | |
| GFXIMVP_ISEN3 | Default | d | 0.622 | |
| GFXIMVP_ISNS1_N | Default | d | 0.002 | |
| GFXIMVP_ISNS1_P | Default | d | 0.002 | |
| GFXIMVP_ISNS2_N | Default | d | 0.002 | |
| GFXIMVP_ISNS2_N | Default | r | 2.100R | |
| GFXIMVP_ISNS2_N | Default | v | 1,100 | |
| GFXIMVP_ISNS2_P | Default | d | 0.002 | |
| GFXIMVP_ISNS2_P | Default | r | 2.100R | |
| GFXIMVP_ISNS2_P | Default | v | 1,100 | |
| GFXIMVP_ISNS3_N | Default | d | 0,002 | |
| GFXIMVP_ISNS3_N | Default | r | 2.100R | |
| GFXIMVP_ISNS3_N | Default | v | 1,100 | |
| GFXIMVP_ISNS3_P | Default | d | 0,002 | |
| GFXIMVP_ISNS3_P | Default | r | 2.100R | |
| GFXIMVP_ISNS3_P | Default | v | 1,100 | |
| GFXIMVP_ISNS_N | Default | d | OL | |
| GFXIMVP_ISNS_P | Default | d | OL | |
| GFXIMVP_ISNS_R_N | Default | d | OL | |
| GFXIMVP_ISNS_R_P | Default | d | OL | |
| GFXIMVP_ISUMN | Default | d | 0.000 | |
| GFXIMVP_ISUMN_R | Default | d | 0.512 | |
| GFXIMVP_ISUMP | Default | d | 0.337 | |
| GFXIMVP_ISUMP_C | Default | d | OL | |
| GFXIMVP_LGATE1 | Default | d | 0.471 | |
| GFXIMVP_LGATE3 | Default | d | 0.431 | |
| GFXIMVP_PHASE1 | Default | d | 0.002 | |
| GFXIMVP_PHASE1 | Default | r | 2.100R | |
| GFXIMVP_PHASE1 | Default | v | 1,100 | |
| GFXIMVP_PHASE2 | Default | d | 0.002 | |
| GFXIMVP_PHASE2 | Default | r | 2.100R | |
| GFXIMVP_PHASE3 | Default | d | 0.002 | |
| GFXIMVP_PHASE3 | Default | r | 2.100R | |
| GFXIMVP_PHASE3 | Default | v | 1,100 | |
| GFXIMVP_Q1S1 | Default | d | 0.000 | |
| GFXIMVP_Q1S2 | Default | d | 0.000 | |
| GFXIMVP_Q1S3 | Default | d | 0.000 | |
| GFX_SELF_THROTTLE | Default | d | 0.406 | |
| GFX_SELF_THROTTLE_1V8 | Default | d | 0.473 | |
| GFX_THROTTLE_1V8_L | Default | d | 0.490 | |
| GFX_THROTTLE_1V8_R_L | Default | d | 0.706 | |
| GFX_THROTTLE_L | Default | d | 0.413 | |
| GMUX_IOEXP_ADDR_SEL | Default | d | 0.000 | |
| GND_5V3V3_AGND | Default | d | 0.000 | |
| GND_AUDIO_CODEC | Default | d | 0.000 | |
| GND_BKLT_SGND | Default | d | 0.000 | |
| GND_CALPE_AVSS | Default | d | 0.000 | |
| GND_FAN | Default | d | 0.00 | |
| GND_P3V3G3HRTC_AGND | Default | d | 0.00 | |
| GND_SMC_AVSS | Default | d | 0.000 | |
| GPUCOREVSENSE_IN | Default | d | 0.000 | |
| GPUFB_AGND | Default | d | 0.000 | |
| GPUFB_BOOT_RC | Default | d | 0.574 | |
| GPUFB_CS_N | Default | d | 0.053 | |
| GPUFB_CS_N | Default | r | 52.000R | |
| GPUFB_CS_N | Default | v | 1,350 | |
| GPUFB_CS_P | Default | d | 0.053 | |
| GPUFB_CS_P | Default | r | 52.000R | |
| GPUFB_CS_P | Default | v | 1,350 | |
| GPUFB_DRVH | Default | d | 0.557 | |
| GPUFB_DRVH_R | Default | d | 0.550 | |
| GPUFB_FSEL | Default | d | 0.559 | |
| GPUFB_GPU_OCSET_R | Default | d | 0.053 | |
| GPUFB_GPU_OCSET_R | Default | r | 54.500R | |
| GPUFB_GPU_VO_R | Default | d | 0.053 | |
| GPUFB_GPU_VO_R | Default | r | 52.200R | |
| GPUFB_LL | Default | d | 0.055 | |
| GPUFB_LL | Default | r | 54.400R | |
| GPUFB_LL | Default | v | 1,350 | |
| GPUFB_OCSET | Default | d | 0.556 | |
| GPUFB_PGOOD | Default | d | 0.481 | |
| GPUFB_RTN_DIV | Default | d | 0.541 | |
| GPUFB_SENSE_DIV | Default | d | 0.540 | |
| GPUFB_SET0 | Default | d | 0.559 | |
| GPUFB_SET1 | Default | d | 0.559 | |
| GPUFB_SET_R | Default | d | 0.559 | |
| GPUFB_SREF | Default | d | 0.556 | |
| GPUFB_VBST | Default | d | 0.577 | |
| GPUFB_VO | Default | d | 0.553 | |
| GPUVCORE_COMP | Default | d | 0.609 | |
| GPUVCORE_COMP_C | Default | d | OL | |
| GPUVCORE_EN | Default | d | 0.575 | |
| GPUVCORE_FB | Default | d | 0.572 | |
| GPUVCORE_FB2 | Default | d | 0.622 | |
| GPUVCORE_FB_R | Default | d | OL | |
| GPUVCORE_NTC | Default | d | 0.636 | |
| GPUVCORE_PGOOD | Default | d | 0.558 | |
| GPUVCORE_SENSE_N | Default | d | 0.000 | |
| GPUVCORE_SENSE_P | Default | d | 0.000 | |
| GPUVCORE_SVC | Default | d | 0.518 | |
| GPUVCORE_SVC_R | Default | d | 0.501 | |
| GPUVCORE_SVD | Default | d | 0.523 | |
| GPUVCORE_SVD_R | Default | d | 0.512 | |
| GPUVCORE_SVT | Default | d | 0.502 | |
| GPUVCORE_SVT_R | Default | d | 0.501 | |
| GPUVCORE_VR_HOT_L | Default | d | 0.430 | |
| GPUVDDC_PCC_ALERT_L | Default | d | 0.432 | |
| GPUVDDC_PCC_ALERT_R_L | Default | d | OL | |
| GPUVR_ISUM_IOUT | Default | d | OL | |
| GPUVR_ISUM_IOUT_R | Default | d | OL | |
| GPU_AUD<0> | Default | d | 0.407 | |
| GPU_AUD<1> | Default | d | 0.430 | |
| GPU_AUD_PORT_CONN<1> | Default | d | 0.460 | |
| GPU_AUD_PORT_CONN<2> | Default | d | 0.460 | |
| GPU_AUX_ZVSS | Default | d | 0.152 | |
| GPU_BIF_GEN3_EN_A | Default | d | 0.430 | |
| GPU_BP_0 | Default | d | 0.513 | |
| GPU_BP_1 | Default | d | 0.510 | |
| GPU_BRD_CFG<1> | Default | d | 0.462 | |
| GPU_CLKREQ_EN | Default | d | 0.481 | |
| GPU_CLKREQ_L | Default | d | 0.461 | |
| GPU_CLKREQ_L_R | Default | d | 0.496 | |
| GPU_CLK_IN | Default | d | 0.747 | |
| GPU_CLK_IN_R | Default | d | 0.726 | |
| GPU_CLK_YA740_OE | Default | d | 0.620 | |
| GPU_DBG_10 | Default | d | 0.470 | |
| GPU_DBG_11 | Default | d | 0.470 | |
| GPU_DBG_8 | Default | d | 0.469 | |
| GPU_DBG_9 | Default | d | 0.468 | |
| GPU_DIECRACKMON | Default | d | 0.001 | |
| GPU_DIECRACKMON | Default | r | 0.300R | |
| GPU_FB_SNS_COMMON_NEG | Default | d | 0.001 | |
| GPU_FB_SNS_COMMON_NEG | Default | r | 0.500R | |
| GPU_GFX_OVERTEMP | Default | d | 0.415 | |
| GPU_GFX_OVERTEMP_R | Default | d | 0.554 | |
| GPU_GPIO_SVC_R | Default | d | 0.485 | |
| GPU_GPIO_SVD_R | Default | d | 0.494 | |
| GPU_JTAG_TCK | Default | d | 0.415 | |
| GPU_JTAG_TDI | Default | d | 0.414 | |
| GPU_JTAG_TDO | Default | d | 0.417 | |
| GPU_JTAG_TMS | Default | d | 0.413 | |
| GPU_JTAG_TRST_L | Default | d | 0.416 | |
| GPU_MPLS_PS_0 | Default | d | 0.470 | |
| GPU_MPLS_PS_1 | Default | d | 0.469 | |
| GPU_MPLS_PS_2 | Default | d | 0.468 | |
| GPU_MPLS_PS_3 | Default | d | 0.470 | |
| GPU_PCIE_ZVSS | Default | d | 0.203 | |
| GPU_PLLCHARZ_H | Default | d | 0.318 | |
| GPU_PLLCHARZ_RC_H | Default | d | OL | |
| GPU_PLLCHARZ_RC_L | Default | d | OL | |
| GPU_RESET_L | Default | d | 0.708 | |
| GPU_RESET_L_R | Default | d | 0.684 | |
| GPU_RESET_R_L | Default | d | 0.708 | |
| GPU_ROM_CONFIG<1> | Default | d | 0.414 | |
| GPU_ROM_CONFIG<2> | Default | d | 0.408 | |
| GPU_ROM_CS_L | Default | d | OL | |
| GPU_ROM_CS_L_R | Default | d | 0.407 | |
| GPU_ROM_SCLK | Default | d | OL | |
| GPU_ROM_SCLK_R | Default | d | 0.413 | |
| GPU_ROM_SI | Default | d | OL | |
| GPU_ROM_SI_R | Default | d | 0.407 | |
| GPU_ROM_SO | Default | d | 0.430 | |
| GPU_ROM_SO_R | Default | d | OL | |
| GPU_ROM_WP_L | Default | d | OL | |
| GPU_SMBUS_ADDR<0> | Default | d | 0.512 | |
| GPU_SMBUS_ADDR<1> | Default | d | 0.460 | |
| GPU_SMB_CLK | Default | d | 0.493 | |
| GPU_SMB_DAT | Default | d | 0.491 | |
| GPU_TDIODE_N | Default | d | 0.657 | |
| GPU_TDIODE_P | Default | d | 0.843 | |
| GPU_TEST_EN | Default | d | 0.814 | |
| GPU_TEST_PG | Default | d | 0.797 | |
| GPU_TEST_PG_BACON | Default | d | 0.816 | |
| GPU_TX_HALF_SWING | Default | d | 0.409 | |
| GPU_VCORE_IOUT_REF | Default | d | OL | |
| GPU_VCORE_IOUT_REF_R | Default | d | OL | |
| GPU_VGA_DIS | Default | d | 0.411 | |
| GPU_VRAM_STRAP | Default | d | 0.414 | |
| GT_ISUMN_R | Default | d | 1.013 | |
| HRN_BT_DEV_WAKE | Default | d | 0.489 | |
| HS_3V3_X_IOUT | Default | d | 0.698 | |
| HS_MIC_N | Default | d | 0.628 | |
| HS_MIC_P | Default | d | 0.630 | |
| HS_OTHER5V_IOUT | Default | d | 0.695 | |
| HS_P3V3_G3W_SSD0_OUT | Default | d | 0.698 | |
| HS_P3V3_G3W_SSD1_OUT | Default | d | OL | |
| HS_PBUS_MAIN_SSD0_OUT | Default | d | 0.687 | |
| HS_PBUS_MAIN_SSD1_OUT | Default | d | OL | |
| I2C_ALS_SCL | Default | d | 0.470 | |
| I2C_ALS_SDA | Default | d | 0.470 | |
| I2C_BATT_SDA_R | Default | d | 0.492 | |
| I2C_BKLT_SCL | Default | d | 0.530 | |
| I2C_BKLT_SDA | Default | d | 0.530 | |
| I2C_CAM_ISOL_SCL | Default | d | 0.480 | |
| I2C_CAM_ISOL_SDA | Default | d | 0.480 | |
| I2C_CODEC_SCL | Default | d | 0.478 | |
| I2C_CODEC_SDA | Default | d | 0.479 | |
| I2C_DFR_SCL | Default | d | 0.479 | |
| I2C_DFR_SCL_R | Default | d | 0.47 | |
| I2C_DFR_SDA | Default | d | 0.478 | |
| I2C_DFR_SDA_R | Default | d | 0.47 | |
| I2C_DISP_SCL | Default | d | 0.489 | |
| I2C_DISP_SDA | Default | d | 0.488 | |
| I2C_FTCAM_SCL | Default | d | 0.455 | |
| I2C_FTCAM_SDA | Default | d | 0.455 | |
| I2C_KBD_SCL | Default | d | OL | |
| I2C_KBD_SDA | Default | d | OL | |
| I2C_PWR_SCL | Default | d | 0.45 | |
| I2C_PWR_SDA | Default | d | 0.45 | |
| I2C_SEP_SCL | Default | d | 0.483 | |
| I2C_SEP_SDA | Default | d | 0.480 | |
| I2C_SNS0_S0_5V_SCL | Default | d | OL | |
| I2C_SNS0_S0_5V_SDA | Default | d | OL | |
| I2C_SNS0_S0_SCL | Default | d | 0.489 | |
| I2C_SNS0_S0_SDA | Default | d | 0.489 | |
| I2C_SNS1_S0_SCL | Default | d | 0.484 | |
| I2C_SNS1_S0_SDA | Default | d | 0.484 | |
| I2C_SNS_G3S_SCL | Default | d | 0.484 | |
| I2C_SNS_G3S_SDA | Default | d | 0.488 | |
| I2C_SPKRAMP_L_SCL | Default | d | 0.386 | |
| I2C_SPKRAMP_L_SDA | Default | d | 0.386 | |
| I2C_SPKRAMP_R_SCL | Default | d | 0.388 | |
| I2C_SPKRAMP_R_SDA | Default | d | 0.388 | |
| I2C_SSD0_SCL | Default | d | 0.508 | |
| I2C_SSD0_SDA | Default | d | 0.509 | |
| I2C_SSD1_SCL | Default | d | OL | |
| I2C_SSD1_SDA | Default | d | OL | |
| I2C_SSD_SCL | Default | d | 0.484 | |
| I2C_SSD_SDA | Default | d | 0.485 | |
| I2C_TBT_TA_INT_L | Default | d | 0.70 | |
| I2C_TBT_TB_INT_L | Default | d | 0.69 | |
| I2C_TBT_T_SCL | Default | d | 0.59 | |
| I2C_TBT_T_SDA | Default | d | 0.59 | |
| I2C_TBT_XA_INT_L | Default | d | 0.69 | |
| I2C_TBT_XB_INT_L | Default | d | 0.70 | |
| I2C_TBT_X_SCL | Default | d | 0.60 | |
| I2C_TBT_X_SDA | Default | d | 0.60 | |
| I2C_TCON_SCL | Default | d | 0.500 | |
| I2C_TCON_SDA | Default | d | 0.500 | |
| I2C_TPAD3V3_SCL | Default | d | 0.89 | |
| I2C_TPAD3V3_SCL_R | Default | d | 0.87 | |
| I2C_TPAD3V3_SDA | Default | d | 0.933 | |
| I2C_TPAD3V3_SDA_R | Default | d | 0.87 | |
| I2C_TPAD_SDA_R | Default | d | 0.47 | |
| I2C_UPC_SCL | Default | d | 0.485 | |
| I2C_UPC_SDA | Default | d | 0.488 | |
| I2C_UPC_TA_DBG_CTL_SCL | Default | d | 0.777 | |
| I2C_UPC_TA_DBG_CTL_SDA | Default | d | 0.776 | |
| I2C_UPC_TB_DBG_CTL_SCL | Default | d | 0.776 | |
| I2C_UPC_TB_DBG_CTL_SDA | Default | d | 0.775 | |
| I2C_UPC_T_SCL2 | Default | d | 0.48 | |
| I2C_UPC_T_SDA2 | Default | d | 0.48 | |
| I2C_UPC_XA_DBG_CTL_SCL | Default | d | 0.53 | |
| I2C_UPC_XA_DBG_CTL_SDA | Default | d | 0.55 | |
| I2C_UPC_XB_DBG_CTL_SCL | Default | d | 0.76 | |
| I2C_UPC_XB_DBG_CTL_SDA | Default | d | 0.76 | |
| I2C_UPC_X_SCL2 | Default | d | 0.48 | |
| I2C_UPC_X_SDA2 | Default | d | 0.48 | |
| I2S_CODEC_BCLK | Default | d | 0.477 | |
| I2S_CODEC_D2R | Default | d | 0.473 | |
| I2S_CODEC_LRCLK_R | Default | d | 0.494 | |
| I2S_CODEC_R2D | Default | d | 0.465 | |
| I2S_SPKRAMP_L_BCLK | Default | d | 0.388 | |
| I2S_SPKRAMP_L_D2R | Default | d | 0.378 | |
| I2S_SPKRAMP_L_D2R_R1 | Default | d | 0.385 | |
| I2S_SPKRAMP_L_D2R_R2 | Default | d | 0.386 | |
| I2S_SPKRAMP_L_LRCLK_R | Default | d | 0.386 | |
| I2S_SPKRAMP_L_R2D | Default | d | 0.387 | |
| I2S_SPKRAMP_R_BCLK | Default | d | 0.387 | |
| I2S_SPKRAMP_R_D2R_R1 | Default | d | 0.388 | |
| I2S_SPKRAMP_R_D2R_R2 | Default | d | 0.387 | |
| I2S_SPKRAMP_R_LRCLK_R | Default | d | 0.386 | |
| I2S_SPKRAMP_R_R2D | Default | d | 0.387 | |
| IAPC_OPA_OUT | Default | d | OL | |
| IMON_A_CPUCORE | Default | d | 0.626 | |
| IMON_B_CPUGT | Default | d | 0.623 | |
| IMON_C_CPUSA | Default | d | 0.626 | |
| IPD_LID_OPEN | Default | d | 0.70 | |
| IPD_LID_OPEN_R | Default | d | OL | |
| ISNS_1V0_N | Default | d | OL | |
| ISNS_1V0_N | Default | v | - | |
| ISNS_1V0_P | Default | d | OL | |
| ISNS_1V0_P | Default | v | - | |
| ISNS_2V5_S3_N | Default | d | 0.360 | |
| ISNS_2V5_S3_P | Default | d | 0.360 | |
| ISNS_CALPE_IOUT | Default | d | 0.693 | |
| ISNS_CALPE_N | Default | d | 0.426 | |
| ISNS_CALPE_P | Default | d | 0.426 | |
| ISNS_CPUDDR_IOUT | Default | d | OL | |
| ISNS_CPUDDR_N | Default | d | 0.163 | |
| ISNS_CPUDDR_N | Default | v | 1,200 | |
| ISNS_CPUDDR_P | Default | d | 0.163 | |
| ISNS_CPUDDR_P | Default | v | 1,200 | |
| ISNS_CPUSA_IOUT | Default | d | OL | |
| ISNS_CPUVCCIO_NEG | Default | d | 0.085 | |
| ISNS_CPUVCCIO_NEG | Default | r | 83.500R | |
| ISNS_CPUVCCIO_POS | Default | d | 0.085 | |
| ISNS_CPUVCCIO_POS | Default | r | 83.700R | |
| ISNS_CPUVDDQ_N | Default | d | OL | |
| ISNS_CPUVDDQ_P | Default | d | OL | |
| ISNS_DDR_IOUT | Default | d | 0.718 | |
| ISNS_GPU1V8_IOUT | Default | d | OL | |
| ISNS_GPU1V8_N | Default | d | OL | |
| ISNS_GPU1V8_P | Default | d | OL | |
| ISNS_GPUFBIC_IOUT | Default | d | OL | |
| ISNS_GPUFBIC_N | Default | d | OL | |
| ISNS_GPUFBIC_P | Default | d | OL | |
| ISNS_GPUFB_IOUT | Default | d | OL | |
| ISNS_GPUVDDCI_IOUT | Default | d | OL | |
| ISNS_GPU_HS_N | Default | d | 0.400 | |
| ISNS_GPU_HS_N | Default | v | 12,600 | |
| ISNS_GPU_HS_P | Default | d | 0.431 | |
| ISNS_GPU_HS_P | Default | v | 12,600 | |
| ISNS_HS_3V3_T_N | Default | d | 0.434 | |
| ISNS_HS_3V3_T_N | Default | v | 12,600 | |
| ISNS_HS_3V3_T_OUT | Default | d | 0.717 | |
| ISNS_HS_3V3_T_P | Default | d | 0.434 | |
| ISNS_HS_3V3_T_P | Default | v | 12,600 | |
| ISNS_HS_3V3_X_N | Default | d | 0.434 | |
| ISNS_HS_3V3_X_P | Default | d | 0.436 | |
| ISNS_HS_COMPUTING_N | Default | d | 0.434 | |
| ISNS_HS_COMPUTING_N | Default | v | 12,600 | |
| ISNS_HS_COMPUTING_OUT | Default | d | 0.717 | |
| ISNS_HS_COMPUTING_P | Default | d | 0.434 | |
| ISNS_HS_COMPUTING_P | Default | v | 12,600 | |
| ISNS_HS_OTHER5V_N | Default | d | 0.434 | |
| ISNS_HS_OTHER5V_P | Default | d | 0.434 | |
| ISNS_LCDBKLT_IOUT | Default | d | OL | |
| ISNS_LCDBKLT_N | Default | d | 0.434 | |
| ISNS_LCDBKLT_N | Default | v | 12,600 | |
| ISNS_LCDBKLT_P | Default | d | 0.434 | |
| ISNS_LCDBKLT_P | Default | v | 12,600 | |
| ISNS_LCDPANEL_IOUT | Default | d | OL | |
| ISNS_LCDPANEL_N | Default | d | OL | |
| ISNS_LCDPANEL_P | Default | d | OL | |
| ISNS_P3V3S_WLAN_IOUT | Default | d | OL | |
| ISNS_P3V3_G3W_SSD0_N | Default | d | 0.428 | |
| ISNS_P3V3_G3W_SSD0_P | Default | d | 0.428 | |
| ISNS_P3V3_G3W_SSD1_N | Default | d | OL | |
| ISNS_P3V3_G3W_SSD1_P | Default | d | OL | |
| ISNS_PP3V3S0_IOUT | Default | d | OL | |
| ISNS_PPBUS_MAIN_SSD0_N | Default | d | 0.434 | |
| ISNS_PPBUS_MAIN_SSD0_N | Default | v | 12,600 | |
| ISNS_PPBUS_MAIN_SSD0_P | Default | d | 0.432 | |
| ISNS_PPBUS_MAIN_SSD0_P | Default | v | 12,600 | |
| ISNS_PPBUS_MAIN_SSD1_N | Default | d | OL | |
| ISNS_PPBUS_MAIN_SSD1_P | Default | d | OL | |
| ISNS_T139_N | Default | d | OL | |
| ISNS_T139_P | Default | d | OL | |
| ISNS_TBT_T_IOUT | Default | d | OL | |
| ISNS_TBT_T_N | Default | d | OL | |
| ISNS_TBT_T_P | Default | d | OL | |
| ISNS_TBT_X_IOUT | Default | d | OL | |
| ISNS_TBT_X_N | Default | d | OL | |
| ISNS_TBT_X_P | Default | d | OL | |
| ISNS_VCCIO_IOUT | Default | d | OL | |
| ISNS_WL1V8_IOUT | Default | d | OL | |
| ISNS_WL1V8_N | Default | d | OL | |
| ISNS_WL1V8_P | Default | d | OL | |
| ISNS_WLAN_N | Default | d | OL | |
| ISNS_WLAN_P | Default | d | OL | |
| ISNS_WLAN_R_N | Default | d | OL | |
| ISNS_WLAN_R_P | Default | d | OL | |
| JTAG_ISP_TCK | Default | d | 0.564 | |
| JTAG_ISP_TDI | Default | d | 0.563 | |
| JTAG_TBT_T_TMS | Default | d | 0.603 | |
| JTAG_TBT_X_TMS | Default | d | 0.600 | |
| KBD_BLC_GSLAT | Default | d | OL | |
| KBD_BLC_GSSCK | Default | d | OL | |
| KBD_BLC_GSSIN | Default | d | OL | |
| KBD_BLC_GSSOUT | Default | d | OL | |
| KBD_BLC_XBLANK | Default | d | OL | |
| KBD_INT_L | Default | d | OL | |
| L83_FILT | Default | d | 0.800 | |
| L83_FLYC | Default | d | 0.390 | |
| L83_FLYN | Default | d | 0.493 | |
| L83_FLYP | Default | d | 0.402 | |
| L83_HSBIAS_FILT | Default | d | 0.719 | |
| L83_HSBIAS_FILT_REF | Default | d | 0.640 | |
| L83_LDO_EN | Default | d | 0.783 | |
| L83_SDOUT | Default | d | 0.488 | |
| L83_VCP_FILTN | Default | d | 0.633 | |
| L83_VCP_FILTP | Default | d | 0.394 | |
| L83_VCP_FILT_GND | Default | d | 0.000 | |
| L83_VCP_FILT_GND | Default | r | 0.300R | |
| LCDBKLT_EN_L | Default | d | OL | |
| LCDBKLT_FB | Default | d | 0.732 | |
| LCDBKLT_FET_DRV | Default | d | 0.496 | |
| LCDBKLT_FET_DRV_R | Default | d | 0.509 | |
| LCDBKLT_SW | Default | d | 0.430 | |
| LCDBKLT_TB_XWR | Default | d | 1.228 | |
| LCD_FSS | Default | d | NA | |
| LCD_MUX_EN | Default | d | 0.800 | |
| LCD_PWR_SLEW | Default | d | 0.617 | |
| LCD_PWR_SLEW_3V3 | Default | d | 0.723 | |
| LDO_CORE | Default | d | 0.380 | |
| LDO_RTC | Default | d | 0.378 | |
| LID_CTRL_DMIC | Default | d | 0.706 | |
| LID_OPEN_LEFT | Default | d | 0.476 | |
| LID_OPEN_RIGHT | Default | d | 0.476 | |
| MEMVTT_EN | Default | d | 0.549 | |
| MEMVTT_EN_R | Default | d | 0.548 | |
| MEM_A_TEN_R | Default | d | 0.101 | |
| MEM_B_TEN_R | Default | d | 0.100 | |
| MEM_RESET_L | Default | d | 0.383 | |
| MESA_BOOST_EN | Default | d | 0.553 | |
| MESA_BOOST_EN_CONN | Default | d | 1.10 | |
| MESA_INT | Default | d | 0.480 | |
| MESA_INT_CONN | Default | d | 1.03 | |
| MESA_PWR_EN | Default | d | 0.474 | |
| MIPI_DFR_CLK_CONN_FILT_N | Default | d | 0.52 | |
| MIPI_DFR_CLK_CONN_FILT_P | Default | d | 0.52 | |
| MIPI_DFR_CLK_N | Default | d | 0.553 | |
| MIPI_DFR_CLK_P | Default | d | 0.557 | |
| MIPI_DFR_DATA_CONN_FILT_N | Default | d | 0.53 | |
| MIPI_DFR_DATA_CONN_FILT_P | Default | d | 0.53 | |
| MIPI_DFR_DATA_N | Default | d | 0.554 | |
| MIPI_DFR_DATA_P | Default | d | 0.550 | |
| MIPI_FTCAM_CLK_CONN_N | Default | d | 0.480 | |
| MIPI_FTCAM_CLK_CONN_P | Default | d | 0.480 | |
| MIPI_FTCAM_CLK_ISOL_N | Default | d | 0.522 | |
| MIPI_FTCAM_CLK_ISOL_P | Default | d | 0.522 | |
| MIPI_FTCAM_DATA_CONN_N<0> | Default | d | 0.490 | |
| MIPI_FTCAM_DATA_CONN_P<0> | Default | d | 0.490 | |
| MIPI_FTCAM_DATA_ISOL_N<0> | Default | d | 0.524 | |
| MIPI_FTCAM_DATA_ISOL_P<0> | Default | d | 0.521 | |
| MLBSNS_I2CLS_EN | Default | d | OL | |
| MLB_RAMCFG0 | Default | d | 0.766 | |
| MLB_RAMCFG1 | Default | d | 0.768 | |
| MLB_RAMCFG2 | Default | d | 0.617 | |
| MLB_RAMCFG3 | Default | d | 0.563 | |
| MLB_RAMCFG4 | Default | d | 0.545 | |
| NTC_A_CPUCORE | Default | d | 0.627 | |
| NTC_A_CPUCORE_R | Default | d | OL | |
| NTC_A_CPUCORE_XW | Default | d | 0.000 | |
| NTC_B_CPUCORE_XW | Default | d | OL | |
| NTC_B_CPUGT | Default | d | 0.626 | |
| NTC_B_CPUGT_R | Default | d | 2.835 | |
| NTC_B_CPUGT_R | Default | v | - | |
| P0V8SLPDDR_FB | Default | d | 0.064 | |
| P0V8SLPDDR_FB | Default | r | 62.400R | |
| P0V8SLPDDR_FB_R | Default | d | 0.064 | |
| P0V8SLPDDR_FB_R | Default | r | 63.000R | |
| P0V8SLPDDR_SW0 | Default | d | 0.043 | |
| P0V8SLPDDR_SW0 | Default | r | 62.000R | |
| P0V8SLPDDR_SW0 | Default | v | 0,800 | |
| P0V8SLPDDR_SW1 | Default | d | 0.045 | |
| P0V8SLPDDR_SW1 | Default | r | 62,000R | |
| P0V8SLPDDR_SW1 | Default | v | 0,800 | |
| P0V9SLPDDR_FB | Default | d | 0.074 | |
| P0V9SLPDDR_FB | Default | r | 72.800R | |
| P0V9SLPDDR_SW0 | Default | d | 0.076 | |
| P0V9SLPDDR_SW0 | Default | r | 76.500R | |
| P0V9SLPDDR_SW0 | Default | v | 0,900 | |
| P0V9SLPDDR_SW1 | Default | d | 0.076 | |
| P0V9SLPDDR_SW1 | Default | r | 74.300R | |
| P0V9SLPDDR_SW1 | Default | v | 0,900 | |
| P0V9_LX0_SSD0 | Default | d | 0.328 | |
| P0V9_LX0_SSD0 | Default | r | 398,000 | |
| P0V9_LX0_SSD0 | Default | v | 0,900 | |
| P0V9_LX0_SSD1 | Default | d | OL | |
| P0V9_LX0_SSD1 | Default | v | 0,900 | |
| P0V9_LX1_SSD0 | Default | d | 0.328 | |
| P0V9_LX1_SSD0 | Default | r | 398.000 | |
| P0V9_LX1_SSD0 | Default | v | 0,900 | |
| P0V9_LX1_SSD1 | Default | d | OL | |
| P0V9_LX1_SSD1 | Default | v | 0,900 | |
| P0V9_TBT_T_SVR_AGND | Default | d | 0.000 | |
| P0V9_TBT_T_SVR_AGND | Default | r | 0.300R | |
| P0V9_TBT_X_SVR_AGND | Default | d | 0.000 | |
| P1V1S0SW_FET_EN | Default | d | 0.557 | |
| P1V1S0SW_RAMP | Default | d | 0.695 | |
| P1V1SLPDDR_RAMP | Default | d | 0.715 | |
| P1V1SLPS2R_FB | Default | d | 0.365 | |
| P1V1SLPS2R_SW0 | Default | d | 0.366 | |
| P1V1SLPS2R_SW0 | Default | r | 0.001R | |
| P1V1SLPS2R_SW0 | Default | v | 1,100 | |
| P1V1SLPS2R_SW1 | Default | d | 0.366 | |
| P1V1SLPS2R_SW1 | Default | r | 0.001R | |
| P1V1SLPS2R_SW1 | Default | v | 1,100 | |
| P1V1_SLPDDR_SOCFET_EN | Default | d | 0.568 | |
| P1V1_SLPDDR_SOCFET_EN_R | Default | d | OL | |
| P1V2REG_AGND | Default | d | 0.000 | |
| P1V2REG_MODE | Default | d | 0.555 | |
| P1V2REG_TRIP | Default | d | 0.753 | |
| P1V2REG_VREF | Default | d | 0.658 | |
| P1V2REG_VREF_R | Default | d | OL | |
| P1V2_BOOT_RC | Default | d | 0.632 | |
| P1V2_DRVH | Default | d | 0.700 | |
| P1V2_DRVH_R | Default | d | 0.702 | |
| P1V2_DRVL | Default | d | 0.490 | |
| P1V2_DRVL_R | Default | d | 0.482 | |
| P1V2_LL_SNUB | Default | d | OL | |
| P1V2_PHASE | Default | d | 0.199 | |
| P1V2_PHASE | Default | r | 160.500 | |
| P1V2_PHASE | Default | v | 1,200 | |
| P1V2_SNS | Default | d | 0.173 | |
| P1V2_SNS_R | Default | d | 0.164 | |
| P1V2_SW | Default | d | 0.160 | |
| P1V2_VBST | Default | d | 0.630 | |
| P1V2_WLANBT_VLX | Default | d | 0.315 | |
| P1V35FB_EN | Default | d | 0.537 | |
| P1V5R1V35_GPU_FB_SNS_N | Default | d | 0.000 | |
| P1V5R1V35_GPU_FB_SNS_P | Default | d | 0.056 | |
| P1V5R1V35_GPU_FB_SNS_P | Default | r | 55.200R | |
| P1V5_WLANBT_VLX | Default | d | 0.340 | |
| P1V8G3S_EN | Default | d | 0.573 | |
| P1V8G3S_SS | Default | d | 0.723 | |
| P1V8GPU_EN | Default | d | 0.621 | |
| P1V8GPU_PGOOD | Default | d | 0.520 | |
| P1V8S5_VALID | Default | d | 0.718 | |
| P1V8SLPS2R_FB | Default | d | 0.409 | |
| P1V8SLPS2R_SW0 | Default | d | 0.411 | |
| P1V8SLPS2R_SW0 | Default | r | 172.000 | |
| P1V8SLPS2R_SW0 | Default | v | 1,800 | |
| P1V8_G3S_EN_R | Default | d | OL | |
| P1V8_LX0_SSD0 | Default | d | 0.371 | |
| P1V8_LX0_SSD0 | Default | r | 0.090R | |
| P1V8_LX0_SSD0 | Default | v | 1,800 | |
| P1V8_LX0_SSD1 | Default | d | OL | |
| P1V8_LX0_SSD1 | Default | v | 1,800 | |
| P2V5S3_FSW | Default | d | 0.360 | |
| P2V5S3_REG | Default | d | 0.360 | |
| P2V5S3_REG | Default | v | 2,500 | |
| P2V5_SSD0_AGND | Default | d | 0.000 | |
| P2V5_SSD1_AGND | Default | d | OL | |
| P2V5_SW1_TPS62180_SSD0 | Default | d | 0.376 | |
| P2V5_SW1_TPS62180_SSD0 | Default | r | 137,000 | |
| P2V5_SW1_TPS62180_SSD0 | Default | v | 2,500 | |
| P2V5_SW1_TPS62180_SSD1 | Default | d | OL | |
| P2V5_SW1_TPS62180_SSD1 | Default | v | 2.500 | |
| P2V5_SW2_TPS62180_SSD0 | Default | d | 0.376 | |
| P2V5_SW2_TPS62180_SSD0 | Default | r | 137,000 | |
| P2V5_SW2_TPS62180_SSD0 | Default | v | 2,500 | |
| P2V5_SW2_TPS62180_SSD1 | Default | d | OL | |
| P2V5_VPP_PGOOD | Default | d | 0.500 | |
| P3V3G3HRTC_FB | Default | d | 1.38 | |
| P3V3G3HRTC_FB_R | Default | d | 0.440 | |
| P3V3G3HRTC_PGOOD | Default | d | 0.68 | |
| P3V3G3HRTC_PHASE1 | Default | d | 0.429 | |
| P3V3G3HRTC_PHASE1 | Default | v | 3,300 | |
| P3V3G3HRTC_PHASE2 | Default | d | 0.429 | |
| P3V3G3HRTC_PHASE2 | Default | r | 0.010R | |
| P3V3G3HRTC_PHASE2 | Default | v | 3,300 | |
| P3V3G3HRTC_RA_R | Default | d | 0.440 | |
| P3V3G3HRTC_SS | Default | d | 0.53 | |
| P3V3G3H_COMP2 | Default | d | 0.745 | |
| P3V3G3H_CSN2 | Default | d | 0.420 | |
| P3V3G3H_CSP2 | Default | d | 1.288 | |
| P3V3G3H_CSP2_R | Default | d | 0.420 | |
| P3V3G3H_DRVH | Default | d | 0.996 | |
| P3V3G3H_DRVL | Default | d | 0.563 | |
| P3V3G3H_EN | Default | d | 0.583 | |
| P3V3G3H_RF | Default | d | 0.583 | |
| P3V3G3H_SNUBR | Default | d | OL | |
| P3V3G3H_SW | Default | d | 0.427 | |
| P3V3G3H_TG | Default | d | 0.997 | |
| P3V3G3H_VBST | Default | d | 0.636 | |
| P3V3G3H_VBST_R | Default | d | 0.637 | |
| P3V3G3H_VFB2 | Default | d | 0.585 | |
| P3V3G3H_VFB2_R | Default | d | 0.420 | |
| P3V3G3H_VFB2_RR | Default | d | 1.380 | |
| P3V3G3H_VSW | Default | d | 0.427 | |
| P3V3G3H_VSW | Default | r | 425.200 | |
| P3V3G3H_VSW | Default | v | 3,300 | |
| P3V3G3ST_SS | Default | d | 0.724 | |
| P3V3G3SX_SS | Default | d | 0.723 | |
| P3V3G3S_EN | Default | d | 0.541 | |
| P3V3GPU_EN | Default | d | 0.523 | |
| P3V3GPU_RAMP | Default | d | 0.718 | |
| P3V3MAIN_PGOOD | Default | d | 0.578 | |
| P3V3S5_COMP2_R | Default | d | OL | |
| P3V3TBTT_RAMP | Default | d | 0.624 | |
| P3V3TBTX_RAMP | Default | d | 0.723 | |
| P3V3_G3H_RTC_DEBUG_LED_R | Default | d | OL | |
| P3V3_S0GPU_PGOOD | Default | d | 0.718 | |
| P3V3_TBT_T_SX_R | Default | d | 0.574 | |
| P3V3_TBT_X_SX_R | Default | d | 0.572 | |
| P5GPU_RAMP | Default | d | 0.619 | |
| P5VG3S_COMP1 | Default | d | 0.751 | |
| P5VG3S_CSN1 | Default | d | 0.409 | |
| P5VG3S_CSN1 | Default | v | 5,000 | |
| P5VG3S_CSP1 | Default | d | 0.994 | |
| P5VG3S_CSP1_R | Default | d | 0.409 | |
| P5VG3S_CSP1_R | Default | v | 5,000 | |
| P5VG3S_DRVH | Default | d | 0.980 | |
| P5VG3S_DRVL | Default | d | 0.563 | |
| P5VG3S_EN | Default | d | 0.583 | |
| P5VG3S_EN_R | Default | d | 0.583 | |
| P5VG3S_PGOOD | Default | d | 0.578 | |
| P5VG3S_SNUBR | Default | d | OL | |
| P5VG3S_SW | Default | d | 0.409 | |
| P5VG3S_TG | Default | d | 0.977 | |
| P5VG3S_VBST | Default | d | 0.636 | |
| P5VG3S_VBST_R | Default | d | 0.637 | |
| P5VG3S_VFB1 | Default | d | 0.578 | |
| P5VG3S_VFB1_R | Default | d | 0.406 | |
| P5VG3S_VSW | Default | d | 0.408 | |
| P5VG3S_VSW | Default | v | 5,000 | |
| P5VP3V3_SKIPSEL | Default | d | 0.477 | |
| P5VP3V3_VREF2 | Default | d | 0.480 | |
| P5VP3V3_VREG3 | Default | d | 0.511 | |
| P5VS4_COMP1_R | Default | d | OL | |
| P5VUSBCT_AGND | Default | d | 0.000 | |
| P5VUSBCT_BOOT_RC | Default | d | 0.612 | |
| P5VUSBCT_DRVH | Default | d | 0.685 | |
| P5VUSBCT_DRVH_R | Default | d | 0.668 | |
| P5VUSBCT_FSEL | Default | d | 0.554 | |
| P5VUSBCT_LL | Default | d | 0.215 | |
| P5VUSBCT_LL | Default | r | 213.700R | |
| P5VUSBCT_LL | Default | v | 5,000 | |
| P5VUSBCT_N | Default | d | 0.215 | |
| P5VUSBCT_OCSET | Default | d | 0.548 | |
| P5VUSBCT_P | Default | d | 0.215 | |
| P5VUSBCT_R | Default | d | 0.215 | |
| P5VUSBCT_R | Default | r | 213.700R | |
| P5VUSBCT_R | Default | v | 5,000 | |
| P5VUSBCT_RTN_DIV | Default | d | 0.551 | |
| P5VUSBCT_RTN_DIV_R | Default | d | 0.000 | |
| P5VUSBCT_SENSE_DIV | Default | d | 0.547 | |
| P5VUSBCT_SENSE_DIV_R | Default | d | 0.216 | |
| P5VUSBCT_SET0 | Default | d | 0.550 | |
| P5VUSBCT_SET1 | Default | d | 0.552 | |
| P5VUSBCT_SET_R | Default | d | OL | |
| P5VUSBCT_SREF | Default | d | 0.551 | |
| P5VUSBCT_VBST | Default | d | 0.610 | |
| P5VUSBCT_VO | Default | d | 0.547 | |
| P5VUSBC_X_AGND | Default | d | 0.000 | |
| P5VUSBC_X_BOOT_RC | Default | d | 0.616 | |
| P5VUSBC_X_DRVH | Default | d | 0.716 | |
| P5VUSBC_X_DRVH_R | Default | d | 0.715 | |
| P5VUSBC_X_FSEL | Default | d | 0.558 | |
| P5VUSBC_X_LL | Default | d | 0.244 | |
| P5VUSBC_X_LL | Default | r | 500.000R | |
| P5VUSBC_X_LL | Default | v | 5,000 | |
| P5VUSBC_X_NEG | Default | d | 0.244 | |
| P5VUSBC_X_OCSET | Default | d | 0.551 | |
| P5VUSBC_X_PGOOD | Default | d | 0.553 | |
| P5VUSBC_X_POS | Default | d | 0.244 | |
| P5VUSBC_X_R | Default | d | 0.244 | |
| P5VUSBC_X_R | Default | r | 0.000R | |
| P5VUSBC_X_R | Default | v | 5,000 | |
| P5VUSBC_X_RTN_DIV | Default | d | 0.555 | |
| P5VUSBC_X_RTN_DIV_XW | Default | d | 0.000 | |
| P5VUSBC_X_SENSE_DIV | Default | d | 0.550 | |
| P5VUSBC_X_SENSE_DIV_XW | Default | d | 0.244 | |
| P5VUSBC_X_SET0 | Default | d | 0.558 | |
| P5VUSBC_X_SET1 | Default | d | 0.556 | |
| P5VUSBC_X_SET_R | Default | d | OL | |
| P5VUSBC_X_SREF | Default | d | 0.556 | |
| P5VUSBC_X_VBST | Default | d | 0.611 | |
| P5VUSBC_X_VO | Default | d | 0.552 | |
| P5V_3V3G3H_EN | Default | d | 0.585 | |
| P5_S0GPU_PGOOD | Default | d | 0.718 | |
| PANEL_P3V3_EN | Default | d | 0.572 | |
| PANEL_P3V3_EN_D | Default | d | 0.764 | |
| PANEL_P5V_EN | Default | d | 0.569 | |
| PANEL_P5V_EN_D | Default | d | 1.043 | |
| PBUSVSENS_EN_L | Default | d | 0.505 | |
| PBUSVSENS_EN_L_DIV | Default | d | OL | |
| PBUS_DIVIDER | Default | d | 0.708 | |
| PBUS_DIVIDER_REF | Default | d | 0.670 | |
| PBUS_S0_VSENSE | Default | d | OL | |
| PBUS_S0_VSENSE_IN | Default | d | 0.437 | |
| PCC_B | Default | d | OL | |
| PCC_CEXT | Default | d | OL | |
| PCC_CLR_L | Default | d | OL | |
| PCC_EVENT | Default | d | 0.493 | |
| PCC_EVENT_3V3 | Default | d | OL | |
| PCC_EVENT_R | Default | d | OL | |
| PCH_1V0_IOUT | Default | d | OL | |
| PCH_BATLOW_L | Default | d | 0.811 | |
| PCH_BT_DEV_WAKE | Default | d | 0.635 | |
| PCH_BT_ROM_BOOT_L | Default | d | 0.575 | |
| PCH_CLK24M_XTALIN | Default | d | 0.837 | |
| PCH_CLK24M_XTALOUT | Default | d | 0.833 | |
| PCH_CLK24M_XTALOUT_R | Default | d | 0.834 | |
| PCH_CLK32K_RTCX1 | Default | d | 0.862 | |
| PCH_CLKIN_XTAL | Default | d | 0.832 | |
| PCH_CPU_TRIGGER | Default | d | 0.433 | |
| PCH_CPU_TRIGGER_R | Default | d | 0.406 | |
| PCH_DISPA_SDI | Default | d | 0.336 | |
| PCH_DRAM_RESET_L | Default | d | 0.384 | |
| PCH_ESPI_ALERT0_L | Default | d | 0.820 | |
| PCH_GPPJ_RCOMP_1P8 | Default | d | 0.202 | |
| PCH_GPP_A0_PU | Default | d | 0.820 | |
| PCH_GPU_CLKREQ_L | Default | d | 0.813 | |
| PCH_INTRUDER_L | Default | d | 0.843 | |
| PCH_ITP_PMODE | Default | d | 0.405 | |
| PCH_PCIE_CLK100M_WLAN_N | Default | d | 0.351 | |
| PCH_PCIE_CLK100M_WLAN_P | Default | d | 0.350 | |
| PCH_PCIE_RCOMPN | Default | d | 0.325 | |
| PCH_PCIE_RCOMPP | Default | d | 0.326 | |
| PCH_PECI | Default | d | 0.397 | |
| PCH_PMTHRMTRIP_L | Default | d | 0.525 | |
| PCH_PMTHRMTRIP_L_R | Default | d | 0.539 | |
| PCH_PM_THRMTRIP_L_R | Default | d | 0.364 | |
| PCH_PROCPWRGD | Default | d | 0.361 | |
| PCH_RTC_RESET_L | Default | d | 0.771 | |
| PCH_SOC_SYNC | Default | d | 0.477 | |
| PCH_STRP_BSSB_SEL_GPIO | Default | d | 0.365 | |
| PCH_STRP_CNV_L | Default | d | 0.620 | |
| PCH_STRP_ESPI | Default | d | 0.811 | |
| PCH_STRP_GPD7 | Default | d | 0.817 | |
| PCH_STRP_NO_REBOOT | Default | d | 0.806 | |
| PCH_STRP_VCCPSPI_1V8 | Default | d | 0.550 | |
| PCH_STRP_XTAL_24MHZ | Default | d | 0.608 | |
| PCH_SWD_SOC_CLK | Default | d | 0.635 | |
| PCH_SWD_SOC_IO | Default | d | 0.635 | |
| PCH_UART_BT_CTS_L | Default | d | 0.710 | |
| PCH_UART_BT_D2R | Default | d | 0.711 | |
| PCH_UART_BT_R2D | Default | d | 0.715 | |
| PCH_UART_BT_RTS_L | Default | d | 0.714 | |
| PCH_UART_DEBUG_D2R | Default | d | 0.773 | |
| PCH_UART_DEBUG_R2D | Default | d | 0.773 | |
| PCH_WLAN_CLKREQ_L | Default | d | 0.812 | |
| PCH_WLAN_CLKREQ_R_L | Default | d | 0.535 | |
| PCH_WLAN_DEV_WAKE | Default | d | 0.747 | |
| PCH_WLAN_PERST_L | Default | d | 0.829 | |
| PCIE_CLK100M_DEBUG_N | Default | d | 0.348 | |
| PCIE_CLK100M_DEBUG_P | Default | d | 0.350 | |
| PCIE_CLK100M_LIFEBOAT_N | Default | d | 0.125 | |
| PCIE_CLK100M_LIFEBOAT_P | Default | d | 0.125 | |
| PCIE_CLK100M_SOC_N | Default | d | 0.325 | |
| PCIE_CLK100M_SOC_P | Default | d | 0.327 | |
| PCIE_LIFEBOAT_CLKREQ_L | Default | d | 0.482 | |
| PCIE_LIFEBOAT_D2R_N | Default | d | 0.407 | |
| PCIE_LIFEBOAT_D2R_P | Default | d | 0.406 | |
| PCIE_LIFEBOAT_R2D_C_N | Default | d | 0.338 | |
| PCIE_LIFEBOAT_R2D_C_P | Default | d | 0.339 | |
| PCIE_LIFEBOAT_RESET_L | Default | d | 0.482 | |
| PCIE_WAKE_L | Default | d | 0.814 | |
| PDM_DMIC_CLK0 | Default | d | 0.518 | |
| PDM_DMIC_CLK1 | Default | d | 0.514 | |
| PDM_DMIC_DATA0 | Default | d | 0.491 | |
| PDM_DMIC_DATA0_RR | Default | d | 0.525 | |
| PDM_DMIC_DATA0_UNSEC | Default | d | 0.718 | |
| PDM_DMIC_DATA1_RR | Default | d | 0.525 | |
| PDM_DMIC_DATA1_UNSEC | Default | d | 0.717 | |
| PEG_GPU_D2R_C_N<0> | Default | d | 0.314 | |
| PEG_GPU_D2R_C_N<1> | Default | d | 0.313 | |
| PEG_GPU_D2R_C_N<2> | Default | d | 0.313 | |
| PEG_GPU_D2R_C_N<3> | Default | d | 0.315 | |
| PEG_GPU_D2R_C_N<4> | Default | d | 0.314 | |
| PEG_GPU_D2R_C_N<5> | Default | d | 0.314 | |
| PEG_GPU_D2R_C_N<6> | Default | d | 0.314 | |
| PEG_GPU_D2R_C_N<7> | Default | d | 0.315 | |
| PEG_GPU_D2R_C_P<0> | Default | d | 0.314 | |
| PEG_GPU_D2R_C_P<1> | Default | d | 0.312 | |
| PEG_GPU_D2R_C_P<2> | Default | d | 0.312 | |
| PEG_GPU_D2R_C_P<3> | Default | d | 0.315 | |
| PEG_GPU_D2R_C_P<4> | Default | d | 0.312 | |
| PEG_GPU_D2R_C_P<5> | Default | d | 0.313 | |
| PEG_GPU_D2R_C_P<6> | Default | d | 0.314 | |
| PEG_GPU_D2R_C_P<7> | Default | d | 0.314 | |
| PEG_GPU_D2R_N<0> | Default | d | 0.292 | |
| PEG_GPU_D2R_N<1> | Default | d | 0.292 | |
| PEG_GPU_D2R_N<2> | Default | d | 0.292 | |
| PEG_GPU_D2R_N<3> | Default | d | 0.292 | |
| PEG_GPU_D2R_N<4> | Default | d | 0.292 | |
| PEG_GPU_D2R_N<5> | Default | d | 0.292 | |
| PEG_GPU_D2R_N<6> | Default | d | 0.292 | |
| PEG_GPU_D2R_N<7> | Default | d | 0.293 | |
| PEG_GPU_D2R_P<0> | Default | d | 0.295 | |
| PEG_GPU_D2R_P<1> | Default | d | 0.294 | |
| PEG_GPU_D2R_P<2> | Default | d | 0.294 | |
| PEG_GPU_D2R_P<3> | Default | d | 0.295 | |
| PEG_GPU_D2R_P<4> | Default | d | 0.292 | |
| PEG_GPU_D2R_P<5> | Default | d | 0.295 | |
| PEG_GPU_D2R_P<6> | Default | d | 0.296 | |
| PEG_GPU_D2R_P<7> | Default | d | 0.295 | |
| PEG_GPU_R2D_C_N<0> | Default | d | 0.239 | |
| PEG_GPU_R2D_C_N<1> | Default | d | 0.237 | |
| PEG_GPU_R2D_C_N<2> | Default | d | 0.239 | |
| PEG_GPU_R2D_C_N<3> | Default | d | 0.238 | |
| PEG_GPU_R2D_C_N<4> | Default | d | 0.239 | |
| PEG_GPU_R2D_C_N<5> | Default | d | 0.240 | |
| PEG_GPU_R2D_C_N<6> | Default | d | 0.240 | |
| PEG_GPU_R2D_C_N<7> | Default | d | 0.239 | |
| PEG_GPU_R2D_C_P<0> | Default | d | 0.238 | |
| PEG_GPU_R2D_C_P<1> | Default | d | 0.236 | |
| PEG_GPU_R2D_C_P<2> | Default | d | 0.238 | |
| PEG_GPU_R2D_C_P<3> | Default | d | 0.238 | |
| PEG_GPU_R2D_C_P<4> | Default | d | 0.239 | |
| PEG_GPU_R2D_C_P<5> | Default | d | 0.239 | |
| PEG_GPU_R2D_C_P<6> | Default | d | 0.240 | |
| PEG_GPU_R2D_C_P<7> | Default | d | 0.240 | |
| PEG_GPU_R2D_N<0> | Default | d | 0.393 | |
| PEG_GPU_R2D_N<1> | Default | d | 0.393 | |
| PEG_GPU_R2D_N<2> | Default | d | 0.392 | |
| PEG_GPU_R2D_N<3> | Default | d | 0.393 | |
| PEG_GPU_R2D_N<4> | Default | d | 0.393 | |
| PEG_GPU_R2D_N<5> | Default | d | 0.392 | |
| PEG_GPU_R2D_N<6> | Default | d | 0.392 | |
| PEG_GPU_R2D_N<7> | Default | d | 0.393 | |
| PEG_GPU_R2D_P<0> | Default | d | 0.393 | |
| PEG_GPU_R2D_P<1> | Default | d | 0.393 | |
| PEG_GPU_R2D_P<2> | Default | d | 0.391 | |
| PEG_GPU_R2D_P<3> | Default | d | 0.392 | |
| PEG_GPU_R2D_P<4> | Default | d | 0.393 | |
| PEG_GPU_R2D_P<5> | Default | d | 0.392 | |
| PEG_GPU_R2D_P<6> | Default | d | 0.392 | |
| PEG_GPU_R2D_P<7> | Default | d | 0.393 | |
| PHV_INT_TA_G3H | Default | d | 0.645 | |
| PHV_INT_TB_G3H | Default | d | 0.644 | |
| PHV_INT_XA_G3H | Default | d | 0.643 | |
| PHV_INT_XB_G3H | Default | d | 0.62 | |
| PLT3V3_RST_L | Default | d | 0.514 | |
| PLT_RST_L | Default | d | 0.625 | |
| PMU_3V3_T_HI_ISENSE | Default | d | 0.582 | |
| PMU_3V3_X_HI_ISENSE | Default | d | 0.582 | |
| PMU_ACTIVE_READY | Default | d | 0.479 | |
| PMU_ACTIVE_READY_R | Default | d | OL | |
| PMU_CLK32K_PCH | Default | d | 0.809 | |
| PMU_CLK32K_PCH_R | Default | d | 0.776 | |
| PMU_CLK32K_SOC | Default | d | 0.495 | |
| PMU_CLK32K_SOC_R | Default | d | 0.529 | |
| PMU_CLK32K_WLANBT | Default | d | 0.490 | |
| PMU_COLD_RESET_L | Default | d | 0.490 | |
| PMU_CPUDDR_ISENSE | Default | d | 0.586 | |
| PMU_CPU_ISENSE | Default | d | 0.587 | |
| PMU_CPU_VSENSE | Default | d | 0.581 | |
| PMU_DDR1V2_ISENSE | Default | d | 0.581 | |
| PMU_DROOP_L | Default | d | 0.485 | |
| PMU_FORCE_DFU | Default | d | 0.771 | |
| PMU_GPU_CORE_ISENSE | Default | d | 0.584 | |
| PMU_GPU_CORE_VSENSE | Default | d | 0.580 | |
| PMU_GPU_FB_ISENSE | Default | d | 0.585 | |
| PMU_IREF | Default | d | 0.758 | |
| PMU_LDO3_OUT | Default | d | 0.596 | |
| PMU_ONOFF_L | Default | d | 0.699 | |
| PMU_ONOFF_R_L | Default | d | 0.69 | |
| PMU_OTHER5V_HI_ISENSE | Default | d | 0.584 | |
| PMU_P1V8_WLAN_ISENSE | Default | d | 0.586 | |
| PMU_P3V3_G3W_SSD0_ISENSE | Default | d | 0.582 | |
| PMU_P3V3_G3W_SSD1_ISENSE | Default | d | 0.584 | |
| PMU_PBUS_BMON_DIS_ISENSE | Default | d | 0.585 | |
| PMU_PBUS_MAIN_SSD0_ISENSE | Default | d | 0.584 | |
| PMU_PBUS_MAIN_SSD1_ISENSE | Default | d | 0.583 | |
| PMU_PVDDMAIN_EN | Default | d | 0.773 | |
| PMU_RSLOC_RST_L | Default | d | 0.70 | |
| PMU_RSLOC_RST_R_L | Default | d | 0.70 | |
| PMU_SYS_ALIVE | Default | d | 0.436 | |
| PMU_VDD_HI | Default | d | 0.662 | |
| PMU_VDD_MAX | Default | d | 0.553 | |
| PMU_VPUMP | Default | d | 0.583 | |
| PMU_VREF | Default | d | 0.642 | |
| PMU_XTAL1_R | Default | d | 0.800 | |
| PMU_XTAL2 | Default | d | 0.800 | |
| PM_ALL_GPU_PGOOD | Default | d | 0.480 | |
| PM_MEMVTT_EN | Default | d | 0.376 | |
| PM_PCH_PWROK | Default | d | 0.491 | |
| PM_PCH_SYS_PWROK | Default | d | 0.538 | |
| PM_PWRBTN_L | Default | d | 0.765 | |
| PM_RSMRST_L | Default | d | 0.514 | |
| PM_SLP_S0_L | Default | d | OL | |
| PM_SLP_S0_R_L | Default | d | OL | |
| PM_SLP_S3_L | Default | d | 0.560 | |
| PM_SLP_S4_L | Default | d | 0.815 | |
| PM_SLP_S5_L | Default | d | 0.815 | |
| PM_SLP_TIEOFF | Default | d | 0.717 | |
| PM_SYNC | Default | d | 0.434 | |
| PM_SYSRST_L | Default | d | 0.813 | |
| PM_SYSRST_R_L | Default | d | 0.538 | |
| PM_THRMTRIP_L | Default | d | 0.251 | |
| PP0V6_S0_DDRVTT | Default | d | 0.126 | |
| PP0V82_SLPDDR | Default | d | 0.045 | |
| PP0V82_SLPDDR | Default | r | 62.000R | |
| PP0V82_SLPDDR | Default | v | 0,800 | |
| PP0V8_SLPS2R | Default | d | 0.229 | |
| PP0V95_S0_CPUVCCIO_REG_R | Default | d | 0.076 | |
| PP0V95_S0_CPUVCCIO_REG_R | Default | r | 75.600R | |
| PP0V9_SE_VMID | Default | d | 0.596 | |
| PP0V9_SLPDDR | Default | d | 0.076 | |
| PP0V9_SLPDDR | Default | r | 74.300R | |
| PP0V9_SLPDDR | Default | v | 0,900 | |
| PP0V9_SLPDDR_SOC_PCIEREFBUF | Default | d | 0.084 | |
| PP0V9_SLPDDR_SOC_PCIEREFBUF | Default | r | 82.600R | |
| PP0V9_SSD0 | Default | d | 0.328 | |
| PP0V9_SSD0 | Default | r | 398,000 | |
| PP0V9_SSD0 | Default | v | 0,900 | |
| PP0V9_SSD0_FB_DIS | Default | d | 0.405 | |
| PP0V9_SSD1 | Default | d | OL | |
| PP0V9_SSD1 | Default | v | 0,900 | |
| PP0V9_SSD1_FB_DIS | Default | d | OL | |
| PP0V9_TBT_T_LC | Default | d | 0.353 | |
| PP0V9_TBT_T_LVR | Default | d | 0.485 | |
| PP0V9_TBT_T_PCIE | Default | d | 0.316 | |
| PP0V9_TBT_T_SVR | Default | d | 0.314 | |
| PP0V9_TBT_T_SVR | Default | v | 0,900 | |
| PP0V9_TBT_X_LVR | Default | d | 0.486 | |
| PP0V9_TBT_X_PCIE | Default | d | 0.315 | |
| PP0V9_TBT_X_SVR | Default | d | 0.314 | |
| PP0V9_TBT_X_SVR | Default | r | 300.000R | |
| PP0V9_TBT_X_SVR | Default | v | 0,900 | |
| PP16V0_MESA | Default | d | 0.655 | |
| PP16V0_MESA_CONN | Default | d | 0.64 | |
| PP17V0_MOJAVE_LDOIN | Default | d | 0.596 | |
| PP1V05_PRIM | Default | d | 0.148 | |
| PP1V05_PRIM | Default | v | 1,050 | |
| PP1V05_PRIM_PCH_VCCAPLL_F | Default | d | 0.148 | |
| PP1V05_PRIM_PCH_VCCAXTAL_F | Default | d | 0.148 | |
| PP1V05_S0SW | Default | d | 0.216 | |
| PP1V05_S3 | Default | d | 0.214 | |
| PP1V1_SLPDDR | Default | d | 0.355 | |
| PP1V1_SLPDDR_SOC_VDDIOPLLDDR_F | Default | d | 0.385 | |
| PP1V1_SLPDDR_SOC_XTAL_F | Default | d | 0.385 | |
| PP1V1_SLPS2R | Default | d | 0.380 | |
| PP1V1_SLPS2R | Default | r | 0.001R | |
| PP1V1_SLPS2R | Default | v | 1,100 | |
| PP1V1_UPC_TA_LDO_BMC | Default | d | 0.521 | |
| PP1V1_UPC_TB_LDO_BMC | Default | d | 0.521 | |
| PP1V1_UPC_XA_LDO_BMC | Default | d | 0.521 | |
| PP1V1_UPC_XB_LDO_BMC | Default | d | 0.51 | |
| PP1V2_AWAKE | Default | d | 0.530 | |
| PP1V2_AWAKE_SOC_PCIEPLL_F | Default | d | 0.535 | |
| PP1V2_AWAKE_SOC_PCIEREFBUF_F | Default | d | 0.533 | |
| PP1V2_AWAKE_SOC_PLLCPU_F | Default | d | 0.533 | |
| PP1V2_AWAKE_SOC_PLLSOC_F | Default | d | 0.533 | |
| PP1V2_S0SW | Default | d | 0.324 | |
| PP1V2_S3 | Default | d | 0.163 | |
| PP1V2_S3 | Default | v | 1,200 | |
| PP1V2_S3_CPUDDR | Default | d | 0.161 | |
| PP1V2_S3_REG_R | Default | d | 0,163 | |
| PP1V2_S3_REG_R | Default | r | 160.500 | |
| PP1V2_S3_REG_R | Default | v | 1,200 | |
| PP1V2_WLANBT | Default | d | 0.316 | |
| PP1V2_WLANBT_C | Default | d | 0.315 | |
| PP1V5R1V35_GPU_REG_R | Default | d | - | |
| PP1V5R1V35_GPU_REG_R | Default | r | 54.400R | |
| PP1V5R1V35_GPU_REG_R | Default | v | 1,350 | |
| PP1V5R1V35_S0_GPU_IC | Default | d | 0.053 | |
| PP1V5R1V35_S0_GPU_IC | Default | r | 52.600R | |
| PP1V5R1V35_S0_GPU_IC | Default | v | 1,350 | |
| PP1V5R1V35_S0_GPU_MEM | Default | d | 0.053 | |
| PP1V5R1V35_S0_GPU_MEM | Default | r | 52.800R | |
| PP1V5R1V35_S0_GPU_MEM | Default | v | 1,350 | |
| PP1V5_WLANBT | Default | d | 0.339 | |
| PP1V5_WLANBT_C | Default | d | 0.340 | |
| PP1V8_ACCEL_FILT | Default | d | OL | |
| PP1V8_AUDIO | Default | d | 0.328 | |
| PP1V8_AWAKE | Default | d | -0.362 | |
| PP1V8_AWAKE_SOC_FMON_RC | Default | d | 0.415 | |
| PP1V8_AWAKE_SOC_TSADC_RC | Default | d | 0.365 | |
| PP1V8_DMIC | Default | d | 0.32 | |
| PP1V8_G3S | Default | d | 0.330 | |
| PP1V8_G3S | Default | v | 1.800 | |
| PP1V8_G3S_WLANBT_VDDIO | Default | d | 0.331 | |
| PP1V8_GPU | Default | d | 0.277 | |
| PP1V8_GPU_TSVDD | Default | d | 0.277 | |
| PP1V8_L83_VCP | Default | d | 0.329 | |
| PP1V8_L83_VCP_R | Default | d | 0.328 | |
| PP1V8_L83_VL | Default | d | 0.331 | |
| PP1V8_L83_VL_R | Default | d | 0.328 | |
| PP1V8_MESA | Default | d | 0.523 | |
| PP1V8_MESA_CONN | Default | d | 0.52 | |
| PP1V8_S0_GPU | Default | d | 0.277 | |
| PP1V8_S0_GPU | Default | r | 280.000R | |
| PP1V8_S0_GPU_LC_IC | Default | d | 0.277 | |
| PP1V8_S0_PCH_VCCHDA_F | Default | d | 0.350 | |
| PP1V8_S5 | Default | d | 0.35 | |
| PP1V8_S5_CPUTHMSNS_R | Default | d | 0.377 | |
| PP1V8_S5_GPIOX_R | Default | d | 0.367 | |
| PP1V8_S5_GPUTHMSNS_R | Default | d | OL | |
| PP1V8_S5_TBTTHMSNS_T_R | Default | d | 0.414 | |
| PP1V8_S5_TBTTHMSNS_X_R | Default | d | 0.416 | |
| PP1V8_SE_AVDD | Default | d | 0.317 | |
| PP1V8_SE_ESE | Default | d | 0.360 | |
| PP1V8_SLPS2R | Default | d | 0.411 | |
| PP1V8_SLPS2R | Default | r | 172.000 | |
| PP1V8_SLPS2R | Default | v | 1,800 | |
| PP1V8_SLPS2RSW_DFR | Default | d | 0.53 | |
| PP1V8_SLPS2RSW_DFR | Default | v | 1,800 | |
| PP1V8_SLPS2R_PMUVDDGPIO | Default | d | 0.744 | |
| PP1V8_SLPS2R_SOC_LPADC_RC | Default | d | 0.447 | |
| PP1V8_SLPS2R_SOC_LPOSC_RC | Default | d | 0.462 | |
| PP1V8_SSD0 | Default | d | 0.371 | |
| PP1V8_SSD0 | Default | r | 0.090R | |
| PP1V8_SSD0 | Default | v | 1,800 | |
| PP1V8_SSD0_FB_DIS | Default | d | 0.378 | |
| PP1V8_SSD1 | Default | d | OL | |
| PP1V8_SSD1 | Default | v | 1,800 | |
| PP1V8_SSD1_FB_DIS | Default | d | OL | |
| PP1V8_SSD1_S4E2_AVDD18_PLL | Default | d | OL | |
| PP1V8_UPC_TA_LDOA | Default | d | 0.528 | |
| PP1V8_UPC_TA_LDOD | Default | d | 0.491 | |
| PP1V8_UPC_TB_LDOA | Default | d | 0.527 | |
| PP1V8_UPC_TB_LDOD | Default | d | 0.492 | |
| PP1V8_UPC_XA_LDOA | Default | d | 0.529 | |
| PP1V8_UPC_XA_LDOD | Default | d | 0.491 | |
| PP1V8_UPC_XB_LDOA | Default | d | 0.52 | |
| PP1V8_UPC_XB_LDOD | Default | d | 0.48 | |
| PP1V8_VDD_XTAL | Default | d | 0.279 | |
| PP1V_PRIM_PCH_VCCAMPHYPLL_F | Default | d | 0.148 | |
| PP20V_USBC_TA_VBUS | Default | d | 0.188 | |
| PP20V_USBC_TA_VBUS | Default | t | Won't Boot without Battery, thereabout 20V 0.03A | |
| PP20V_USBC_TA_VBUS | Default | v | 20,000 | |
| PP20V_USBC_TA_VBUS_F | Default | d | 0.188 | |
| PP20V_USBC_TA_VBUS_F | Default | v | 20,000 | |
| PP20V_USBC_TB_VBUS | Default | d | 0.187 | |
| PP20V_USBC_TB_VBUS | Default | t | Won't Boot without Battery, thereabout 20V 0.03A | |
| PP20V_USBC_TB_VBUS | Default | v | 20,000 | |
| PP20V_USBC_TB_VBUS_F | Default | d | 0.185 | |
| PP20V_USBC_TB_VBUS_F | Default | v | 20,000 | |
| PP20V_USBC_XA_VBUS | Default | d | 0.187 | |
| PP20V_USBC_XA_VBUS | Default | t | Won't Boot without Battery, thereabout 20V 0.03A | |
| PP20V_USBC_XA_VBUS | Default | v | 20,000 | |
| PP20V_USBC_XA_VBUS_F | Default | d | 0.188 | |
| PP20V_USBC_XA_VBUS_F | Default | v | 20,000 | |
| PP20V_USBC_XB_VBUS | Default | d | 0.190 | |
| PP20V_USBC_XB_VBUS | Default | t | Won't Boot without Battery, thereabout 20V 0.03A | |
| PP20V_USBC_XB_VBUS | Default | v | 20,000 | |
| PP20V_USBC_XB_VBUS_F | Default | d | 0.190 | |
| PP20V_USBC_XB_VBUS_F | Default | v | 20,000 | |
| PP2V5_ADC1_VREF | Default | d | OL | |
| PP2V5_ADC2_VREF | Default | d | OL | |
| PP2V5_NAND_SSD0 | Default | d | 0.376 | |
| PP2V5_NAND_SSD0 | Default | r | 137,000 | |
| PP2V5_NAND_SSD0 | Default | v | 2,500 | |
| PP2V5_NAND_SSD1 | Default | d | OL | |
| PP2V5_NAND_SSD1 | Default | v | 2,500 | |
| PP2V5_S3 | Default | d | 0.360 | |
| PP2V5_S3 | Default | v | 2,500 | |
| PP3V0_G3H_RTC | Default | d | 0.517 | |
| PP3V0_MESA | Default | d | 0.561 | |
| PP3V0_MESA_CONN | Default | d | 0.559 | |
| PP3V3_G3HSW_DFR | Default | d | 0.56 | |
| PP3V3_G3H_DFR | Default | d | 0.432 | |
| PP3V3_G3H_DFR | Default | v | 3,300 | |
| PP3V3_G3H_MESA_SW | Default | d | 0.423 | |
| PP3V3_G3H_PMU_VINRTC_R | Default | d | 0.429 | |
| PP3V3_G3H_RTC_REG_R | Default | d | 0.429 | |
| PP3V3_G3H_RTC_REG_R | Default | r | 0.010R | |
| PP3V3_G3H_RTC_REG_R | Default | v | 3,300 | |
| PP3V3_G3H_RTC_X | Default | d | 0.41 | |
| PP3V3_G3H_SOCPMU | Default | d | 0.427 | |
| PP3V3_G3H_SSD0_SNS | Default | d | 0.425 | |
| PP3V3_G3H_SSD0_SNS | Default | v | 3,300 | |
| PP3V3_G3H_SSD1_SNS | Default | d | OL | |
| PP3V3_G3H_T | Default | d | 0.427 | |
| PP3V3_G3H_T | Default | r | 425.200 | |
| PP3V3_G3H_T | Default | v | 3,300 | |
| PP3V3_G3SSW_SNS | Default | d | 0.517 | |
| PP3V3_G3S_AUD_F | Default | d | 0.337 | |
| PP3V3_G3S_T | Default | d | 0.339 | |
| PP3V3_G3S_WLAN | Default | d | 0.353 | |
| PP3V3_G3S_X | Default | d | 0.352 | |
| PP3V3_L83_VP | Default | d | 0.339 | |
| PP3V3_S0SW_LCD | Default | d | 0.490 | |
| PP3V3_S0SW_LCD_R | Default | d | 0.553 | |
| PP3V3_S0SW_TBT_T | Default | d | 0.535 | |
| PP3V3_S0SW_TBT_T_SNS | Default | d | 0.535 | |
| PP3V3_S0SW_TBT_T_SNS | Default | v | 3,300 | |
| PP3V3_S0SW_TBT_X | Default | d | 0.535 | |
| PP3V3_S0SW_TBT_X_SNS | Default | d | 0.537 | |
| PP3V3_S0SW_TBT_X_SNS | Default | v | 3,300 | |
| PP3V3_S0_GPU | Default | d | 0.453 | |
| PP3V3_S5 | Default | d | 0.327 | |
| PP3V3_S5_GPIOX_R | Default | d | 0.328 | |
| PP3V3_TBT_T_ANA_PCIE | Default | d | 0.520 | |
| PP3V3_TBT_T_ANA_USB2 | Default | d | 0.496 | |
| PP3V3_TBT_T_F | Default | d | 0.535 | |
| PP3V3_TBT_T_F | Default | v | 3,300 | |
| PP3V3_TBT_T_LC | Default | d | 0.577 | |
| PP3V3_TBT_T_SX | Default | d | 0.538 | |
| PP3V3_TBT_X_ANA | Default | d | 0.537 | |
| PP3V3_TBT_X_ANA_PCIE | Default | d | 0.51 | |
| PP3V3_TBT_X_F | Default | d | 0.537 | |
| PP3V3_TBT_X_F | Default | v | 3,300 | |
| PP3V3_TBT_X_LC | Default | d | 0.56 | |
| PP3V3_TBT_X_SX | Default | d | 0.538 | |
| PP3V3_UPC_TA_LDO | Default | d | 0.514 | |
| PP3V3_UPC_TB_LDO | Default | d | 0.514 | |
| PP3V3_UPC_XA_LDO | Default | d | 0.517 | |
| PP3V3_UPC_XB_LDO | Default | d | 0.50 | |
| PP3V3_VREF_PCC | Default | d | OL | |
| PP4V7_SE_TVDD | Default | d | 0.352 | |
| PP5V_COREVR_VCC | Default | d | 0.401 | |
| PP5V_EADC1_AVDD | Default | d | OL | |
| PP5V_EADC2_AVDD | Default | d | OL | |
| PP5V_EDRAM_V5IN | Default | d | 0.410 | |
| PP5V_G3S | Default | d | 0.408 | |
| PP5V_G3S | Default | v | 5,000 | |
| PP5V_G3S_BKLT_A | Default | d | 0.409 | |
| PP5V_G3S_BKLT_D | Default | d | 0.410 | |
| PP5V_G3S_DFR_FILT | Default | d | 0.39 | |
| PP5V_G3S_FAN_CONN | Default | d | 0.39 | |
| PP5V_G3S_GFXIMVP_VDD | Default | d | 0.409 | |
| PP5V_G3S_GFXIMVP_VDDP | Default | d | 0.408 | |
| PP5V_G3S_ISNS_D | Default | d | OL | |
| PP5V_G3S_TPAD_CONN | Default | d | 0.39 | |
| PP5V_G3S_VCCIOVCC | Default | d | 0.411 | |
| PP5V_S0GPU_P1V35_GPU | Default | d | 0.408 | |
| PP5V_S0SW_LCD | Default | d | 0.566 | |
| PP5V_S0_ALSCAM_F | Default | d | 0.386 | |
| PP5V_S0_GPUFET | Default | d | 0.567 | |
| PP5V_S0_PCCAMP | Default | d | OL | |
| PP5V_S4_T_USBC | Default | d | 0.215 | |
| PP5V_S4_T_USBC | Default | v | 5,000 | |
| PP5V_S4_X_USBC | Default | d | 0.244 | |
| PP5V_S4_X_USBC | Default | r | 0.000R | |
| PP5V_S4_X_USBC | Default | v | 5,000 | |
| PP5V_S5_LDO | Default | d | 0.481 | |
| PP5V_USBCT_VCC | Default | d | 0.412 | |
| PP5V_USBC_X_VCC | Default | d | 0.412 | |
| PP5V_VREF_PCC | Default | d | OL | |
| PPBUS_G3H | Default | d | 0.434 | |
| PPBUS_G3H | Default | v | 12,600 | |
| PPBUS_G3H_R_IP0R | Default | d | OL | |
| PPBUS_G3H_SSD0_SNS | Default | d | 0.433 | |
| PPBUS_G3H_SSD0_SNS | Default | v | 12,600 | |
| PPBUS_G3H_SSD1_SNS | Default | d | OL | |
| PPBUS_G3H_SSD1_SNS | Default | v | 12,600 | |
| PPBUS_HS_3V3G3HRTC_X | Default | d | 0.436 | |
| PPBUS_HS_3V3G3H_T | Default | d | 0.434 | |
| PPBUS_HS_3V3G3H_T | Default | v | 12,600 | |
| PPBUS_HS_CPU | Default | d | 0.434 | |
| PPBUS_HS_CPU | Default | v | 12,600 | |
| PPBUS_HS_GPU | Default | d | 0.429 | |
| PPBUS_HS_GPU | Default | v | 12,600 | |
| PPBUS_HS_OTH5V | Default | d | 0.434 | |
| PPDCIN_G3H | Default | d | 0.540 | |
| PPDCIN_G3H | Default | v | 20,000 | |
| PPDCIN_G3H_CHGR | Default | d | 0.54 | |
| PPDCIN_G3H_CHGR | Default | v | 20,000 | |
| PPVBAT_G3H_CHGR_R | Default | d | 0.434 | |
| PPVBAT_G3H_CHGR_R | Default | v | 12,600 | |
| PPVBAT_G3H_CHGR_REG | Default | d | 0.434 | |
| PPVBAT_G3H_CHGR_REG | Default | v | 12,600 | |
| PPVBAT_G3H_CONN | Default | d | 1.40 | |
| PPVBAT_G3H_CONN | Default | t | Won't Boot without Battery, thereabout 20V 0.03A | |
| PPVCCGT_CPU_PH1 | Default | d | 0.006 | |
| PPVCCGT_CPU_PH1 | Default | r | 5,600R | |
| PPVCCGT_CPU_PH1 | Default | v | 1,500 | |
| PPVCCGT_CPU_PH2 | Default | d | 0.006 | |
| PPVCCGT_CPU_PH2 | Default | r | 5,600R | |
| PPVCCGT_CPU_PH2 | Default | v | 1,500 | |
| PPVCCGT_S0_CPU | Default | d | 0.006 | |
| PPVCCGT_S0_CPU | Default | r | 5,600R | |
| PPVCCGT_S0_CPU | Default | v | 1,500 | |
| PPVCCIO_S0_CPU | Default | d | 0.076 | |
| PPVCCPRIMCORE_PRIM_REG | Default | d | 0.073 | |
| PPVCCPRIMCORE_PRIM_REG | Default | r | 143.000 | |
| PPVCCPRIMCORE_PRIM_REG | Default | v | 1,050 | |
| PPVCCPRIM_FETIN | Default | d | 0.129 | |
| PPVCCSA_CPU_R | Default | d | 0.022 | |
| PPVCCSA_CPU_R | Default | r | 22,200R | |
| PPVCCSA_CPU_R | Default | v | 1,150 | |
| PPVCCSA_S0_CPU | Default | d | 0.022 | |
| PPVCCSA_S0_CPU | Default | r | 22,200R | |
| PPVCCSA_S0_CPU | Default | v | 1,150 | |
| PPVCCSPI_PRIM_PCH | Default | d | 0.325 | |
| PPVCC_CPU_PH1 | Default | d | 0.002 | |
| PPVCC_CPU_PH1 | Default | r | 2.100R | |
| PPVCC_CPU_PH1 | Default | v | 1,500 | |
| PPVCC_CPU_PH2 | Default | d | 0.002 | |
| PPVCC_CPU_PH2 | Default | r | 2.100R | |
| PPVCC_CPU_PH2 | Default | v | 1,500 | |
| PPVCC_CPU_PH3 | Default | d | 0.002 | |
| PPVCC_CPU_PH3 | Default | r | 2,100R | |
| PPVCC_CPU_PH3 | Default | v | 1,500 | |
| PPVCC_S0_CPU | Default | d | 0.002 | |
| PPVCC_S0_CPU | Default | r | 2,100R | |
| PPVCC_S0_CPU | Default | v | 1,500 | |
| PPVCORE_S0_GFX_PH1 | Default | d | 0.002 | |
| PPVCORE_S0_GFX_PH1 | Default | r | 2.100R | |
| PPVCORE_S0_GFX_PH1 | Default | t | 1~2R | |
| PPVCORE_S0_GFX_PH2 | Default | d | 0.002 | |
| PPVCORE_S0_GFX_PH2 | Default | r | 2.100R | |
| PPVCORE_S0_GFX_PH2 | Default | v | 1,100 | |
| PPVCORE_S0_GFX_PH3 | Default | d | 0.002 | |
| PPVCORE_S0_GFX_PH3 | Default | r | 2.100R | |
| PPVCORE_S0_GFX_PH3 | Default | v | 1,100 | |
| PPVCORE_S0_GPU | Default | d | 0,002 | |
| PPVCORE_S0_GPU | Default | r | 2.100R | |
| PPVCORE_S0_GPU | Default | v | 1,100 | |
| PPVDDCI_S0_GPU | Default | d | 0.035 | |
| PPVDDCI_S0_GPU | Default | r | 34.400R | |
| PPVDDCI_S0_GPU | Default | v | 0,900 | |
| PPVDDCPUSRAM_AWAKE | Default | d | 0.416 | |
| PPVDDCPUSRAM_AWAKE | Default | r | 411.000 | |
| PPVDDCPUSRAM_AWAKE | Default | v | 1,000 | |
| PPVDDCPU_AWAKE | Default | d | 0.019 | |
| PPVDDCPU_AWAKE | Default | r | 19.000R | |
| PPVDDCPU_AWAKE | Default | v | 0,625 | |
| PPVIN_G3H_P3V3G3HRTC_R | Default | d | 0.436 | |
| PPVIN_G3H_P3V3G3HRTC_R | Default | v | 3,300 | |
| PPVIN_G3H_TPAD_FUSE | Default | d | 0.434 | |
| PPVIN_G3H_TPAD_FUSE | Default | v | 12.600 | |
| PPVIN_RFLDO_WLANBT | Default | d | 0.000 | |
| PPVIN_RFLDO_WLANBT_C | Default | d | 0.347 | |
| PPVIN_S0GPU_1V8_RC | Default | d | 0.443 | |
| PPVIN_S0SW_LCDBKLT | Default | d | 0.870 | |
| PPVIN_S0SW_LCDBKLT | Default | r | 0.549R | |
| PPVIN_S0SW_LCDBKLT | Default | v | 12,600 | |
| PPVIN_S0SW_LCDBKLT_FET | Default | d | 0.434 | |
| PPVIN_S0SW_LCDBKLT_FET | Default | v | 12,600 | |
| PPVIN_S0SW_LCDBKLT_R | Default | d | 0.434 | |
| PPVIN_S0SW_LCDBKLT_R | Default | v | 12,600 | |
| PPVIN_S0_CPUVR_VIN | Default | d | 0.438 | |
| PPVIN_S0_GFXIMVP_VIN | Default | d | 0.433 | |
| PPVIN_S3_DDR2V5_RC | Default | d | 0.442 | |
| PPVIN_SW_LCDBKLT_SW | Default | d | 0.870 | |
| PPVIN_SW_LCDBKLT_SW | Default | r | 0.549R | |
| PPVIN_SW_LCDBKLT_SW | Default | v | 12,600 | |
| PPVOUT_S0_LCDBKLT | Default | d | 1.142 | |
| PPVOUT_S0_LCDBKLT | Default | v | 59,000 | |
| PPVTT_VTTREF | Default | d | 0.507 | |
| PROG1_CPUCOREVR | Default | d | 0.620 | |
| PROG2_CPUCOREVR | Default | d | 0.616 | |
| PROG3_CPUCOREVR | Default | d | 0.598 | |
| PROG4_CPUCOREVR | Default | d | 0.624 | |
| PROG5_CPUCOREVR | Default | d | 0.624 | |
| PVCCCGT_PH1_AGND | Default | d | 0.000 | |
| PVCCCGT_PH1_VCC | Default | d | 0.412 | |
| PVCCCGT_PH2_AGND | Default | d | 0.000 | |
| PVCCCGT_PH2_VCC | Default | d | 0.410 | |
| PVCCCORE_PH1_AGND | Default | d | 0.000 | |
| PVCCCORE_PH1_VCC | Default | d | 0.411 | |
| PVCCCORE_PH2_AGND | Default | d | 0.000 | |
| PVCCCORE_PH2_VCC | Default | d | 0.410 | |
| PVCCCORE_PH3_AGND | Default | d | 0.000 | |
| PVCCCORE_PH3_VCC | Default | d | 0.410 | |
| PVCCCSA_AGND | Default | d | 0.000 | |
| PVCCCSA_VCIN | Default | d | 0.408 | |
| PVCCEDRAM_REFIN | Default | d | 0.707 | |
| PVCCIOS0_AGND | Default | d | 0.000 | |
| PVCCIOS0_CS_N | Default | d | 0.076 | |
| PVCCIOS0_CS_P | Default | d | 0.076 | |
| PVCCIOS0_EN | Default | d | 0.782 | |
| PVCCIOS0_EN_FILT | Default | d | 0.752 | |
| PVCCIOS0_EN_FILT_BUF | Default | d | 0.552 | |
| PVCCIOS0_EN_R | Default | d | 0.800 | |
| PVCCIOS0_FB | Default | d | 0.538 | |
| PVCCIOS0_FSEL | Default | d | 0.555 | |
| PVCCIOS0_RTN | Default | d | 0.542 | |
| PVCCIOS0_SREF | Default | d | 0.552 | |
| PVCCIOS0_VO | Default | d | 0.547 | |
| PVCCIO_BOOT_RC | Default | d | 0.579 | |
| PVCCIO_DRVH | Default | d | 0.554 | |
| PVCCIO_DRVH_R | Default | d | 0.554 | |
| PVCCIO_DRVL | Default | d | 0.458 | |
| PVCCIO_DRVL_R | Default | d | 0.460 | |
| PVCCIO_EN | Default | d | 0.762 | |
| PVCCIO_LL | Default | d | 0.079 | |
| PVCCIO_LL_SNUB | Default | d | OL | |
| PVCCIO_PGOOD | Default | d | 0.550 | |
| PVCCIO_PHASE | Default | d | 0.076 | |
| PVCCIO_PHASE | Default | r | 60.000R | |
| PVCCIO_VBST | Default | d | 0.576 | |
| PVCCOIOS0_OCSET | Default | d | 0.548 | |
| PVCCPLLOC_EN | Default | d | 0.533 | |
| PVCCPRIMCORE_FB | Default | d | 0.130 | |
| PVCCPRIMCORE_FB_R | Default | d | 0.131 | |
| PVCCPRIMCORE_SW0 | Default | d | 0.073 | |
| PVCCPRIMCORE_SW0 | Default | r | 143.000 | |
| PVCCPRIMCORE_SW0 | Default | v | 1,050 | |
| PVCCPRIMCORE_SW1 | Default | d | 0.073 | |
| PVCCPRIMCORE_SW1 | Default | r | 143.000 | |
| PVCCPRIMCORE_SW1 | Default | v | 1,050 | |
| PVCORE_GPU_FB_SNS_N | Default | d | 0.000 | |
| PVCORE_GPU_FB_SNS_P | Default | d | 0.000 | |
| PVDDCI_GPU_FB_SNS_N | Default | d | 0.000 | |
| PVDDCI_GPU_FB_SNS_P | Default | d | 0.036 | |
| PVDDCI_GPU_FB_SNS_P | Default | r | 35.020R | |
| PVDDCI_PGOOD | Default | d | 0.555 | |
| PVDDCPUAWAKE_FB | Default | d | 0.011 | |
| PVDDCPUAWAKE_FB | Default | r | 16.700R | |
| PVDDCPUAWAKE_FB_R | Default | d | 0.018 | |
| PVDDCPUAWAKE_FB_R | Default | r | 17.000R | |
| PVDDCPUAWAKE_SW0 | Default | d | 0.019 | |
| PVDDCPUAWAKE_SW0 | Default | r | 19,000R | |
| PVDDCPUAWAKE_SW0 | Default | v | 0,625 | |
| PVDDCPUAWAKE_SW1 | Default | d | 0.019 | |
| PVDDCPUAWAKE_SW1 | Default | r | 19,000R | |
| PVDDCPUAWAKE_SW1 | Default | v | 0,625 | |
| PVDDCPUAWAKE_SW2 | Default | d | 0.019 | |
| PVDDCPUAWAKE_SW2 | Default | r | 19,000R | |
| PVDDCPUAWAKE_SW2 | Default | v | 0,625 | |
| PVDDCPUAWAKE_SW3 | Default | d | 0.019 | |
| PVDDCPUAWAKE_SW3 | Default | r | 19.000R | |
| PVDDCPUAWAKE_SW3 | Default | v | 0,625 | |
| PVDDCPUSRAMAWAKE_SW0 | Default | d | 0.416 | |
| PVDDCPUSRAMAWAKE_SW0 | Default | r | 411.000 | |
| PVDDCPUSRAMAWAKE_SW0 | Default | v | 1,000 | |
| PVDDQ_EN | Default | d | 0.739 | |
| PVDDQ_EN_LED | Default | d | OL | |
| PVDDQ_EN_R | Default | d | 0.503 | |
| PVDDQ_PGOOD | Default | d | 0.504 | |
| PVIN_RFLDO_WLANBT_VLX | Default | d | 0.347 | |
| PVPP_EN_R | Default | d | 0.738 | |
| PVTT_VTTSNS | Default | d | 0.126 | |
| REG_BOOT_GPU_VDDCI | Default | d | 0.508 | |
| REG_BOOT_GPU_VDDCI_RC | Default | d | 0.510 | |
| REG_FB_P1V8GPU | Default | d | 1.415 | |
| REG_FB_P2V5S3 | Default | d | 1.414 | |
| REG_GPU_VDDCI_COMP | Default | d | 0.607 | |
| REG_GPU_VDDCI_FB | Default | d | 0.503 | |
| REG_GPU_VDDCI_FB2_R | Default | d | OL | |
| REG_GPU_VDDCI_FB_R | Default | d | OL | |
| REG_GPU_VDDCI_FCCM | Default | d | 0.624 | |
| REG_GPU_VDDCI_IMON | Default | d | 0.635 | |
| REG_GPU_VDDCI_ISEN1 | Default | d | 0.632 | |
| REG_GPU_VDDCI_ISUMN | Default | d | 0.502 | |
| REG_GPU_VDDCI_ISUMP | Default | d | 0.583 | |
| REG_GPU_VDDCI_VSEN | Default | d | 0.037 | |
| REG_GPU_VDDCI_VSEN | Default | r | 35.800R | |
| REG_GPU_VDDCI_VSUMN | Default | d | 0.035 | |
| REG_GPU_VDDCI_VSUMN | Default | v | 0,900 | |
| REG_GPU_VDDCI_VSUMN_R | Default | d | 0.037 | |
| REG_GPU_VDDCI_VSUMN_R | Default | r | 358.000R | |
| REG_GPU_VDDCI_VSUMP | Default | d | 0.035 | |
| REG_GPU_VDDCI_VSUMP | Default | v | 0,900 | |
| REG_LGATE_GPU_VDDCI | Default | d | 0.469 | |
| REG_PHASE_1V8GPU | Default | d | 0.277 | |
| REG_PHASE_1V8GPU | Default | r | 280.000R | |
| REG_PHASE_2V5S3 | Default | d | 0.360 | |
| REG_PHASE_2V5S3 | Default | r | 500.000R | |
| REG_PHASE_2V5S3 | Default | v | 2,500 | |
| REG_PHASE_GPU_VDDCI | Default | d | 0.036 | |
| REG_SNUBBER_GPU_VDDCI | Default | d | OL | |
| REG_SSTR_P1V8GPU | Default | d | 0.755 | |
| REG_SSTR_P2V5S3 | Default | d | 0.755 | |
| REG_UGATE_GPU_VDDCI | Default | d | 0.522 | |
| REG_UGATE_GPU_VDDCI_R | Default | d | 0.522 | |
| REG_VOS_P1V8GPU | Default | d | 0.280 | |
| REG_VOS_P2V5S3 | Default | d | 0.368 | |
| RTN_A_CPUCORE | Default | d | 0.000 | |
| RTN_B_CPUGT | Default | d | 0.000 | |
| RTN_C_CPUSA | Default | d | 0.000 | |
| SAVE_BAT_G | Default | d | 0.775 | |
| SAVE_BAT_S | Default | d | 1.568 | |
| SAVE_XA_CC1_G | Default | d | 0.801 | |
| SAVE_XA_CC2_G | Default | d | 0.802 | |
| SAVE_XA_CC2_Z | Default | d | OL | |
| SAVE_XB_CC1_B | Default | d | OL | |
| SAVE_XB_CC1_G | Default | d | 0.863 | |
| SAVE_XB_CC1_Z | Default | d | OL | |
| SAVE_XB_CC2_B | Default | d | OL | |
| SAVE_XB_CC2_G | Default | d | 0.838 | |
| SAVE_XB_CC2_Z | Default | d | OL | |
| SA_ISUMN_R | Default | d | 1.027 | |
| SENSOR_PWR_EN | Default | d | 0.718 | |
| SEP_CAM_DISABLE_DFF_L | Default | d | 0.514 | |
| SEP_CAM_DISABLE_DFF_R_L | Default | d | 0.511 | |
| SEP_CAM_DISABLE_L | Default | d | 0.479 | |
| SEP_DISABLE_STROBE | Default | d | 0.483 | |
| SEP_DMIC_DISABLE_L | Default | d | 0.481 | |
| SEP_DMIC_DISABLE_Q_L | Default | d | 0.669 | |
| SE_CTLR_FW_DWLD | Default | d | 0.478 | |
| SE_DEV_WAKE | Default | d | 0.481 | |
| SE_PWR_EN | Default | d | 0.740 | |
| SMBUS_3V3_BATT_SCL | Default | d | 0.94 | |
| SMBUS_3V3_BATT_SDA | Default | d | 0.96 | |
| SMBUS_PCH_CLK | Default | d | 0.822 | |
| SMBUS_PCH_DATA | Default | d | 0.822 | |
| SMCRST_TIEOFF | Default | d | 0.721 | |
| SMC_BMON_ISENSE | Default | d | 0.809 | |
| SMC_DCIN_VSENSE | Default | d | 0.809 | |
| SMC_DEBUGPRT_RX | Default | d | 0.492 | |
| SMC_DEBUGPRT_TX | Default | d | 0.491 | |
| SMC_FAN_0_PWM | Default | d | 0.45 | |
| SMC_FAN_0_TACH | Default | d | 0.45 | |
| SMC_FAN_0_TACH | Default | v | 1.800 | |
| SMC_FAN_1_PWM | Default | d | 0.492 | |
| SMC_FAN_1_TACH | Default | d | 0.45 | |
| SMC_FAN_1_TACH | Default | v | 1.800 | |
| SMC_FIXTURE_MODE_L | Default | d | 0.492 | |
| SMC_GPU_THRMTRIP | Default | d | 0.488 | |
| SMC_LID_LEFT | Default | d | 0.657 | |
| SMC_LID_RIGHT | Default | d | 0.646 | |
| SMC_P3V3_CAPLE_ISENSE | Default | d | 0.809 | |
| SMC_PBUS_VSENSE | Default | d | 0.809 | |
| SMC_PCH_PWROK | Default | d | 0.469 | |
| SMC_PCH_SYS_PWROK | Default | d | 0.465 | |
| SMC_PECI_RX | Default | d | 0.463 | |
| SMC_PECI_TX | Default | d | 0.474 | |
| SMC_PECI_TX_R | Default | d | 0.457 | |
| SMC_PROCHOT_L | Default | d | 0.471 | |
| SMC_RSMRST_L | Default | d | 0.459 | |
| SMC_SYSRST_L | Default | d | 0.466 | |
| SOC_AMBER_DFU | Default | d | OL | |
| SOC_AMBER_R | Default | d | OL | |
| SOC_BLUE_AWAKE | Default | d | 0.451 | |
| SOC_BLUE_R | Default | d | OL | |
| SOC_CLKREQ_L | Default | d | 0.812 | |
| SOC_COLD_RESET_L | Default | d | 0.430 | |
| SOC_DEBUGPRT_RX | Default | d | 0.482 | |
| SOC_DEBUGPRT_TX | Default | d | 0.483 | |
| SOC_DFU_STATUS | Default | d | 0.480 | |
| SOC_DOCK_CONNECT | Default | d | 0.490 | |
| SOC_FORCE_DFU | Default | d | 0.480 | |
| SOC_GPU_THRMTRIP | Default | d | 0.686 | |
| SOC_GREEN_DDR | Default | d | OL | |
| SOC_GREEN_R | Default | d | OL | |
| SOC_HOLD_RESET | Default | d | 0.471 | |
| SOC_JTAG_SEL | Default | d | 0.492 | |
| SOC_PERST_L | Default | d | 0.493 | |
| SOC_PM_THRMTRIP_L | Default | d | 0.772 | |
| SOC_PM_THRMTRIP_L_R | Default | d | 0.689 | |
| SOC_RED_R | Default | d | OL | |
| SOC_RED_SLPS2R | Default | d | OL | |
| SOC_SOCHOT_L | Default | d | 0.483 | |
| SOC_SWD_MUX_SEL_PCH | Default | d | 0.622 | |
| SOC_TESTMODE | Default | d | 0.482 | |
| SOC_USB_VBUS | Default | d | 0.683 | |
| SOC_VDDCPU_SENSE | Default | d | 0.019 | |
| SOC_VDDCPU_SENSE | Default | r | 18.700R | |
| SOC_WDOG | Default | d | 0.494 | |
| SPIROM_USE_MLB | Default | d | 0.828 | |
| SPI_ACCEL_CS_L | Default | d | 0.496 | |
| SPI_AOP_SENSOR_CLK | Default | d | 0.515 | |
| SPI_AOP_SENSOR_MISO | Default | d | 0.493 | |
| SPI_AOP_SENSOR_MISO_R | Default | d | 0.515 | |
| SPI_AOP_SENSOR_MOSI | Default | d | 0.515 | |
| SPI_DFR_CLK | Default | d | 0.48 | |
| SPI_DFR_CS_L | Default | d | 0.46 | |
| SPI_DFR_MISO | Default | d | 0.493 | |
| SPI_DFR_MISO_R | Default | d | 0.47 | |
| SPI_DFR_MOSI | Default | d | 0.47 | |
| SPI_IO2_STRAP_L | Default | d | 0.740 | |
| SPI_IO<2> | Default | d | 0.799 | |
| SPI_IO<3> | Default | d | 0.802 | |
| SPI_MESA_CLK_CONN | Default | d | 0.52 | |
| SPI_MESA_MISO | Default | d | 0.484 | |
| SPI_MESA_MISO_CONN | Default | d | 0.45 | |
| SPI_MESA_MOSI_CONN | Default | d | 0.47 | |
| SPI_MOSI_R | Default | d | 0.807 | |
| SPI_MOSI_R_CONN | Default | d | 1.108 | |
| SPI_SOCROM_CLK | Default | d | 0.496 | |
| SPI_SOCROM_CS_L | Default | d | 0.486 | |
| SPI_SOCROM_MISO_R | Default | d | 0.391 | |
| SPI_SOCROM_MOSI | Default | d | 0.486 | |
| SPI_SOCROM_WP_L | Default | d | OL | |
| SPI_TPAD3V3_CLK | Default | d | 0.68 | |
| SPI_TPAD3V3_CLK_R | Default | d | 0.458 | |
| SPI_TPAD3V3_CS_L | Default | d | 0.66 | |
| SPI_TPAD3V3_MISO | Default | d | 0.66 | |
| SPI_TPAD3V3_MOSI | Default | d | 0.68 | |
| SPI_TPAD3V3_MOSI_R | Default | d | 0.486 | |
| SPI_TPAD_CS_L | Default | d | 0.451 | |
| SPI_TPAD_MISO | Default | d | 0.447 | |
| SPI_TPAD_MISO_R | Default | d | 0.440 | |
| SPKRAMP_INT_L | Default | d | 0.370 | |
| SPKRAMP_LT_AREG | Default | d | 0.588 | |
| SPKRAMP_LT_BSTN | Default | d | 0.779 | |
| SPKRAMP_LT_BSTP | Default | d | 0.779 | |
| SPKRAMP_LT_DREG | Default | d | 0.530 | |
| SPKRAMP_LT_MODE | Default | d | 0.000 | |
| SPKRAMP_LT_OUTN | Default | d | 0.533 | |
| SPKRAMP_LT_OUTP | Default | d | 0.533 | |
| SPKRAMP_LW_AREG | Default | d | 0.587 | |
| SPKRAMP_LW_BSTN | Default | d | 0.779 | |
| SPKRAMP_LW_BSTP | Default | d | 0.779 | |
| SPKRAMP_LW_DREG | Default | d | 0.527 | |
| SPKRAMP_LW_MODE | Default | d | 0.405 | |
| SPKRAMP_LW_OUTN | Default | d | 0.533 | |
| SPKRAMP_LW_OUTP | Default | d | 0.533 | |
| SPKRAMP_RESET_L | Default | d | 0.368 | |
| SPKRAMP_RT_DREG | Default | d | 0.532 | |
| SPKRAMP_RT_MODE | Default | d | 0.460 | |
| SPKRAMP_RT_OUTN | Default | d | 0.525 | |
| SPKRAMP_RT_OUTP | Default | d | 0.520 | |
| SPKRAMP_RW_AREG | Default | d | 0.592 | |
| SPKRAMP_RW_BSTN | Default | d | 0.779 | |
| SPKRAMP_RW_BSTP | Default | d | 0.779 | |
| SPKRAMP_RW_DREG | Default | d | 0.531 | |
| SPKRAMP_RW_MODE | Default | d | 0.466 | |
| SPKRAMP_RW_OUTN | Default | d | 0.520 | |
| SPKRAMP_RW_OUTP | Default | d | 0.520 | |
| SPKRCONN_LT_OUTN | Default | d | 0.533 | |
| SPKRCONN_LT_OUTP | Default | d | 0.533 | |
| SPKRCONN_LW_OUTN | Default | d | 0.533 | |
| SPKRCONN_LW_OUTP | Default | d | 0.533 | |
| SPKRCONN_RT_OUTN | Default | d | 0.525 | |
| SPKRCONN_RT_OUTP | Default | d | 0.517 | |
| SPKRCONN_RW_OUTN | Default | d | 0.520 | |
| SPKRCONN_RW_OUTP | Default | d | 0.520 | |
| SPKR_ID0 | Default | d | 0.485 | |
| SPROM_CLK | Default | d | 0.508 | |
| SPROM_CS | Default | d | 0.504 | |
| SPROM_DIN | Default | d | 0.512 | |
| SPROM_DOUT | Default | d | 0.512 | |
| SSD0_CLKREQ0_L | Default | d | 0.461 | |
| SSD0_CLKREQ1_L | Default | d | 0.453 | |
| SSD0_CLKREQ2_L | Default | d | 0.452 | |
| SSD0_CLKREQ3_L | Default | d | 0.463 | |
| SSD0_OCARINA_FORCE_EN | Default | d | 0.584 | |
| SSD0_OCARINA_NAND_VCC_DET | Default | d | 0.763 | |
| SSD0_OCARINA_PGOOD | Default | d | 0.764 | |
| SSD0_OCARINA_POK2 | Default | d | 0.000 | |
| SSD0_OCARINA_RESET_L | Default | d | 0.438 | |
| SSD0_OCARINA_TCAL | Default | d | 0.776 | |
| SSD0_OCARINA_VDD_LDO | Default | d | 0.368 | |
| SSD0_OCARINA_VREF | Default | d | 0.772 | |
| SSD0_OCARINA_WP_L | Default | d | 0.522 | |
| SSD0_PCIE_RESET_L | Default | d | 0.428 | |
| SSD0_S4E0_DROOP_L | Default | d | 0.505 | |
| SSD0_S4E0_JTAG_TDI | Default | d | 0.499 | |
| SSD0_S4E0_JTAG_TDO | Default | d | 0.466 | |
| SSD0_S4E0_PCIE_RESREF | Default | d | 0.786 | |
| SSD0_S4E0_UART_TX | Default | d | 0.496 | |
| SSD0_S4E0_VPP | Default | d | 0.550 | |
| SSD0_S4E0_ZQ_C | Default | d | 0.101 | |
| SSD0_S4E0_ZQ_L | Default | d | 0.303 | |
| SSD0_S4E1_DROOP_L | Default | d | 0.489 | |
| SSD0_S4E1_JTAG_TDO | Default | d | 0.460 | |
| SSD0_S4E1_PCIE_RESREF | Default | d | 0.789 | |
| SSD0_S4E1_UART_TX | Default | d | 0.479 | |
| SSD0_S4E1_VPP | Default | d | 0.553 | |
| SSD0_S4E1_ZQ_C | Default | d | 0.101 | |
| SSD0_S4E1_ZQ_L | Default | d | 0.303 | |
| SSD0_S4E2_DROOP_L | Default | d | 0.483 | |
| SSD0_S4E2_JTAG_TDO | Default | d | 0.468 | |
| SSD0_S4E2_PCIE_RESREF | Default | d | 0.787 | |
| SSD0_S4E2_UART_TX | Default | d | 0.479 | |
| SSD0_S4E2_VPP | Default | d | 0.552 | |
| SSD0_S4E2_ZQ_C | Default | d | 0.102 | |
| SSD0_S4E2_ZQ_L | Default | d | 0.304 | |
| SSD0_S4E3_DROOP_L | Default | d | 0.509 | |
| SSD0_S4E3_JTAG_TDO | Default | d | 0.504 | |
| SSD0_S4E3_PCIE_RESREF | Default | d | 0.786 | |
| SSD0_S4E3_UART_TX | Default | d | 0.505 | |
| SSD0_S4E3_VPP | Default | d | 0.550 | |
| SSD0_S4E3_ZQ_C | Default | d | 0.102 | |
| SSD0_S4E3_ZQ_L | Default | d | 0.305 | |
| SSD0_S4E_JTAG_SEL | Default | d | 0.439 | |
| SSD0_S4E_JTAG_TRST_L | Default | d | 0.440 | |
| SSD0_STG01_ADDR | Default | d | 0.582 | |
| SSD0_SWCLK_UART_R2D | Default | d | 0.437 | |
| SSD0_SWDIO_UART_D2R | Default | d | 0.433 | |
| SSD0_TPS62180_FB | Default | d | 1.411 | |
| SSD0_TPS62180_FB_R | Default | d | 0.376 | |
| SSD0_TPS62180_SS | Default | d | 0.540 | |
| SSD0_VR_P2V5_EN | Default | d | 0.650 | |
| SSD0_VR_P2V5_EN_R | Default | d | 0.651 | |
| SSD0_VR_P2V5_PGOOD | Default | d | 0.575 | |
| SSD1_CLK24M | Default | d | OL | |
| SSD1_CLKREQ0_L | Default | d | OL | |
| SSD1_CLKREQ1_L | Default | d | 0.491 | |
| SSD1_CLKREQ2_L | Default | d | 0.490 | |
| SSD1_CLKREQ3_L | Default | d | OL | |
| SSD1_OCARINA_FORCE_EN | Default | d | OL | |
| SSD1_OCARINA_IREF | Default | d | OL | |
| SSD1_OCARINA_NAND_VCC_DET | Default | d | OL | |
| SSD1_OCARINA_PGOOD | Default | d | OL | |
| SSD1_OCARINA_POK2 | Default | d | OL | |
| SSD1_OCARINA_RESET_L | Default | d | OL | |
| SSD1_OCARINA_TCAL | Default | d | OL | |
| SSD1_OCARINA_VDD_LDO | Default | d | OL | |
| SSD1_OCARINA_VREF | Default | d | OL | |
| SSD1_OCARINA_WP_L | Default | d | OL | |
| SSD1_PCIE_RESET_L | Default | d | 0.476 | |
| SSD1_S4E0_JTAG_TDI | Default | d | OL | |
| SSD1_S4E0_JTAG_TDO | Default | d | OL | |
| SSD1_S4E0_PCIE_RESREF | Default | d | OL | |
| SSD1_S4E0_UART_TX | Default | d | OL | |
| SSD1_S4E0_VPP | Default | d | OL | |
| SSD1_S4E0_ZQ_C | Default | d | OL | |
| SSD1_S4E0_ZQ_L | Default | d | OL | |
| SSD1_S4E1_JTAG_TDO | Default | d | OL | |
| SSD1_S4E1_PCIE_RESREF | Default | d | OL | |
| SSD1_S4E1_UART_TX | Default | d | OL | |
| SSD1_S4E1_VPP | Default | d | OL | |
| SSD1_S4E1_ZQ_C | Default | d | OL | |
| SSD1_S4E1_ZQ_L | Default | d | OL | |
| SSD1_S4E2_JTAG_TDO | Default | d | OL | |
| SSD1_S4E2_PCIE_RESREF | Default | d | OL | |
| SSD1_S4E2_UART_TX | Default | d | OL | |
| SSD1_S4E2_VPP | Default | d | OL | |
| SSD1_S4E2_ZQ_C | Default | d | OL | |
| SSD1_S4E2_ZQ_L | Default | d | OL | |
| SSD1_S4E3_JTAG_TDO | Default | d | OL | |
| SSD1_S4E3_PCIE_RESREF | Default | d | OL | |
| SSD1_S4E3_UART_TX | Default | d | OL | |
| SSD1_S4E3_VPP | Default | d | OL | |
| SSD1_S4E3_ZQ_C | Default | d | OL | |
| SSD1_S4E3_ZQ_L | Default | d | OL | |
| SSD1_S4E_JTAG_SEL | Default | d | OL | |
| SSD1_S4E_JTAG_TRST_L | Default | d | OL | |
| SSD1_TPS62180_FB | Default | d | OL | |
| SSD1_TPS62180_SS | Default | d | OL | |
| SSD1_VR_P2V5_EN | Default | d | OL | |
| SSD1_VR_P2V5_EN_R | Default | d | OL | |
| SSD1_VR_P2V5_PGOOD | Default | d | OL | |
| SSD_BFH | Default | d | 0.430 | |
| SSD_PMU_RESET_L | Default | d | 0.473 | |
| SSTATE_BLUE | Default | d | OL | |
| SSTATE_BLUE_R | Default | d | OL | |
| SSTATE_GREEN | Default | d | OL | |
| SSTATE_GREEN_R | Default | d | OL | |
| SSTATE_RED | Default | d | OL | |
| SSTATE_RED_R | Default | d | OL | |
| SWD_SOC_SWCLK | Default | d | 0.489 | |
| SWD_SOC_SWDIO | Default | d | 0.490 | |
| SYS_DETECT | Default | d | OL | |
| SYS_DETECT_L | Default | d | 0.55 | |
| TBTTHMSNS_T_D1_N | Default | d | 0.000 | |
| TBTTHMSNS_T_D1_P | Default | d | 0.653 | |
| TBTTHMSNS_X_D1_N | Default | d | 0.000 | |
| TBTTHMSNS_X_D1_P | Default | d | 0.652 | |
| TBT_POC_RESET | Default | d | 0.66 | |
| TBT_PWR_EN | Default | d | 0.745 | |
| TBT_PWR_EN_U8295 | Default | d | 0.574 | |
| TBT_PWR_EN_U8297 | Default | d | 0.575 | |
| TBT_TA_LSRX | Default | d | 0.774 | |
| TBT_TA_USB2_MXCTL | Default | d | 0.601 | |
| TBT_TA_USB2_RBIAS | Default | d | 0.210 | |
| TBT_TB_USB2_MXCTL | Default | d | 0.598 | |
| TBT_TB_USB2_RBIAS | Default | d | 0.202 | |
| TBT_T_BATLOW_L | Default | d | 0.600 | |
| TBT_T_CIO_PWR_EN | Default | d | 0.57 | |
| TBT_T_CLKREQ_L | Default | d | 0.810 | |
| TBT_T_CLKREQ_R_L | Default | d | 0.601 | |
| TBT_T_HDMI_DDC_CLK | Default | d | 0.601 | |
| TBT_T_HDMI_DDC_DATA | Default | d | 0.601 | |
| TBT_T_PCI_RESET_L | Default | d | 0.595 | |
| TBT_T_RBIAS | Default | d | 0.781 | |
| TBT_T_ROM_HOLD_L | Default | d | 0.708 | |
| TBT_T_ROM_WP_L | Default | d | 0.592 | |
| TBT_T_RSENSE | Default | d | 0.000 | |
| TBT_T_RTD3_PWR_EN | Default | d | 0.599 | |
| TBT_T_SPI_CLK | Default | d | 0.570 | |
| TBT_T_SPI_CLK_DBG | Default | d | 0.64 | |
| TBT_T_SPI_CS_L | Default | d | 0.601 | |
| TBT_T_SPI_MISO | Default | d | 0.602 | |
| TBT_T_SPI_MOSI | Default | d | 0.606 | |
| TBT_T_TEST_EN | Default | d | 0.100 | |
| TBT_T_TEST_PWR_GOOD | Default | d | 0.101 | |
| TBT_T_TMU_CLK_IN | Default | d | 0.603 | |
| TBT_T_USB_PWR_EN | Default | d | 0.57 | |
| TBT_T_XTAL25M_IN | Default | d | 0.840 | |
| TBT_T_XTAL25M_OUT | Default | d | 0.792 | |
| TBT_WAKE_3V3_L | Default | d | 0.57 | |
| TBT_XA_LSRX | Default | d | 0.537 | |
| TBT_XA_LSTX | Default | d | 0.815 | |
| TBT_XB_LSRX | Default | d | 0.788 | |
| TBT_XB_LSTX | Default | d | 0.80 | |
| TBT_X_CIO_PWR_EN | Default | d | 0.58 | |
| TBT_X_HDMI_DDC_CLK | Default | d | 0.601 | |
| TBT_X_HDMI_DDC_DATA | Default | d | 0.600 | |
| TBT_X_PCIE_BIAS | Default | d | 0.792 | |
| TBT_X_PCI_RESET_L | Default | d | 0.59 | |
| TBT_X_PLUG_EVENT_L | Default | d | 0.59 | |
| TBT_X_RBIAS | Default | d | 0.782 | |
| TBT_X_ROM_HOLD_L | Default | d | 0.708 | |
| TBT_X_ROM_WP_L | Default | d | 0.591 | |
| TBT_X_RSENSE | Default | d | 0.001 | |
| TBT_X_RSENSE | Default | r | 0.600R | |
| TBT_X_RTD3_PWR_EN | Default | d | 0.598 | |
| TBT_X_SPI_CLK | Default | d | 0.567 | |
| TBT_X_SPI_CLK_DBG | Default | d | 0.65 | |
| TBT_X_SPI_CS_L | Default | d | 0.599 | |
| TBT_X_SPI_MISO | Default | d | 0.602 | |
| TBT_X_SPI_MOSI | Default | d | 0.604 | |
| TBT_X_TEST_EN | Default | d | 0.100 | |
| TBT_X_TEST_PWR_GOOD | Default | d | 0.100 | |
| TBT_X_TMU_CLK_IN | Default | d | 0.601 | |
| TBT_X_TMU_CLK_OUT | Default | d | 0.600 | |
| TBT_X_USB_PWR_EN | Default | d | 0.58 | |
| TBT_X_XTAL25M_IN | Default | d | 0.838 | |
| TBT_X_XTAL25M_OUT | Default | d | 0.790 | |
| TPAD3V3_ACTUATOR_DISABLE_L | Default | d | 0.84 | |
| TPAD3V3_SPI_EN | Default | d | 0.66 | |
| TPAD3V3_SPI_INT_L | Default | d | 0.85 | |
| TPAD_ACTUATOR_DISABLE_L | Default | d | 0.495 | |
| TPAD_KBD_WAKE_L | Default | d | 0.45 | |
| TPAD_SPI_EN | Default | d | 0.481 | |
| TPAD_SPI_INT_L | Default | d | 0.45 | |
| TP_BKLT_BOOST_EN | Default | d | 0.618 | |
| TP_BKLT_FAULT_L | Default | d | 0.614 | |
| TP_BMON_IOUT | Default | d | OL | |
| TP_BT_JTAG_STRAP | Default | d | 0.728 | |
| TP_CHGR_EN_VR1 | Default | d | 0.61 | |
| TP_CHGR_SMC_RST_L | Default | d | 0.60 | |
| TP_CPU_RSVD_TP75 | Default | d | 0.335 | |
| TP_CPU_RSVD_TP76 | Default | d | 0.242 | |
| TP_CPU_RSVD_TP_BT2 | Default | d | 0.340 | |
| TP_CPU_RSVD_TP_D1 | Default | d | 0.243 | |
| TP_DFR_TOUCH_PANEL_DETECT | Default | d | OL | |
| TP_DFR_TOUCH_ROM_WC | Default | d | OL | |
| TP_DFR_TOUCH_RSVD | Default | d | OL | |
| TP_GPUVCORE_IMON | Default | d | 0.635 | |
| TP_HDA_RST | Default | d | 0.823 | |
| TP_HDA_SDI1 | Default | d | 0.823 | |
| TP_HDA_SDO | Default | d | 0.823 | |
| TP_JTAG_SOC_TRST_L | Default | d | 0.494 | |
| TP_LCD_IRQ_L | Default | d | NA | |
| TP_PCH_SLP_SUS_L | Default | d | 0.817 | |
| TP_PCH_STRP_BOOT_SPI_L | Default | d | 0.828 | |
| TP_PCH_STRP_TLSCONF | Default | d | 0.829 | |
| TP_PCH_STRP_TOPBLK_SWP_L | Default | d | 0.829 | |
| TP_PCH_TP1_F22 | Default | d | 0.787 | |
| TP_PCH_TP3_B24 | Default | d | 0.838 | |
| TP_Q3100_DRAIN | Default | d | 0.59 | |
| TP_Q3200_DRAIN | Default | d | 0.675 | |
| TP_SSD0_S4E0_ANI0_VREF | Default | d | 0.591 | |
| TP_SSD0_S4E0_ANI1_VREF | Default | d | 0.591 | |
| TP_SSD0_S4E1_ANI0_VREF | Default | d | 0.592 | |
| TP_SSD0_S4E1_ANI1_VREF | Default | d | 0.592 | |
| TP_SSD0_S4E2_ANI0_VREF | Default | d | 0.591 | |
| TP_SSD0_S4E2_ANI1_VREF | Default | d | 0.592 | |
| TP_SSD0_S4E3_ANI0_VREF | Default | d | 0.591 | |
| TP_SSD0_S4E3_ANI1_VREF | Default | d | 0.591 | |
| TP_SSD1_S4E0_ANI0_VREF | Default | d | OL | |
| TP_SSD1_S4E0_ANI1_VREF | Default | d | OL | |
| TP_SSD1_S4E1_ANI0_VREF | Default | d | OL | |
| TP_SSD1_S4E1_ANI1_VREF | Default | d | OL | |
| TP_SSD1_S4E2_ANI0_VREF | Default | d | OL | |
| TP_SSD1_S4E2_ANI1_VREF | Default | d | OL | |
| TP_SSD1_S4E3_ANI0_VREF | Default | d | OL | |
| TP_SSD1_S4E3_ANI1_VREF | Default | d | OL | |
| TP_UPC_TA_SWD_CLK | Default | d | 0.748 | |
| TP_UPC_TA_SWD_DATA | Default | d | 0.747 | |
| TP_UPC_TB_SWD_CLK | Default | d | 0.748 | |
| TP_UPC_TB_SWD_DATA | Default | d | 0.749 | |
| TP_UPC_XA_SWD_CLK | Default | d | 0.751 | |
| TP_UPC_XA_SWD_DATA | Default | d | 0.751 | |
| TP_UPC_XB_SWD_CLK | Default | d | 0.73 | |
| TP_UPC_XB_SWD_DATA | Default | d | 0.73 | |
| TP_USBC_PP20V_TA | Default | d | OL | |
| TP_USBC_PP20V_TB | Default | d | OL | |
| TP_USBC_PP20V_XA | Default | d | OL | |
| TP_USBC_PP20V_XB | Default | d | OL | |
| TP_USBC_TB_RESET_L | Default | d | 0.778 | |
| TP_USBC_XA_RESET_L | Default | d | 0.780 | |
| TP_WLAN_PMU_TEST | Default | d | 0.000 | |
| TSNS_T1_DN | Default | d | 0.000 | |
| TSNS_T1_DX1_N | Default | d | 0.000 | |
| TSNS_T1_DX1_P | Default | d | 0.639 | |
| TSNS_T1_DX2_N | Default | d | 0.000 | |
| TSNS_T1_DX2_P | Default | d | 0.640 | |
| TSNS_T1_DX3_N | Default | d | 0.000 | |
| TSNS_T1_DX3_P | Default | d | 0.642 | |
| TSNS_T1_DX4_P | Default | d | 0.640 | |
| TSNS_T1_DX5_N | Default | d | 0.000 | |
| TSNS_T1_DX5_P | Default | d | 0.641 | |
| TSNS_T1_DX6_N | Default | d | 0.000 | |
| TSNS_T1_DX6_N | Default | r | 1.300R | |
| TSNS_T1_DX6_P | Default | d | 0.643 | |
| TSNS_T1_DX7_P | Default | d | 0.640 | |
| U4800_PIN4 | Default | d | 0.707 | |
| UART_BT_D2R | Default | d | 0.476 | |
| UART_BT_D2R_CTS_L | Default | d | 0.477 | |
| UART_BT_LH_D2R | Default | d | 0.000 | |
| UART_BT_MUX_CTS_L | Default | d | 0.641 | |
| UART_BT_MUX_D2R | Default | d | 0.647 | |
| UART_BT_MUX_R2D | Default | d | 0.645 | |
| UART_BT_MUX_RTS_L | Default | d | 0.645 | |
| UART_BT_R2D | Default | d | 0.477 | |
| UART_BT_R2D_RTS_L | Default | d | 0.474 | |
| UART_SE_D2R | Default | d | 0.484 | |
| UART_SE_D2R_CTS_L | Default | d | 0.483 | |
| UART_SE_R2D | Default | d | 0.485 | |
| UART_SE_R2D_RTS_L | Default | d | 0.485 | |
| UART_WLAN_D2R | Default | d | 0.486 | |
| UART_WLAN_D2R_CTS_L | Default | d | 0.485 | |
| UART_WLAN_R2D | Default | d | 0.485 | |
| UART_WLAN_R2D_RTS_L | Default | d | 0.483 | |
| UNCONNECTED_14 | Default | d | OL | |
| UNCONNECTED_15 | Default | d | OL | |
| UNCONNECTED_180 | Default | d | NA | |
| UNCONNECTED_188 | Default | d | OL | |
| UNCONNECTED_189 | Default | d | OL | |
| UNCONNECTED_190 | Default | d | OL | |
| UPC_I2C_INT_L | Default | d | 0.45 | |
| UPC_PMU_RESET | Default | d | 0.716 | |
| UPC_PMU_RESET | Default | t | 0 volt is normal | |
| UPC_TA_DBG3 | Default | d | 0.778 | |
| UPC_TA_DBG4 | Default | d | 0.778 | |
| UPC_TA_FAULT_L | Default | d | 0.762 | |
| UPC_TA_GATE1 | Default | d | 0.659 | |
| UPC_TA_GATE2 | Default | d | 0.659 | |
| UPC_TA_GPIO0 | Default | d | 0.774 | |
| UPC_TA_GPIO1 | Default | d | 0.772 | |
| UPC_TA_R_OSC | Default | d | 0.539 | |
| UPC_TA_SPI_CLK | Default | d | 0.584 | |
| UPC_TA_SPI_CS_L | Default | d | 0.617 | |
| UPC_TA_SPI_MISO | Default | d | 0.619 | |
| UPC_TA_SPI_MOSI | Default | d | 0.621 | |
| UPC_TA_SS | Default | d | 0.533 | |
| UPC_TA_UART_RX | Default | d | 0.74 | |
| UPC_TA_UART_TX | Default | d | 0.75 | |
| UPC_TB_DBG3 | Default | d | 0.778 | |
| UPC_TB_DBG4 | Default | d | 0.778 | |
| UPC_TB_FAULT_L | Default | d | 0.762 | |
| UPC_TB_GATE1 | Default | d | 0.659 | |
| UPC_TB_GATE2 | Default | d | 0.651 | |
| UPC_TB_GPIO0 | Default | d | 0.775 | |
| UPC_TB_GPIO1 | Default | d | 0.773 | |
| UPC_TB_GPIO7 | Default | d | 0.775 | |
| UPC_TB_R_OSC | Default | d | 0.536 | |
| UPC_TB_SS | Default | d | 0.533 | |
| UPC_T_5V_EN | Default | d | 0.704 | |
| UPC_T_5V_EN_R | Default | d | 0.554 | |
| UPC_T_SPI_CLK | Default | d | 0.594 | |
| UPC_T_SPI_CS_L | Default | d | 0.591 | |
| UPC_T_SPI_MISO | Default | d | 0.593 | |
| UPC_T_SPI_MOSI | Default | d | 0.568 | |
| UPC_XA_DBG1 | Default | d | 0.573 | |
| UPC_XA_FAULT_L | Default | d | 0.755 | |
| UPC_XA_GATE1 | Default | d | 0.64 | |
| UPC_XA_GATE2 | Default | d | 0.63 | |
| UPC_XA_GPIO0 | Default | d | 0.777 | |
| UPC_XA_R_OSC | Default | d | 0.787 | |
| UPC_XA_SS | Default | d | 0.530 | |
| UPC_XA_UART_RX | Default | d | 0.75 | |
| UPC_XA_UART_TX | Default | d | 0.74 | |
| UPC_XB_DBG3 | Default | d | 0.494 | |
| UPC_XB_DBG4 | Default | d | 0.495 | |
| UPC_XB_FAULT_L | Default | d | 0.74 | |
| UPC_XB_GATE2 | Default | d | 0.654 | |
| UPC_XB_GPIO0 | Default | d | 0.76 | |
| UPC_XB_GPIO1 | Default | d | 0.76 | |
| UPC_XB_R_OSC | Default | d | 0.53 | |
| UPC_XB_SPI_CLK | Default | d | 0.58 | |
| UPC_XB_SPI_CS_L | Default | d | 0.61 | |
| UPC_XB_SPI_MISO | Default | d | 0.61 | |
| UPC_XB_SPI_MOSI | Default | d | 0.61 | |
| UPC_XB_SS | Default | d | 0.53 | |
| UPC_X_5V_EN | Default | d | 0.705 | |
| UPC_X_5V_EN_R | Default | d | 0.558 | |
| UPC_X_SPI_CS_L | Default | d | 0.591 | |
| USB2_UPC_TA_N | Default | d | 0.522 | |
| USB2_UPC_TA_P | Default | d | 0.517 | |
| USB2_UPC_TB_N | Default | d | 0.511 | |
| USB2_UPC_TB_P | Default | d | 0.515 | |
| USB2_UPC_XA_N | Default | d | 0.520 | |
| USB2_UPC_XA_P | Default | d | 0.520 | |
| USB2_UPC_XB_P | Default | d | 0.44 | |
| USB3_EXTA_D2R_N | Default | d | 0.360 | |
| USB3_EXTA_D2R_P | Default | d | 0.358 | |
| USB3_EXTA_R2D_C_N | Default | d | 0.341 | |
| USB3_EXTA_R2D_C_P | Default | d | 0.343 | |
| USB3_EXTA_R2D_N | Default | d | 0.738 | |
| USB3_EXTA_R2D_P | Default | d | 0.739 | |
| USB3_TEST2_D2R_N | Default | d | 0.363 | |
| USB3_TEST2_D2R_P | Default | d | 0.361 | |
| USB3_TEST2_R2D_N | Default | d | 0.340 | |
| USB3_TEST2_R2D_P | Default | d | 0.340 | |
| USB3_TEST_D2R_N | Default | d | 0.361 | |
| USB3_TEST_D2R_P | Default | d | 0.361 | |
| USB3_TEST_R2D_N | Default | d | 0.342 | |
| USB3_TEST_R2D_P | Default | d | 0.343 | |
| USBC_HPD_DET | Default | d | 0.604 | |
| USBC_TA_CC1 | Default | d | 0.611 | |
| USBC_TA_CC1_CONN | Default | d | 0.812 | |
| USBC_TA_CC2 | Default | d | 0.615 | |
| USBC_TA_CC2_CONN | Default | d | 0.779 | |
| USBC_TA_D2R_CR_N<1> | Default | d | OL | |
| USBC_TA_D2R_CR_N<2> | Default | d | OL | |
| USBC_TA_D2R_CR_P<1> | Default | d | OL | |
| USBC_TA_D2R_CR_P<2> | Default | d | OL | |
| USBC_TA_R2D_N<1> | Default | d | OL | |
| USBC_TA_R2D_N<2> | Default | d | OL | |
| USBC_TA_R2D_P<1> | Default | d | OL | |
| USBC_TA_R2D_P<2> | Default | d | OL | |
| USBC_TA_SBU1 | Default | d | 0.876 | |
| USBC_TA_SBU2 | Default | d | OL | |
| USBC_TA_USB_BOT_N | Default | d | OL | |
| USBC_TA_USB_BOT_P | Default | d | OL | |
| USBC_TA_USB_TOP_N | Default | d | 0.973 | |
| USBC_TA_USB_TOP_P | Default | d | 0.910 | |
| USBC_TB_CC1 | Default | d | 0.612 | |
| USBC_TB_CC1_CONN | Default | d | 0.734 | |
| USBC_TB_CC2 | Default | d | 0.616 | |
| USBC_TB_CC2_CONN | Default | d | 0.821 | |
| USBC_TB_D2R_CR_N<1> | Default | d | OL | |
| USBC_TB_D2R_CR_N<2> | Default | d | OL | |
| USBC_TB_D2R_CR_P<1> | Default | d | OL | |
| USBC_TB_D2R_CR_P<2> | Default | d | OL | |
| USBC_TB_R2D_N<1> | Default | d | OL | |
| USBC_TB_R2D_N<2> | Default | d | OL | |
| USBC_TB_R2D_P<1> | Default | d | OL | |
| USBC_TB_SBU1 | Default | d | 0.887 | |
| USBC_TB_SBU2 | Default | d | 0.847 | |
| USBC_TB_USB_BOT_N | Default | d | OL | |
| USBC_TB_USB_BOT_P | Default | d | OL | |
| USBC_TB_USB_TOP_N | Default | d | 0.961 | |
| USBC_TB_USB_TOP_P | Default | d | 0.959 | |
| USBC_T_RESET_L | Default | d | 0.765 | |
| USBC_XA_CC1 | Default | d | 0.614 | |
| USBC_XA_CC1_CONN | Default | d | 0.943 | |
| USBC_XA_CC2 | Default | d | 0.617 | |
| USBC_XA_CC2_CONN | Default | d | 0.946 | |
| USBC_XA_D2R_CR_N<1> | Default | d | OL | |
| USBC_XA_D2R_CR_N<2> | Default | d | OL | |
| USBC_XA_D2R_CR_P<1> | Default | d | OL | |
| USBC_XA_D2R_CR_P<2> | Default | d | OL | |
| USBC_XA_R2D_N<1> | Default | d | OL | |
| USBC_XA_R2D_N<2> | Default | d | OL | |
| USBC_XA_R2D_P<1> | Default | d | OL | |
| USBC_XA_R2D_P<2> | Default | d | OL | |
| USBC_XA_SBU1 | Default | d | 0.856 | |
| USBC_XA_SBU2 | Default | d | 0.856 | |
| USBC_XA_USB_DBG_BOT_N | Default | d | 0.316 | |
| USBC_XA_USB_DBG_BOT_N | Default | t | Data+ 2.0 480Mps | |
| USBC_XA_USB_DBG_BOT_P | Default | d | 0.316 | |
| USBC_XA_USB_DBG_TOP_N | Default | d | 0.315 | |
| USBC_XA_USB_DBG_TOP_P | Default | d | 0.316 | |
| USBC_XB_CC1 | Default | d | 0.59 | |
| USBC_XB_CC1_CONN | Default | d | 0.971 | |
| USBC_XB_CC2 | Default | d | 0.59 | |
| USBC_XB_CC2_CONN | Default | d | 0.933 | |
| USBC_XB_D2R_CR_N<1> | Default | d | OL | |
| USBC_XB_D2R_CR_N<2> | Default | d | OL | |
| USBC_XB_D2R_CR_P<1> | Default | d | OL | |
| USBC_XB_D2R_CR_P<2> | Default | d | OL | |
| USBC_XB_R2D_N<1> | Default | d | OL | |
| USBC_XB_R2D_N<2> | Default | d | OL | |
| USBC_XB_R2D_P<1> | Default | d | OL | |
| USBC_XB_R2D_P<2> | Default | d | OL | |
| USBC_XB_SBU1 | Default | d | 0.859 | |
| USBC_XB_SBU2 | Default | d | 0.861 | |
| USBC_XB_USB_BOT_N | Default | d | OL | |
| USBC_XB_USB_BOT_P | Default | d | OL | |
| USBC_XB_USB_TOP_N | Default | d | 0.975 | |
| USBC_XB_USB_TOP_P | Default | d | 0.978 | |
| USBC_X_RESET_L | Default | d | 0.770 | |
| USB_DBG_PCH_XA_F_N | Default | d | 0.520 | |
| USB_DBG_PCH_XA_F_P | Default | d | 0.520 | |
| USB_SOC_N | Default | d | 0.727 | |
| USB_SOC_P | Default | d | 0.727 | |
| USB_SOC_TYPEC_N | Default | d | 0.722 | |
| USB_SOC_TYPEC_P | Default | d | 0.722 | |
| USB_UPC_TA_F_N | Default | d | 0.522 | |
| USB_UPC_TA_F_P | Default | d | 0.517 | |
| USB_UPC_TB_F_N | Default | d | 0.511 | |
| USB_UPC_TB_F_P | Default | d | 0.515 | |
| USB_UPC_XA_N | Default | d | 0.755 | |
| USB_UPC_XA_P | Default | d | 0.755 | |
| USB_UPC_XB_F_P | Default | d | 0.44 | |
| UVP_DIS_L | Default | d | 0.560 | |
| VDDCIS0_CS_N | Default | d | 0.033 | |
| VDDCIS0_CS_N | Default | r | 31.900R | |
| VDDCIS0_CS_P | Default | d | 0.032 | |
| VDDCIS0_CS_P | Default | r | 31.600R | |
| VR0V9_IND_TBT_T | Default | d | 0.314 | |
| VR0V9_IND_TBT_T | Default | r | 330.000R | |
| VR0V9_IND_TBT_T | Default | v | 0,900 | |
| VR0V9_IND_TBT_X | Default | d | 0.314 | |
| VR0V9_IND_TBT_X | Default | v | 0,900 | |
| VRVDDCI_R | Default | d | 0.035 | |
| VRVDDCI_R | Default | r | 34.400R | |
| VRVDDCI_R | Default | v | 0,900 | |
| VR_PHASE_GPU_VDDCI | Default | d | 0.035 | |
| VR_PHASE_GPU_VDDCI | Default | r | 34.400R | |
| VR_PHASE_GPU_VDDCI | Default | v | 0,900 | |
| WIFI_SROM_ORG | Default | d | 0.707 | |
| WLAN_AUDIO_SYNC | Default | d | 0.480 | |
| WLAN_AUDIO_SYNC_LS3V3 | Default | d | 0.638 | |
| WLAN_CONTEXT_A | Default | d | 0.490 | |
| WLAN_CONTEXT_B | Default | d | 0.491 | |
| WLAN_HOST_WAKE | Default | d | 0.489 | |
| WLAN_JTAG_SEL | Default | d | 0.744 | |
| WLAN_JTAG_TCK | Default | d | 0.490 | |
| WLAN_JTAG_TDI | Default | d | 0.482 | |
| WLAN_JTAG_TDO | Default | d | 0.478 | |
| WLAN_JTAG_TMS | Default | d | 0.490 | |
| WLAN_JTAG_TRST_L | Default | d | 0.756 | |
| WLAN_PWR_EN | Default | d | 0.490 | |
| WLAN_SROM_STRAP | Default | d | 0.744 | |
| WL_GPIO_13 | Default | d | 0.655 | |
| XDP_BPM_L<0> | Default | d | 0.283 | |
| XDP_BPM_L<1> | Default | d | 0.281 | |
| XDP_BPM_L<2> | Default | d | 0.281 | |
| XDP_BPM_L<3> | Default | d | 0.283 | |
| XDP_CPU_PRDY_L | Default | d | 0.254 | |
| XDP_CPU_PREQ_L | Default | d | 0.273 | |
| XDP_CPU_PWRBTN_L | Default | d | 0.778 | |
| XDP_CPU_TCK | Default | d | 0.052 | |
| XDP_CPU_TCK | Default | r | 50.600R | |
| XDP_CPU_TDI | Default | d | 0.235 | |
| XDP_CPU_TDO | Default | d | 0.220 | |
| XDP_CPU_TMS | Default | d | 0.235 | |
| XDP_CPU_TRST_L | Default | d | 0.282 | |
| XDP_DBRESET_L | Default | d | 0.814 | |
| XDP_JTAG_ISP_TCK | Default | d | 0.564 | |
| XDP_JTAG_ISP_TDI | Default | d | 0.563 | |
| XDP_JTAG_ISP_TDO | Default | d | 0.566 | |
| XDP_PCH_JTAGX | Default | d | 0.053 | |
| XDP_PCH_JTAGX | Default | r | 52.600R | |
| XDP_PCH_OBSDATA_A0 | Default | d | 0.825 | |
| XDP_PCH_OBSDATA_A1 | Default | d | 0.824 | |
| XDP_PCH_OBSDATA_A2 | Default | d | 0.823 | |
| XDP_PCH_OBSDATA_A3 | Default | d | 0.825 | |
| XDP_PCH_OBSDATA_B0 | Default | d | 0.825 | |
| XDP_PCH_OBSDATA_B1 | Default | d | 0.825 | |
| XDP_PCH_OBSDATA_B2 | Default | d | 0.824 | |
| XDP_PCH_OBSDATA_B3 | Default | d | 0.824 | |
| XDP_PCH_OBSDATA_D0 | Default | d | 0.824 | |
| XDP_PCH_OBSDATA_D1 | Default | d | 0.824 | |
| XDP_PCH_OBSFN_C0 | Default | d | 0.824 | |
| XDP_PCH_TCK | Default | d | 0.339 | |
| XDP_PCH_TDI | Default | d | 0.236 | |
| XDP_PCH_TDO | Default | d | 0.224 | |
| XDP_PCH_TMS | Default | d | 0.236 | |
| XDP_PCH_TRST_L | Default | d | 0.281 | |
| XDP_PM_RSMRST_L | Default | d | 1.524 | |
| XDP_PRESENT_CPU | Default | d | 1.771 | |
| XDP_PRESENT_L | Default | d | 0.476 | |
| XDP_USB_EXTA_OC_L | Default | d | 0.762 | |
| XDP_USB_EXTB_OC_L | Default | d | 0.762 | |
| XDP_USB_EXTC_OC_L | Default | d | 0.762 | |
| XDP_USB_EXTD_OC_L | Default | d | 0.763 | |