Netname | Condition | Type | Value | Comment |
1V8_SWCH_EN | Default | d | 0.760 | |
1V8_SWCH_SLEW | Default | d | OL | |
50_ANT_C0 | Default | d | OL | |
50_ANT_C1 | Default | d | OL | |
ACT_GND | Default | d | 0.000 | |
ADC2_REFCOMP | Default | d | OL | |
ALL_SYS_PWRGD | Default | d | 0.709 | |
ALL_SYS_PWRGD_R | Default | d | 0.488 | |
AON_SLEEP1_RESET_L | Default | d | 0.420 | |
AUD_CONN_HP_LEFT | Default | d | 0.718 | |
AUD_CONN_HP_RIGHT | Default | d | 0.718 | |
AUD_CONN_HP_SENSE_L | Default | d | 1.362 | |
AUD_CONN_HP_SENSE_R | Default | d | 1.359 | |
AUD_CONN_RING2 | Default | d | 0.002 | |
AUD_CONN_RING2 | Default | r | 1.700R | |
AUD_CONN_RING2_XW | Default | d | 0.632 | |
AUD_CONN_RING_SENSE | Default | d | 0.644 | |
AUD_CONN_SLEEVE | Default | d | 0.002 | |
AUD_CONN_SLEEVE | Default | r | 1.800R | |
AUD_CONN_SLEEVE_XW | Default | d | 0.632 | |
AUD_CONN_TIP_SENSE | Default | d | 1.475 | |
AUD_DMIC0_DATA_CONN | Default | d | 0.550 | |
AUD_DMIC1_DATA_CONN | Default | d | 0.549 | |
AUD_HP_PORT_CH_GND | Default | d | 0.002 | |
AUD_HP_PORT_L | Default | d | 0.718 | |
AUD_HP_PORT_R | Default | d | 0.718 | |
AUD_HP_PORT_US_GND | Default | d | 0.002 | |
AUD_HP_SENSE_L | Default | d | 1.362 | |
AUD_HP_SENSE_R | Default | d | 1.359 | |
AUD_HS_MIC_N | Default | d | 0.632 | |
AUD_HS_MIC_P | Default | d | 0.632 | |
AUD_RING_SENSE | Default | d | 0.644 | |
AUD_TIP_SENSE | Default | d | 1.475 | |
BKLT_EN_R | Default | d | 0.559 | |
BKLT_ISET_KEYB | Default | d | 0.680 | |
BKLT_KEYB1 | Default | d | 0.662 | |
BKLT_KEYB2 | Default | d | 0.657 | |
BKLT_PWM_KEYB_3V3 | Default | d | 0.531 | |
BKLT_SCL | Default | d | 0.555 | |
BKLT_SD | Default | d | 0.603 | |
BKLT_SDA | Default | d | 0.555 | |
BKLT_SENSE_OUT | Default | d | 0.733 | |
BOARD_REV0 | Default | d | 0.473 | |
BOARD_REV1 | Default | d | 0.477 | |
BOARD_REV2 | Default | d | 0.474 | |
BOOT_CONFIG0 | Default | d | 0.478 | |
BOOT_CONFIG1 | Default | d | 0.476 | |
BOOT_CONFIG2 | Default | d | 0.477 | |
BT_AUDIO_SYNC | Default | d | 0.632 | |
BT_GPIO_4 | Default | d | 0.562 | |
BT_SFLASH_CS_L | Default | d | 0.696 | |
BT_SFLASH_HOLD_L | Default | d | 0.466 | |
BT_SFLASH_WP_L | Default | d | 0.463 | |
BT_SPI2_CLK | Default | d | 0.471 | |
BT_SPI2_CSN | Default | d | 0.635 | |
BT_SPI2_MISO | Default | d | 0.459 | |
BT_SPI2_MOSI | Default | d | 0.460 | |
CAPSLOCK_LED_EN | Default | d | 0.528 | |
CATERR_LED_A | Default | d | OL | |
CATERR_LED_G | Default | d | OL | |
CATERR_LED_K | Default | d | OL | |
CHGR_AMON | Default | d | 0.635 | |
CHGR_AUX_DET | Default | d | 0.641 | |
CHGR_BGATE | Default | d | 0.635 | |
CHGR_BMON | Default | d | 0.635 | |
CHGR_BOOT1 | Default | d | 0.589 | |
CHGR_BOOT1_RC | Default | d | 0.595 | |
CHGR_BOOT2 | Default | d | 0.585 | |
CHGR_BOOT2_RC | Default | d | 0.585 | |
CHGR_COMP | Default | d | 0.639 | |
CHGR_CSI_N | Default | d | 0.557 | |
CHGR_CSI_P | Default | d | 0.558 | |
CHGR_CSI_R_N | Default | d | 0.562 | |
CHGR_CSI_R_P | Default | d | 0.562 | |
CHGR_CSO_N | Default | d | 0.339 | |
CHGR_CSO_P | Default | d | 0.340 | |
CHGR_CSO_R_N | Default | d | 0.336 | |
CHGR_CSO_R_N | Default | v | 12.650 | |
CHGR_CSO_R_P | Default | d | 0.336 | |
CHGR_CSO_R_P | Default | v | 12.650 | |
CHGR_EN_MVR | Default | d | 0.615 | |
CHGR_EN_MVR_R | Default | d | 0.613 | |
CHGR_GATE_Q1 | Default | d | 0.855 | |
CHGR_GATE_Q2 | Default | d | 0.480 | |
CHGR_GATE_Q3 | Default | d | 0.472 | |
CHGR_GATE_Q4 | Default | d | 0.852 | |
CHGR_LX1 | Default | d | 0.377 | |
CHGR_LX1 | Default | r | 0.135R | |
CHGR_LX2 | Default | d | 0.377 | |
CHGR_LX2 | Default | r | 0.135R | |
CHGR_RST_IN | Default | d | 0.632 | |
CHGR_RST_IN_R | Default | d | 0.694 | |
CHGR_VBAT | Default | d | 0.635 | |
CHGR_VDDA | Default | d | 0.468 | |
CHGR_VDDP | Default | d | 0.466 | |
CODEC_INT_L | Default | d | 0.478 | |
CODEC_RESET_L | Default | d | 0.475 | |
CODEC_WAKE_L | Default | d | 0.471 | |
COMP_A_CPUGT | Default | d | 0.634 | |
COMP_A_CPUGT_L | Default | d | OL | |
COMP_B_CPUCORE | Default | d | 0.635 | |
COMP_B_CPUCORE_L | Default | d | OL | |
COMP_C_CPUSA | Default | d | 0.635 | |
COMP_C_CPUSA_L | Default | d | OL | |
CORE_ISUMN_R | Default | d | 1.015 | |
CPUCORE1_DRVH | Default | d | 0.636 | |
CPUCORE2_DRVH | Default | d | 0.637 | |
CPUCORE_BOOT1 | Default | d | 0.605 | |
CPUCORE_BOOT2 | Default | d | 0.604 | |
CPUCORE_BP1 | Default | d | 0.605 | |
CPUCORE_BP2 | Default | d | 0.604 | |
CPUCORE_FCCM | Default | d | 0.612 | |
CPUCORE_ISEN1 | Default | d | 0.635 | |
CPUCORE_ISEN2 | Default | d | 0.635 | |
CPUCORE_ISNS1_N | Default | d | 0.006 | |
CPUCORE_ISNS1_N | Default | r | 5.200R | |
CPUCORE_ISNS1_P | Default | d | 0.006 | |
CPUCORE_ISNS1_P | Default | r | 5.200R | |
CPUCORE_ISNS2_N | Default | d | 0.006 | |
CPUCORE_ISNS2_N | Default | r | 5.200R | |
CPUCORE_ISNS2_P | Default | d | 0.006 | |
CPUCORE_ISNS2_P | Default | r | 5.200R | |
CPUCORE_ISUMN | Default | d | 0.006 | |
CPUCORE_ISUMN | Default | r | 6.200R | |
CPUCORE_ISUMN_R | Default | d | 0.486 | |
CPUCORE_ISUMP | Default | d | 0.487 | |
CPUCORE_PHASE1 | Default | d | 0.005 | |
CPUCORE_PHASE1 | Default | r | 5.300R | |
CPUCORE_PHASE2 | Default | r | 6.800R | |
CPUCORE_PSYS | Default | d | 0.633 | |
CPUCORE_PWM1 | Default | d | 0.617 | |
CPUCORE_PWM2 | Default | d | 0.618 | |
CPUCORE_SW1 | Default | d | 0.006 | |
CPUCORE_SW1 | Default | r | 5.200R | |
CPUCORE_SW1_SNUB | Default | d | OL | |
CPUCORE_SW2 | Default | d | 0.006 | |
CPUCORE_SW2 | Default | r | 5.400R | |
CPUCORE_SW2_SNUB | Default | d | OL | |
CPUDDR_IOUT | Default | d | OL | |
CPUGT1_DRVH | Default | d | 0.634 | |
CPUGT1_GL0 | Default | d | 0.462 | |
CPUGTVSENSE_IN | Default | d | 0.005 | |
CPUGTVSENSE_IN | Default | r | 5.300R | |
CPUGT_BOOT1 | Default | d | 0.605 | |
CPUGT_BOOT2 | Default | d | 0.607 | |
CPUGT_BP1 | Default | d | 0.605 | |
CPUGT_BP2 | Default | d | 0.607 | |
CPUGT_FCCM | Default | d | 0.611 | |
CPUGT_ISEN1 | Default | d | 0.635 | |
CPUGT_ISEN2 | Default | d | 0.635 | |
CPUGT_ISNS1_N | Default | d | 0.006 | |
CPUGT_ISNS1_N | Default | r | 5.100R | |
CPUGT_ISNS1_P | Default | d | 0.006 | |
CPUGT_ISNS1_P | Default | r | 5.100R | |
CPUGT_ISNS2_N | Default | d | 0.006 | |
CPUGT_ISNS2_N | Default | r | 5.100R | |
CPUGT_ISNS2_P | Default | d | 0.006 | |
CPUGT_ISNS2_P | Default | r | 5.100R | |
CPUGT_ISUMN | Default | d | 0.006 | |
CPUGT_ISUMN | Default | r | 5.900R | |
CPUGT_ISUMN_R | Default | d | 0.486 | |
CPUGT_ISUMP | Default | d | 0.486 | |
CPUGT_ISUM_IOUT | Default | d | OL | |
CPUGT_PHASE1 | Default | d | 0.006 | |
CPUGT_PHASE1 | Default | r | 6.600R | |
CPUGT_PHASE2 | Default | d | 0.006 | |
CPUGT_PHASE2 | Default | r | 6.600R | |
CPUGT_PWM1 | Default | d | 0.619 | |
CPUGT_PWM2 | Default | d | 0.619 | |
CPUGT_SW1 | Default | d | 0.006 | |
CPUGT_SW1_SNUB | Default | d | OL | |
CPUGT_SW2 | Default | d | 0.006 | |
CPUGT_SW2 | Default | r | 5.100R | |
CPUGT_SW2_SNUB | Default | d | OL | |
CPUHI_IOUT | Default | d | 0.711 | |
CPUREGMISCP5V_IOUT | Default | d | OL | |
CPUSAVSENSE_IN | Default | d | 0.020 | |
CPUSAVSENSE_IN | Default | r | 19.400R | |
CPUSA_BOOTSA | Default | d | 0.603 | |
CPUSA_BPSA | Default | d | 0.603 | |
CPUSA_DRVH | Default | d | 0.001 | |
CPUSA_DRVH | Default | r | 1.300R | |
CPUSA_FCCM | Default | d | 0.619 | |
CPUSA_GL0 | Default | d | 0.490 | |
CPUSA_ISNS_N | Default | d | 0.031 | |
CPUSA_ISNS_N | Default | r | 30.500R | |
CPUSA_ISNS_P | Default | d | 0.031 | |
CPUSA_ISNS_P | Default | r | 30.600R | |
CPUSA_ISNS_R_N | Default | d | 0.023 | |
CPUSA_ISNS_R_N | Default | r | 23.000R | |
CPUSA_ISNS_R_P | Default | d | 0.023 | |
CPUSA_ISNS_R_P | Default | r | 23.000R | |
CPUSA_ISUMN | Default | d | 0.022 | |
CPUSA_ISUMN | Default | r | 21.700R | |
CPUSA_ISUMN_R | Default | d | 0.493 | |
CPUSA_ISUMP | Default | d | 0.584 | |
CPUSA_PHASESA | Default | d | 0.020 | |
CPUSA_PHASESA | Default | r | 20.100R | |
CPUSA_PWM | Default | d | 0.615 | |
CPUSA_SW_SNUB | Default | d | OL | |
CPUVCCIO_IOUT | Default | d | OL | |
CPUVR_ISUM_IOUT | Default | d | OL | |
CPUVR_SWSA | Default | d | 0.023 | |
CPUVR_SWSA | Default | r | 23.000R | |
CPUVR_VIDALERT_L_R | Default | d | 0.291 | |
CPUVR_VIDSCLK_R | Default | d | 0.302 | |
CPUVR_VIDSOUT_R | Default | d | 0.255 | |
CPUVSENSE_IN | Default | d | 0.007 | |
CPUVSENSE_IN | Default | r | 5.900R | |
CPU_C10_GATE_L | Default | d | 0.482 | |
CPU_CATERR_L | Default | d | 0.241 | |
CPU_CFG<10> | Default | d | 0.290 | |
CPU_CFG<16> | Default | d | 0.292 | |
CPU_CFG<3> | Default | d | 0.290 | |
CPU_CFG<4> | Default | d | 0.275 | |
CPU_CFG<5> | Default | d | 0.291 | |
CPU_CFG<7> | Default | d | 0.290 | |
CPU_CFG_RCOMP | Default | d | 0.053 | |
CPU_CFG_RCOMP | Default | r | 50.400R | |
CPU_DDDR0_ALERT_L | Default | d | 0.001 | |
CPU_DDDR0_ALERT_L | Default | r | 0.600R | |
CPU_DDDR1_ALERT_L | Default | d | 0.001 | |
CPU_DDDR1_ALERT_L | Default | r | 0.600R | |
CPU_DDR_RCOMP<0> | Default | d | 0.197 | |
CPU_DDR_RCOMP<1> | Default | d | 0.085 | |
CPU_DDR_RCOMP<1> | Default | r | 81.600R | |
CPU_DDR_RCOMP<2> | Default | d | 0.164 | |
CPU_DIMMA_VREFDQ | Default | d | 0.390 | |
CPU_DIMMB_VREFDQ | Default | d | 0.387 | |
CPU_DIMM_VREFCA | Default | d | 0.382 | |
CPU_DRAM_RESET_L | Default | d | 0.600 | |
CPU_INPUT3VSEL | Default | d | 0.827 | |
CPU_IST_TRIG | Default | d | 0.340 | |
CPU_PECI | Default | d | 0.286 | |
CPU_PECI_R | Default | d | 0.297 | |
CPU_PROCHOT_L | Default | d | 0.456 | |
CPU_PROCHOT_OUT_L | Default | d | 0.481 | |
CPU_PROCHOT_R_L | Default | d | 0.290 | |
CPU_SMC_THRMTRIP_L | Default | d | 0.468 | |
CPU_VCCEOPIOSENSE_N | Default | d | 0.004 | |
CPU_VCCEOPIOSENSE_N | Default | r | 1.200R | |
CPU_VCCEOPIOSENSE_P | Default | d | 0.048 | |
CPU_VCCEOPIOSENSE_P | Default | r | 44.200R | |
CPU_VCCEOPIOSENSE_R | Default | d | 0.058 | |
CPU_VCCEOPIOSENSE_R | Default | r | 56.700R | |
CPU_VCCEOPIOSENSE_XW | Default | d | 0.004 | |
CPU_VCCEOPIOSENSE_XW | Default | r | 2.600R | |
CPU_VCCGTSENSE_N | Default | d | 0.002 | |
CPU_VCCGTSENSE_N | Default | r | 1.500R | |
CPU_VCCGTSENSE_P | Default | d | 0.007 | |
CPU_VCCGTSENSE_P | Default | r | 5.800R | |
CPU_VCCIOSENSE_N | Default | d | 0.000 | |
CPU_VCCIOSENSE_N | Default | r | 1.600R | |
CPU_VCCIOSENSE_P | Default | d | 0.117 | |
CPU_VCCIOSENSE_R | Default | d | 0.192 | |
CPU_VCCIOSENSE_XW | Default | d | 0.002 | |
CPU_VCCIOSENSE_XW | Default | r | 1.600R | |
CPU_VCCSASENSE_N | Default | d | 0.005 | |
CPU_VCCSASENSE_N | Default | r | 2.900R | |
CPU_VCCSASENSE_P | Default | d | 0.025 | |
CPU_VCCSASENSE_P | Default | r | 22.800R | |
CPU_VCCSENSE_N | Default | d | 0.003 | |
CPU_VCCSENSE_N | Default | r | 1.100R | |
CPU_VCCSENSE_P | Default | d | 0.008 | |
CPU_VCCSENSE_P | Default | r | 6.100R | |
CPU_VCCST_PWRGD | Default | d | 0.515 | |
CPU_VCCST_PWRGD_R | Default | d | 0.537 | |
CPU_VIDALERT_L | Default | d | 0.286 | |
CPU_VIDALERT_R_L | Default | d | 0.240 | |
CPU_VIDSCLK | Default | d | 0.239 | |
CPU_VIDSCLK_R | Default | d | 0.240 | |
CPU_VIDSOUT | Default | d | 0.239 | |
CPU_VIDSOUT_R | Default | d | 0.241 | |
CPU_VR_EN_R | Default | d | 0.486 | |
CPU_VR_PROCHOT_L | Default | d | 0.524 | |
CPU_VR_READY | Default | d | 0.592 | |
CPU_ZVM_L | Default | d | 0.379 | |
CSI2_COMP | Default | d | 0.101 | |
DBGLED_S0 | Default | d | OL | |
DBGLED_S0I3 | Default | d | OL | |
DBGLED_S0I3_D | Default | d | OL | |
DBGLED_S0_D | Default | d | OL | |
DBGLED_S3 | Default | d | OL | |
DBGLED_S3_D | Default | d | OL | |
DBGLED_S4 | Default | d | OL | |
DBGLED_S4_D | Default | d | OL | |
DDRREG_VTTSNS | Default | d | 0.137 | |
DEBUG_JTAG_SOC_TDI | Default | d | 0.472 | |
DEBUG_JTAG_SOC_TDO | Default | d | 0.473 | |
DFR3V3_IOUT | Default | d | OL | |
DFR_DISP_INT | Default | d | 0.476 | |
DFR_DISP_RESET_L | Default | d | 0.478 | |
DFR_DISP_TE | Default | d | 0.479 | |
DFR_DISP_VSYNC | Default | d | OL | |
DFR_PWR_EN | Default | d | 0.475 | |
DFR_PWR_EN_R | Default | d | 0.557 | |
DFR_TOUCH_CLK32K_RESET_L | Default | d | 0.478 | |
DFR_TOUCH_INT_L | Default | d | 0.472 | |
DFR_TOUCH_LID_OPEN_L | Default | d | OL | |
DFR_TOUCH_RESET_L | Default | d | 0.475 | |
DFUMUX_SEL | Default | d | OL | |
DP_INT_HPD | Default | d | 0.530 | |
DP_INT_HPD_L | Default | d | 0.468 | |
DP_INT_HPD_MASK | Default | d | 0.456 | |
DP_XA_HPD | Default | d | 0.586 | |
DP_XB_HPD | Default | d | 0.590 | |
EADC2_AD0 | Default | d | OL | |
EADC2_KBBLT_ISENSE | Default | d | OL | |
EADC2_LCDBKLT_ISENSE | Default | d | OL | |
EADC2_MESA_ISENSE | Default | d | OL | |
EADC2_P3V3_DFR_ISENSE | Default | d | OL | |
EADC2_P3V3_KBD_ISENSE | Default | d | OL | |
EADC2_P3V3_TPAD_ISENSE | Default | d | OL | |
EADC2_P5V_LCD_ISENSE | Default | d | OL | |
EADC2_P5V_TPAD_ISENSE | Default | d | OL | |
EDP_AUXCH_N | Default | d | 0.245 | |
EDP_AUXCH_P | Default | d | 0.247 | |
EDP_BKLT_EN | Default | d | 0.562 | |
EDP_BKLT_PWM | Default | d | 0.818 | |
EDP_COMP | Default | d | 0.139 | |
EDP_PANEL_PWR_BUF_EN | Default | d | 0.716 | |
EDP_PANEL_PWR_DLY_EN | Default | d | 0.708 | |
EDP_PANEL_PWR_EN | Default | d | 0.568 | |
EEPROM_WC_L | Default | d | 0.536 | |
EMMC_RCOMP | Default | d | 0.203 | |
ENET_CLKREQ_L | Default | d | 0.479 | |
ESPI_CLK60M | Default | d | 0.465 | |
ESPI_CLK60M_DBG | Default | d | 0.475 | |
ESPI_CLK60M_R | Default | d | 0.483 | |
ESPI_CS_L | Default | d | 0.462 | |
ESPI_CS_PCH_L | Default | d | 0.474 | |
ESPI_DBG_CS_L | Default | d | OL | |
ESPI_IO<0> | Default | d | 0.480 | |
ESPI_IO<1> | Default | d | 0.474 | |
ESPI_IO<2> | Default | d | 0.474 | |
ESPI_IO<3> | Default | d | 0.475 | |
ESPI_IO_DBG<0> | Default | d | OL | |
ESPI_IO_DBG<1> | Default | d | OL | |
ESPI_IO_DBG<2> | Default | d | OL | |
ESPI_IO_DBG<3> | Default | d | OL | |
ESPI_IO_PCH<0> | Default | d | 0.490 | |
ESPI_IO_PCH<1> | Default | d | 0.484 | |
ESPI_IO_PCH<2> | Default | d | 0.501 | |
ESPI_IO_PCH<3> | Default | d | 0.488 | |
ESPI_IO_R<0> | Default | d | 0.462 | |
ESPI_IO_R<1> | Default | d | 0.462 | |
ESPI_IO_R<2> | Default | d | 0.462 | |
ESPI_IO_R<3> | Default | d | 0.462 | |
ESPI_RESET_L | Default | d | 0.460 | |
FAN_RT_PWM | Default | d | 0.725 | |
FAN_RT_TACH | Default | d | OL | |
FB_A_CPUGT | Default | d | 0.613 | |
FB_A_GT_R | Default | d | 1.616 | |
FB_A_GT_RC | Default | d | 1.331 | |
FB_B_CORE_R | Default | d | 1.621 | |
FB_B_CORE_RC | Default | d | 1.338 | |
FB_B_CPUCORE | Default | d | 0.618 | |
FB_CORE_R | Default | d | 0.008 | |
FB_CORE_R | Default | r | 6.100R | |
FB_C_CPUSA | Default | d | 0.615 | |
FB_C_SA_R | Default | d | OL | |
FB_C_SA_RC | Default | d | OL | |
FB_GT_R | Default | d | 0.007 | |
FB_GT_R | Default | r | 6.000R | |
FB_SA_R | Default | d | 0.024 | |
GT_ISUMN_R | Default | d | OL | |
HS_3V3RTC_IOUT | Default | d | OL | |
HS_OTHER3V3_IOUT | Default | d | OL | |
HS_OTHER5V_IOUT | Default | d | OL | |
HW_ID1 | Default | d | 0.552 | |
I2C_ALS_SCL | Default | d | 0.468 | |
I2C_ALS_SCL_R | Default | d | 0.469 | |
I2C_ALS_SDA | Default | d | 0.468 | |
I2C_ALS_SDA_R | Default | d | 0.469 | |
I2C_BKLT_SCL | Default | d | 0.557 | |
I2C_BKLT_SDA | Default | d | 0.557 | |
I2C_CODEC_SCL | Default | d | 0.475 | |
I2C_CODEC_SDA | Default | d | 0.475 | |
I2C_DFR_SCL | Default | d | 0.474 | |
I2C_DFR_SCL_R | Default | d | 0.488 | |
I2C_DFR_SDA | Default | d | 0.474 | |
I2C_DFR_SDA_R | Default | d | 0.488 | |
I2C_DISP_3V3_SCL | Default | d | 0.503 | |
I2C_DISP_3V3_SDA | Default | d | 0.502 | |
I2C_DISP_LS_EN | Default | d | 0.505 | |
I2C_DISP_SCL | Default | d | 0.454 | |
I2C_DISP_SDA | Default | d | 0.452 | |
I2C_FTCAM_DSBL_SCL | Default | d | 0.497 | |
I2C_FTCAM_DSBL_SDA | Default | d | 0.497 | |
I2C_FTCAM_ISOL_SCL | Default | d | 0.498 | |
I2C_FTCAM_ISOL_SDA | Default | d | 0.498 | |
I2C_FTCAM_SCL | Default | d | 0.445 | |
I2C_FTCAM_SCL_R | Default | d | 0.443 | |
I2C_FTCAM_SDA | Default | d | 0.443 | |
I2C_FTCAM_SDA_R | Default | d | 0.443 | |
I2C_KBD_SCL | Default | d | 0.711 | |
I2C_KBD_SDA | Default | d | 0.496 | |
I2C_PWR_SCL | Default | d | 0.469 | |
I2C_PWR_SCL_R1 | Default | d | 0.470 | |
I2C_PWR_SCL_R2 | Default | d | 0.470 | |
I2C_PWR_SDA | Default | d | 0.467 | |
I2C_PWR_SDA_R1 | Default | d | 0.470 | |
I2C_PWR_SDA_R2 | Default | d | 0.469 | |
I2C_SENSE_5V_SCL | Default | d | OL | |
I2C_SENSE_5V_SCL_R2 | Default | d | OL | |
I2C_SENSE_5V_SDA | Default | d | OL | |
I2C_SENSE_5V_SDA_R2 | Default | d | OL | |
I2C_SENSE_SCL | Default | d | 0.466 | |
I2C_SENSE_SCL_R1 | Default | d | 0.488 | |
I2C_SENSE_SCL_R2 | Default | d | OL | |
I2C_SENSE_SDA | Default | d | 0.466 | |
I2C_SENSE_SDA_R1 | Default | d | 0.488 | |
I2C_SENSE_SDA_R2 | Default | d | OL | |
I2C_SEP_SCL | Default | d | 0.472 | |
I2C_SEP_SDA | Default | d | 0.470 | |
I2C_SNS0_S0_SCL | Default | d | 0.465 | |
I2C_SNS0_S0_SDA | Default | d | 0.465 | |
I2C_SPKRAMP_L_SCL | Default | d | 0.386 | |
I2C_SPKRAMP_L_SDA | Default | d | 0.386 | |
I2C_SPKRAMP_R_SCL | Default | d | 0.391 | |
I2C_SPKRAMP_R_SDA | Default | d | 0.391 | |
I2C_SSD_SCL | Default | d | 0.467 | |
I2C_SSD_SDA | Default | d | 0.467 | |
I2C_TBT_XA_INT_L | Default | d | 0.588 | |
I2C_TBT_XB_INT_L | Default | d | 0.586 | |
I2C_TBT_X_SCL | Default | d | 0.531 | |
I2C_TBT_X_SDA | Default | d | 0.531 | |
I2C_THMSNS_SCL | Default | d | 0.464 | |
I2C_THMSNS_SCL_R0 | Default | d | 0.464 | |
I2C_THMSNS_SCL_R1 | Default | d | 0.466 | |
I2C_THMSNS_SCL_R2 | Default | d | 0.465 | |
I2C_THMSNS_SDA | Default | d | 0.463 | |
I2C_THMSNS_SDA_R0 | Default | d | 0.463 | |
I2C_THMSNS_SDA_R1 | Default | d | 0.465 | |
I2C_THMSNS_SDA_R2 | Default | d | 0.464 | |
I2C_TPAD_3V3_SCL | Default | d | 0.950 | |
I2C_TPAD_3V3_SCL_R | Default | d | 0.919 | |
I2C_TPAD_3V3_SDA | Default | d | 0.942 | |
I2C_TPAD_3V3_SDA_R | Default | d | 0.912 | |
I2C_UPC_SCL | Default | d | 0.467 | |
I2C_UPC_SDA | Default | d | 0.466 | |
I2C_UPC_XA_DBG_CTL_SCL | Default | d | 0.599 | |
I2C_UPC_XA_DBG_CTL_SDA | Default | d | 0.587 | |
I2C_UPC_XB_DBG_CTL_SCL | Default | d | 0.589 | |
I2C_UPC_XB_DBG_CTL_SDA | Default | d | 0.588 | |
I2C_UPC_X_SCL2 | Default | d | 0.465 | |
I2C_UPC_X_SDA2 | Default | d | 0.465 | |
I2S_CODEC_BCLK | Default | d | 0.481 | |
I2S_CODEC_D2R | Default | d | 0.469 | |
I2S_CODEC_LRCLK_R | Default | d | 0.482 | |
I2S_CODEC_R2D | Default | d | 0.458 | |
I2S_SPKRAMP_L_BCLK | Default | d | 0.387 | |
I2S_SPKRAMP_L_D2R | Default | d | 0.376 | |
I2S_SPKRAMP_L_D2R_R1 | Default | d | 0.387 | |
I2S_SPKRAMP_L_D2R_R2 | Default | d | 0.387 | |
I2S_SPKRAMP_L_LRCLK_R | Default | d | 0.387 | |
I2S_SPKRAMP_L_R2D | Default | d | 0.389 | |
I2S_SPKRAMP_R_BCLK | Default | d | 0.386 | |
I2S_SPKRAMP_R_BCLK_R | Default | d | 0.378 | |
I2S_SPKRAMP_R_D2R | Default | d | 0.470 | |
I2S_SPKRAMP_R_D2R_R1 | Default | d | 0.388 | |
I2S_SPKRAMP_R_D2R_R2 | Default | d | 0.388 | |
I2S_SPKRAMP_R_LRCLK | Default | d | 0.406 | |
I2S_SPKRAMP_R_LRCLK_R | Default | d | 0.384 | |
I2S_SPKRAMP_R_R2D | Default | d | 0.386 | |
I2S_SPKRAMP_R_R2D_R | Default | d | 0.406 | |
IMON_A_CPUGT | Default | d | 0.635 | |
IMON_B_CPUCORE | Default | d | 0.635 | |
IMON_C_CPUSA | Default | d | 0.635 | |
IOXP1_INT_L | Default | d | 0.646 | |
IOXP1_RESET_L | Default | d | 0.748 | |
IOXP2_ADDR | Default | d | 0.723 | |
IOXP2_INT_L | Default | d | 0.654 | |
IOXP_I2C_SCL | Default | d | 0.690 | |
IOXP_I2C_SDA | Default | d | 0.469 | |
IPD_LID_OPEN | Default | d | 0.710 | |
IPD_LID_OPEN_R | Default | d | OL | |
ISNS_CALPE_IOUT | Default | d | OL | |
ISNS_CALPE_N | Default | d | OL | |
ISNS_CALPE_P | Default | d | OL | |
ISNS_CPUDDR_N | Default | d | 0.224 | |
ISNS_CPUDDR_P | Default | d | 0.224 | |
ISNS_CPUEDRAM_IOUT | Default | d | OL | |
ISNS_CPUEDRAM_N | Default | d | 0.054 | |
ISNS_CPUEDRAM_N | Default | r | 53.000R | |
ISNS_CPUEDRAM_P | Default | d | 0.054 | |
ISNS_CPUEDRAM_P | Default | r | 53.000R | |
ISNS_CPUGT_N | Default | d | OL | |
ISNS_CPUGT_P | Default | d | OL | |
ISNS_CPUGT_R_N | Default | d | OL | |
ISNS_CPUGT_R_P | Default | d | OL | |
ISNS_CPUSA_IOUT | Default | d | OL | |
ISNS_CPUVCCIO_N | Default | d | 0.129 | |
ISNS_CPUVCCIO_P | Default | d | 0.129 | |
ISNS_CPUVDDQ_N | Default | d | OL | |
ISNS_CPUVDDQ_P | Default | d | OL | |
ISNS_CPUVR_N | Default | d | OL | |
ISNS_CPUVR_P | Default | d | OL | |
ISNS_CPUVR_R_N | Default | d | OL | |
ISNS_CPUVR_R_P | Default | d | OL | |
ISNS_DDR_IOUT | Default | d | OL | |
ISNS_DFR3V3_N | Default | d | OL | |
ISNS_DFR3V3_P | Default | d | OL | |
ISNS_HS_3V3RTC_N | Default | d | OL | |
ISNS_HS_3V3RTC_P | Default | d | OL | |
ISNS_HS_CPU_N | Default | d | 0.336 | |
ISNS_HS_CPU_P | Default | d | 0.336 | |
ISNS_HS_OTHER3V3_N | Default | d | 0.336 | |
ISNS_HS_OTHER3V3_N | Default | v | 12.650 | |
ISNS_HS_OTHER3V3_P | Default | d | 0.336 | |
ISNS_HS_OTHER3V3_P | Default | v | 12.650 | |
ISNS_HS_OTHER5V_N | Default | d | 0.338 | |
ISNS_HS_OTHER5V_P | Default | d | 0.338 | |
ISNS_KBBLT_IOUT | Default | d | OL | |
ISNS_KBBLT_N | Default | d | OL | |
ISNS_KBBLT_P | Default | d | OL | |
ISNS_KBDP3V3_N | Default | d | OL | |
ISNS_KBDP3V3_P | Default | d | OL | |
ISNS_LCDBKLT_N | Default | d | 0.336 | |
ISNS_LCDBKLT_N | Default | v | 12.650 | |
ISNS_LCDBKLT_P | Default | d | 0.336 | |
ISNS_LCDBKLT_P | Default | v | 12.650 | |
ISNS_LCDPANEL_N | Default | d | OL | |
ISNS_LCDPANEL_P | Default | d | OL | |
ISNS_MESA_IOUT | Default | d | OL | |
ISNS_MESA_N | Default | d | OL | |
ISNS_MESA_P | Default | d | OL | |
ISNS_OCARINA_IOUT | Default | d | OL | |
ISNS_OCARINA_N | Default | d | OL | |
ISNS_OCARINA_P | Default | d | OL | |
ISNS_P1V8G3S_N | Default | d | OL | |
ISNS_P1V8G3S_P | Default | d | OL | |
ISNS_P1V8LPDDR_N | Default | d | OL | |
ISNS_P1V8LPDDR_P | Default | d | OL | |
ISNS_P5VCPUREGMISC_N | Default | d | OL | |
ISNS_P5VCPUREGMISC_P | Default | d | OL | |
ISNS_PP5V_LCD_N | Default | d | OL | |
ISNS_PP5V_LCD_P | Default | d | OL | |
ISNS_SPKRAMP_LEFT_N | Default | d | OL | |
ISNS_SPKRAMP_LEFT_P | Default | d | OL | |
ISNS_SPKRAMP_RIGHT_N | Default | d | OL | |
ISNS_SPKRAMP_RIGHT_P | Default | d | OL | |
ISNS_SSDNAND_N | Default | d | OL | |
ISNS_SSDNAND_P | Default | d | OL | |
ISNS_TBTX_N | Default | d | 0.000 | |
ISNS_TBTX_P | Default | d | OL | |
ISNS_TPADP3V3_N | Default | d | OL | |
ISNS_TPADP3V3_P | Default | d | OL | |
ISNS_TPADP5V_N | Default | d | OL | |
ISNS_TPADP5V_P | Default | d | OL | |
ISNS_WLANBTP1V8_N | Default | d | OL | |
ISNS_WLANBTP1V8_P | Default | d | OL | |
ISNS_WLANBTP3V3_N | Default | d | OL | |
ISNS_WLANBTP3V3_P | Default | d | OL | |
ISNS_WLANBTP3V3_R_N | Default | d | OL | |
ISNS_WLANBTP3V3_R_P | Default | d | OL | |
ISNS_WLAN_OP | Default | d | OL | |
ITP_PMODE | Default | d | 0.381 | |
JTAG_ISP_TCK | Default | d | 0.586 | |
JTAG_ISP_TDI | Default | d | 0.583 | |
JTAG_ISP_TDO | Default | d | 0.586 | |
JTAG_TBT_T_TMS | Default | d | 0.802 | |
JTAG_TBT_X_TMS | Default | d | 0.583 | |
KBDBKLT_SW2 | Default | d | 0.426 | |
KBDP3V3_IOUT | Default | d | OL | |
KBD_CAPSLOCK_LED | Default | d | 0.503 | |
KBD_CAP_CATHODE | Default | d | 0.505 | |
KBD_CONTROL_KEY | Default | d | 0.477 | |
KBD_CONTROL_L | Default | d | 0.463 | |
KBD_DRIVE_Y0 | Default | d | 0.537 | |
KBD_DRIVE_Y1 | Default | d | 0.551 | |
KBD_DRIVE_Y2 | Default | d | 0.545 | |
KBD_DRIVE_Y3 | Default | d | 0.541 | |
KBD_DRIVE_Y4 | Default | d | 0.544 | |
KBD_DRIVE_Y5 | Default | d | 0.536 | |
KBD_DRIVE_Y6 | Default | d | 0.510 | |
KBD_DRIVE_Y7 | Default | d | 0.511 | |
KBD_ID1 | Default | d | 0.791 | |
KBD_ID_DETECT1 | Default | d | 0.541 | |
KBD_INT_L | Default | d | 0.688 | |
KBD_LEFT_OPTION_KEY | Default | d | 0.476 | |
KBD_LEFT_OPTION_L | Default | d | 0.460 | |
KBD_RIGHT_SHIFT_KEY | Default | d | 0.477 | |
KBD_RIGHT_SHIFT_L | Default | d | 0.460 | |
KBD_SENSE_X0 | Default | d | 0.574 | |
KBD_SENSE_X1 | Default | d | 0.582 | |
KBD_SENSE_X10 | Default | d | 0.573 | |
KBD_SENSE_X11 | Default | d | 0.586 | |
KBD_SENSE_X12 | Default | d | 0.583 | |
KBD_SENSE_X2 | Default | d | 0.577 | |
KBD_SENSE_X3 | Default | d | 0.571 | |
KBD_SENSE_X4 | Default | d | 0.590 | |
KBD_SENSE_X5 | Default | d | 0.583 | |
KBD_SENSE_X6 | Default | d | 0.523 | |
KBD_SENSE_X7 | Default | d | 0.520 | |
KBD_SENSE_X8 | Default | d | 0.522 | |
KBD_SENSE_X9 | Default | d | 0.526 | |
L83_FILT | Default | d | 0.803 | |
L83_FLYC | Default | d | 0.393 | |
L83_FLYN | Default | d | 0.464 | |
L83_FLYP | Default | d | 0.407 | |
L83_HSBIAS_FILT | Default | d | 0.720 | |
L83_HSBIAS_FILT_REF | Default | d | 0.639 | |
L83_SDOUT | Default | d | 0.489 | |
L83_VCP_FILTN | Default | d | 0.620 | |
L83_VCP_FILTP | Default | d | 0.397 | |
L83_VCP_FILT_GND | Default | d | 0.000 | |
LCDBKLT_EN_L | Default | d | OL | |
LCDBKLT_FB | Default | d | 0.731 | |
LCDBKLT_FET_DRV | Default | d | 0.559 | |
LCDBKLT_FET_DRV_R | Default | d | 0.569 | |
LCDBKLT_IOUT | Default | d | OL | |
LCDBKLT_SW | Default | d | 0.451 | |
LCDBKLT_TB_XWR | Default | d | 1.240 | |
LCDP5V_IOUT | Default | d | OL | |
LCDPANEL_IOUT | Default | d | OL | |
LCD_PWR_SLEW | Default | d | 0.721 | |
LED_CTRL | Default | d | 0.569 | |
LED_ISET | Default | d | 0.581 | |
LID_OPEN_LEFT | Default | d | 0.557 | |
LID_OPEN_RIGHT | Default | d | 0.698 | |
LPDDRP1V8_IOUT | Default | d | OL | |
MEMVTT_EN | Default | d | 0.533 | |
MEMVTT_EN_R | Default | d | 0.533 | |
MEM_VREFCA_RC | Default | d | 0.026 | |
MEM_VREFCA_RC | Default | r | 25.400R | |
MESA_BOOST_EN | Default | d | 0.529 | |
MESA_BOOST_EN_CONN | Default | d | 0.548 | |
MESA_INT | Default | d | 0.480 | |
MESA_INT_CONN | Default | d | 0.479 | |
MESA_PWR_EN | Default | d | 0.472 | |
MIPI_DFR_CLK_FILT_CONN_N | Default | d | 0.529 | |
MIPI_DFR_CLK_FILT_CONN_P | Default | d | 0.529 | |
MIPI_DFR_CLK_N | Default | d | 0.529 | |
MIPI_DFR_CLK_P | Default | d | 0.529 | |
MIPI_DFR_DATA_FILT_CONN_N | Default | d | 0.528 | |
MIPI_DFR_DATA_FILT_CONN_P | Default | d | 0.528 | |
MIPI_DFR_DATA_N | Default | d | 0.528 | |
MIPI_DFR_DATA_P | Default | d | 0.528 | |
MIPI_FTCAM_CLK_ISOL_FILT_CONN_N | Default | d | 0.498 | |
MIPI_FTCAM_CLK_ISOL_FILT_CONN_P | Default | d | 0.503 | |
MIPI_FTCAM_CLK_ISOL_N | Default | d | 0.497 | |
MIPI_FTCAM_CLK_ISOL_P | Default | d | 0.502 | |
MIPI_FTCAM_CLK_N | Default | d | 0.466 | |
MIPI_FTCAM_CLK_P | Default | d | 0.468 | |
MIPI_FTCAM_DATA_ISOL_FILT_CONN_N<0> | Default | d | 0.502 | |
MIPI_FTCAM_DATA_ISOL_FILT_CONN_P<0> | Default | d | 0.500 | |
MIPI_FTCAM_DATA_ISOL_N<0> | Default | d | 0.498 | |
MIPI_FTCAM_DATA_ISOL_P<0> | Default | d | 0.499 | |
MIPI_FTCAM_DATA_N<0> | Default | d | 0.467 | |
MIPI_FTCAM_DATA_P<0> | Default | d | 0.465 | |
MLB_RAMCFG0 | Default | d | 0.763 | |
MLB_RAMCFG1 | Default | d | 0.768 | |
MLB_RAMCFG2 | Default | d | 0.765 | |
MLB_RAMCFG3 | Default | d | 0.759 | |
MLB_RAMCFG4 | Default | d | 0.760 | |
NFC_GPIO2_AO | Default | d | 0.757 | |
NFC_GPIO3_AO | Default | d | 0.759 | |
NFC_XTAL1 | Default | d | 0.556 | |
NTC_A_CPUGT | Default | d | 0.636 | |
NTC_A_CPUGT_RN | Default | d | 0.001 | |
NTC_A_CPUGT_RN | Default | r | 0.700R | |
NTC_A_CPUGT_RP | Default | d | OL | |
NTC_B_CPUCORE | Default | d | 0.637 | |
NTC_B_CPUCORE_RN | Default | d | 0.001 | |
NTC_B_CPUCORE_RN | Default | r | 0.700R | |
NTC_B_CPUCORE_RP | Default | d | OL | |
OCARINA_FORCE_EN | Default | d | 0.582 | |
OCARINA_IREF | Default | d | 0.752 | |
OCARINA_NAND_VCC_DET | Default | d | 0.759 | |
OCARINA_PGOOD | Default | d | 0.763 | |
OCARINA_POK2 | Default | d | 0.000 | |
OCARINA_TCAL | Default | d | 0.773 | |
OCARINA_TDEV1 | Default | d | 0.772 | |
OCARINA_TDEV2 | Default | d | 0.772 | |
OCARINA_VDD_LDO | Default | d | 0.371 | |
OCARINA_VREF | Default | d | 0.770 | |
OPCE_RCOMP | Default | d | 0.051 | |
OPCE_RCOMP | Default | r | 50.700R | |
OPC_RCOMP | Default | d | 0.053 | |
OPC_RCOMP | Default | r | 50.400R | |
OUT123_EN | Default | d | 0.309 | |
P0V8SLPDDR_FB | Default | d | 0.036 | |
P0V8SLPDDR_FB | Default | r | 30.600R | |
P0V8SLPDDR_FB_R | Default | d | 0.034 | |
P0V8SLPDDR_FB_R | Default | r | 0.310R | |
P0V8SLPDDR_SW0 | Default | d | 0.048 | |
P0V8SLPDDR_SW1 | Default | d | 0.048 | |
P0V9SLPDDR_FB_R | Default | d | 0.054 | |
P0V9SLPDDR_FB_R | Default | r | 53.700R | |
P0V9SLPDDR_SW0 | Default | d | 0.055 | |
P0V9SLPDDR_SW1 | Default | d | 0.055 | |
P0V9SSD_FB_N | Default | d | 0.002 | |
P0V9SSD_FB_N | Default | r | 0.600R | |
P0V9SSD_FB_P | Default | d | 0.774 | |
P0V9SSD_FB_R_N | Default | d | 0.001 | |
P0V9SSD_FB_R_N | Default | r | 1.300R | |
P0V9SSD_FB_R_P | Default | d | 0.370 | |
P0V9SSD_SW0 | Default | d | 0.378 | |
P0V9_TBT_X_SVR_AGND | Default | d | 0.000 | |
P1V1SLPS2R_SW0 | Default | d | 0.272 | |
P1V1SLPS2R_SW1 | Default | d | 0.272 | |
P1V1_SLPDDR_SOCFET_EN | Default | d | 0.570 | |
P1V2REG_AGND | Default | d | 0.000 | |
P1V2REG_MODE | Default | d | 0.551 | |
P1V2REG_TRIP | Default | d | 0.752 | |
P1V2REG_VREF | Default | d | 0.646 | |
P1V2REG_VREF_R | Default | d | OL | |
P1V2S0SW_FET_EN | Default | d | 0.528 | |
P1V2S0SW_RAMP | Default | d | 0.703 | |
P1V2_BOOT_RC | Default | d | 0.633 | |
P1V2_DRVH | Default | d | 0.711 | |
P1V2_DRVH_R | Default | d | 0.712 | |
P1V2_DRVL | Default | d | 0.461 | |
P1V2_DRVL_R | Default | d | 0.462 | |
P1V2_LL_SNUB | Default | d | OL | |
P1V2_PHASE | Default | d | 0.224 | |
P1V2_SNS | Default | d | 0.228 | |
P1V2_SNS_R | Default | d | 0.223 | |
P1V2_SW | Default | d | 0.223 | |
P1V2_VBST | Default | d | 0.632 | |
P1V8G3S_DSCHG_EN | Default | d | 0.543 | |
P1V8G3S_DSCHG_EN_L | Default | d | 0.572 | |
P1V8G3S_DSCHG_PATH | Default | d | 0.316 | |
P1V8G3S_EN | Default | d | 0.572 | |
P1V8G3S_SS | Default | d | 0.708 | |
P1V8SLPS2R_SW0 | Default | d | 0.400 | |
P1V8_DFR_R | Default | d | 0.703 | |
P1VPRIM_FB | Default | d | 0.195 | |
P1VPRIM_FB_R | Default | d | 0.195 | |
P1VPRIM_SW0 | Default | d | 0.195 | |
P1VPRIM_SW1 | Default | d | 0.195 | |
P2V5_SSD_DISCHARGE | Default | d | OL | |
P3V3G3HRTC_FB | Default | d | 1.415 | |
P3V3G3HRTC_FB_R | Default | d | 0.380 | |
P3V3G3HRTC_PGOOD | Default | d | 0.696 | |
P3V3G3HRTC_PHASE1 | Default | d | 0.372 | |
P3V3G3HRTC_PHASE2 | Default | d | 0.372 | |
P3V3G3HRTC_RA_R | Default | d | 0.380 | |
P3V3G3HRTC_SS | Default | d | 0.539 | |
P3V3G3H_COMP2 | Default | d | 0.478 | |
P3V3G3H_COMP2_R | Default | d | OL | |
P3V3G3H_CS2_L_N | Default | d | 0.415 | |
P3V3G3H_CS2_L_P | Default | d | 0.417 | |
P3V3G3H_CSP2 | Default | d | 1.287 | |
P3V3G3H_DRVH | Default | d | 0.981 | |
P3V3G3H_DRVH_R | Default | d | 0.979 | |
P3V3G3H_DRVL | Default | d | 0.559 | |
P3V3G3H_DRVL_R | Default | d | 0.559 | |
P3V3G3H_RF | Default | d | 0.593 | |
P3V3G3H_SNUBR | Default | d | OL | |
P3V3G3H_SW | Default | d | 0.419 | |
P3V3G3H_VBST | Default | d | 0.636 | |
P3V3G3H_VBST_R | Default | d | 0.633 | |
P3V3G3H_VFB2 | Default | d | 0.592 | |
P3V3G3H_VFB2_R | Default | d | 0.419 | |
P3V3G3H_VFB2_R2 | Default | d | 0.427 | |
P3V3G3H_VFB2_RR | Default | d | OL | |
P3V3G3H_VSW | Default | d | 0.420 | |
P3V3G3H_VSW | Default | r | 0.200R | |
P3V3G3S_EN | Default | d | 0.572 | |
P3V3G3S_SS | Default | d | 0.708 | |
P3V3MAIN_PGOOD | Default | d | 0.583 | |
P3V3TBT_X_RAMP | Default | d | 0.502 | |
P5VG3S_COMP1 | Default | d | 0.750 | |
P5VG3S_COMP1_R | Default | d | OL | |
P5VG3S_CS1_L_N | Default | d | 0.423 | |
P5VG3S_CS1_L_P | Default | d | 0.425 | |
P5VG3S_CSP1 | Default | d | 1.263 | |
P5VG3S_DRVH | Default | d | 0.993 | |
P5VG3S_DRVH_R | Default | d | 0.985 | |
P5VG3S_DRVL | Default | d | 0.559 | |
P5VG3S_DRVL_R | Default | d | 0.558 | |
P5VG3S_EN | Default | d | 0.575 | |
P5VG3S_EN_DLY | Default | d | 0.522 | |
P5VG3S_EN_R | Default | d | 0.574 | |
P5VG3S_PGOOD | Default | d | 0.585 | |
P5VG3S_SNUBR | Default | d | OL | |
P5VG3S_SW | Default | d | 0.425 | |
P5VG3S_VBST | Default | d | 0.633 | |
P5VG3S_VBST_R | Default | d | 0.634 | |
P5VG3S_VFB1 | Default | d | 0.587 | |
P5VG3S_VFB1_R | Default | d | 0.426 | |
P5VG3S_VFB1_R2 | Default | d | 0.434 | |
P5VG3S_VFB1_RR | Default | d | OL | |
P5VG3S_VSW | Default | d | 0.428 | |
P5VG3S_VSW | Default | r | 0.100R | |
P5VP3V3_SKIPSEL | Default | d | 0.489 | |
P5VP3V3_VREF2 | Default | d | 0.488 | |
P5VP3V3_VREG3 | Default | d | 0.517 | |
P5VXX_EN | Default | d | 0.592 | |
P5V_S4SW_SNS_FET_RAMP | Default | d | OL | |
PANEL_P3V3_EN | Default | d | 0.574 | |
PANEL_P3V3_EN_D | Default | d | 0.755 | |
PANEL_P5V_EN | Default | d | 0.573 | |
PANEL_P5V_EN_D | Default | d | 1.038 | |
PBUSVSENS_EN_L | Default | d | 0.486 | |
PBUSVSENS_EN_L_DIV | Default | d | OL | |
PBUS_DIVIDER | Default | d | 0.707 | |
PBUS_DIVIDER_OUT | Default | d | 0.666 | |
PBUS_DIVIDER_REF | Default | d | 0.673 | |
PBUS_S0_VSENSE | Default | d | OL | |
PBUS_S0_VSENSE_IN | Default | d | 0.336 | |
PCH_BATLOW_L | Default | d | 0.817 | |
PCH_BT_AUDIO_SYNC | Default | d | 0.678 | |
PCH_BT_ROM_BOOT_L | Default | d | 0.550 | |
PCH_CLK24M_XTALIN | Default | d | 0.836 | |
PCH_CLK24M_XTALOUT | Default | d | 0.833 | |
PCH_CLK24M_XTALOUT_R | Default | d | 0.831 | |
PCH_CLKIN_XTAL | Default | d | 0.003 | |
PCH_CLKIN_XTAL | Default | r | 0.700R | |
PCH_DDPB_CTRLDATA | Default | d | 0.794 | |
PCH_DDPC_CTRLDATA | Default | d | 0.794 | |
PCH_DIFFCLK_BIASREF | Default | d | 0.063 | |
PCH_DIFFCLK_BIASREF | Default | r | 60.600R | |
PCH_GPP_A6 | Default | d | 0.819 | |
PCH_GPP_A7 | Default | d | 0.818 | |
PCH_HSIO_PWR_EN | Default | d | 0.815 | |
PCH_INTRUDER_L | Default | d | 0.844 | |
PCH_JTAGX | Default | d | 0.052 | |
PCH_JTAGX | Default | r | 51.800R | |
PCH_LAN_WAKE_L | Default | d | 0.816 | |
PCH_OPIRCOMP | Default | d | 0.052 | |
PCH_OPIRCOMP | Default | r | 50.600R | |
PCH_PCIE_CLK100M_WLAN_N | Default | d | 0.535 | |
PCH_PCIE_CLK100M_WLAN_P | Default | d | 0.336 | |
PCH_PCIE_RCOMP_N | Default | d | 0.314 | |
PCH_PCIE_RCOMP_P | Default | d | 0.315 | |
PCH_PCIE_WLAN_D2R_C_N | Default | d | 0.396 | |
PCH_PCIE_WLAN_D2R_C_P | Default | d | 0.395 | |
PCH_PCIE_WLAN_D2R_N | Default | d | 0.346 | |
PCH_PCIE_WLAN_D2R_P | Default | d | 0.346 | |
PCH_PCIE_WLAN_R2D_C_N | Default | d | 0.331 | |
PCH_PCIE_WLAN_R2D_C_P | Default | d | 0.334 | |
PCH_PCIE_WLAN_R2D_N | Default | d | 0.517 | |
PCH_PCIE_WLAN_R2D_P | Default | d | 0.520 | |
PCH_PWRBTN_L | Default | d | 0.762 | |
PCH_RTC_RESET_L | Default | d | 0.768 | |
PCH_SOC_SYNC | Default | d | 0.474 | |
PCH_STRP_CNV_DISABLE | Default | d | 0.540 | |
PCH_STRP_ESPI | Default | d | 0.800 | |
PCH_STRP_GPD7 | Default | d | 0.817 | |
PCH_STRP_JTAGODTDIS | Default | d | 0.810 | |
PCH_STRP_NO_REBOOT | Default | d | 0.799 | |
PCH_STRP_SPIROM_SAF | Default | d | 0.803 | |
PCH_STRP_XTAL_24MHZ | Default | d | 0.801 | |
PCH_SWD_SOC_CLK | Default | d | 0.554 | |
PCH_SWD_SOC_IO | Default | d | 0.543 | |
PCH_UART2_CTS_L | Default | d | 0.819 | |
PCH_UART_DEBUG_D2R | Default | d | 0.697 | |
PCH_UART_DEBUG_R2D | Default | d | 0.702 | |
PCH_UART_DEBUG_R_D2R | Default | d | 0.705 | |
PCH_UART_DEBUG_R_R2D | Default | d | 0.701 | |
PCH_USB2_COMP | Default | d | 0.116 | |
PCH_USB2_VBUSSENSE | Default | d | 0.781 | |
PCH_WLAN_AUDIO_SYNC | Default | d | 0.682 | |
PCH_WLAN_CLKREQ_L | Default | d | 0.818 | |
PCH_WLAN_CLKREQ_R_L | Default | d | 0.559 | |
PCH_WLAN_DEV_WAKE | Default | d | 0.826 | |
PCH_WLAN_PERST_L | Default | d | 0.534 | |
PCIE_CLK100M_SSD0_01_N | Default | d | 0.128 | |
PCIE_CLK100M_SSD0_01_P | Default | d | 0.128 | |
PCIE_CLK100M_TBT_X_N | Default | d | 0.330 | |
PCIE_CLK100M_TBT_X_P | Default | d | 0.336 | |
PCIE_PME_L | Default | d | 0.564 | |
PCIE_SSD0_D2R_N<0> | Default | d | 0.407 | |
PCIE_SSD0_D2R_P<0> | Default | d | 0.404 | |
PCIE_WAKE_L | Default | d | 0.813 | |
PDM_DMIC_CLK0 | Default | d | 0.492 | |
PDM_DMIC_CLK0_R | Default | d | 0.471 | |
PDM_DMIC_CLK1 | Default | d | 0.490 | |
PDM_DMIC_CLK1_R | Default | d | 0.471 | |
PDM_DMIC_DATA0_UNSEC | Default | d | 0.551 | |
PDM_DMIC_DATA1 | Default | d | 0.459 | |
PDM_DMIC_DATA1_RR | Default | d | 0.475 | |
PDM_DMIC_DATA1_UNSEC | Default | d | 0.548 | |
PD_UPC_XA_GPIO4 | Default | d | 0.677 | |
PD_UPC_XB_GPIO1 | Default | d | 0.682 | |
PD_UPC_XB_GPIO10 | Default | d | 0.714 | |
PD_UPC_XB_GPIO4 | Default | d | 0.689 | |
PD_UPC_XB_GPIO9 | Default | d | 0.709 | |
PD_UPC_X_5V_EN | Default | d | 0.641 | |
PLT_RST_3V3_L | Default | d | 0.594 | |
PLT_RST_L | Default | d | 0.559 | |
PMIC_DISCHARGE_EN_RC | Default | d | OL | |
PMU_ACTIVE_READY | Default | d | 0.473 | |
PMU_CLK32K_PCH | Default | d | 0.805 | |
PMU_CLK32K_PCH_1V0 | Default | d | 0.862 | |
PMU_CLK32K_PCH_R | Default | d | 0.773 | |
PMU_CLK32K_SOC | Default | d | 0.474 | |
PMU_CLK32K_SOC_R | Default | d | 0.506 | |
PMU_CLK32K_WLANBT | Default | d | 0.458 | |
PMU_CLK32K_WLANBT_R | Default | d | 0.491 | |
PMU_COLD_RESET_L | Default | d | 0.468 | |
PMU_CPUDDR_ISENSE | Default | d | 0.591 | |
PMU_CPUEDRAM_ISENSE | Default | d | 0.589 | |
PMU_CPUGT_ISENSE | Default | d | 0.588 | |
PMU_CPUGT_VSENSE | Default | d | 0.582 | |
PMU_CPUSA_ISENSE | Default | d | 0.591 | |
PMU_CPUSA_VSENSE | Default | d | 0.584 | |
PMU_CPUVCCIO_ISENSE | Default | d | 0.589 | |
PMU_CPU_ISENSE | Default | d | 0.591 | |
PMU_CPU_VSENSE | Default | d | 0.583 | |
PMU_DDR1V2_ISENSE | Default | d | 0.589 | |
PMU_DROOP_L | Default | d | 0.480 | |
PMU_FORCE_DFU | Default | d | 0.769 | |
PMU_INT_L | Default | d | 0.472 | |
PMU_IREF | Default | d | 0.759 | |
PMU_LCDPANEL_ISENSE | Default | d | 0.592 | |
PMU_LDO3_OUT_R | Default | d | 0.597 | |
PMU_OCARINA_ISENSE | Default | d | 0.592 | |
PMU_ONOFF_L | Default | d | 0.581 | |
PMU_ONOFF_R_L | Default | d | 0.578 | |
PMU_ONOFF_R_L_CONN | Default | d | 0.576 | |
PMU_OTHER3V3_HI_ISENSE | Default | d | 0.591 | |
PMU_OTHER5V_HI_ISENSE | Default | d | 0.592 | |
PMU_P5V_CPUREGMISC_ISENSE | Default | d | 0.589 | |
PMU_PVDDMAIN_EN | Default | d | 0.774 | |
PMU_RSLOC_RST_L | Default | d | 0.514 | |
PMU_SSDNAND_ISENSE | Default | d | 0.591 | |
PMU_SYS_ALIVE | Default | d | 0.418 | |
PMU_VDD_MAX | Default | d | 0.558 | |
PM_MEMVTT_EN | Default | d | 0.380 | |
PM_OPC_ZVM_L | Default | d | 0.528 | |
PM_PCH_PWROK | Default | d | 0.485 | |
PM_PCH_SYS_PWROK | Default | d | 0.518 | |
PM_RSMRST_L | Default | d | 0.502 | |
PM_SLP_S0_3V3_L | Default | d | 0.787 | |
PM_SLP_S0_L | Default | d | 0.471 | |
PM_SLP_S3_L | Default | d | 0.585 | |
PM_SLP_S4_L | Default | d | 0.819 | |
PM_SLP_S5_L | Default | d | 0.817 | |
PM_SLP_SUS_L | Default | d | 0.812 | |
PM_SLP_TIEOFF | Default | d | 0.718 | |
PM_SYSRST_L | Default | d | 0.814 | |
PM_SYSRST_R_L | Default | d | 0.521 | |
PM_THRMTRIP_L | Default | d | 0.260 | |
PP0V6_S0_DDRVTT | Default | d | 0.137 | |
PP0V6_S3_MEM_VREFCA_A | Default | d | 0.378 | |
PP0V6_S3_MEM_VREFDQ_A | Default | d | 0.380 | |
PP0V6_S3_MEM_VREFDQ_B | Default | d | 0.378 | |
PP0V82_SLPDDR | Default | d | 0.048 | |
PP0V82_SLPDDR | Default | r | 32.400R | |
PP0V8_SLPS2R | Default | d | 0.220 | |
PP0V95_S0_CPUVCCIO_REG_R | Default | d | 0.124 | |
PP0V9_SLPDDR | Default | d | 0.055 | |
PP0V9_SLPDDR | Default | r | 53.800R | |
PP0V9_SLPDDR_SOC_PCIEREFBUF | Default | d | 0.062 | |
PP0V9_SLPDDR_SOC_PCIEREFBUF | Default | r | 61.900R | |
PP0V9_SSD0 | Default | d | 0.378 | |
PP0V9_SSD0_S4E0_VDD_PLL | Default | d | 0.368 | |
PP0V9_SSD0_S4E1_VDD_PLL | Default | d | 0.366 | |
PP0V9_SSD0_S4E2_VDD_PLL | Default | d | 0.380 | |
PP0V9_SSD0_S4E3_VDD_PLL | Default | d | 0.380 | |
PP0V9_TBT_X_LC | Default | d | 0.340 | |
PP0V9_TBT_X_LVR | Default | d | 0.274 | |
PP0V9_TBT_X_PCIE | Default | d | 0.299 | |
PP0V9_TBT_X_SVR | Default | d | 0.282 | |
PP16V0_MESA | Default | d | 0.654 | |
PP16V0_MESA_FILT_CONN | Default | d | 0.655 | |
PP17V0_MOJAVE_LDOIN | Default | d | 0.594 | |
PP1V05_PRIMSW_PCH_VCCAMPHYPLL_F | Default | d | 0.191 | |
PP1V05_PRIM_PCH_VCCA19P2_XW | Default | d | 0.192 | |
PP1V05_PRIM_PCH_VCCABCLK_XW | Default | d | 0.192 | |
PP1V05_PRIM_PCH_VCCAPLL_AUD_F | Default | d | 0.192 | |
PP1V05_PRIM_PCH_VCCASRC_XW | Default | d | 0.191 | |
PP1V05_PRIM_PCH_VCCAXTAL_F | Default | d | 0.190 | |
PP1V05_PRIM_PCH_VCCDUSB_XW | Default | d | 0.192 | |
PP1V05_S5_PCH_VCCDSW | Default | d | 0.514 | |
PP1V1_SLPDDR | Default | d | 0.347 | |
PP1V1_SLPDDR_SOC_VDDIOPLLDDR_F | Default | d | 0.347 | |
PP1V1_SLPDDR_SOC_XTAL_F | Default | d | 0.347 | |
PP1V1_SLPS2R | Default | d | 0.262 | |
PP1V24_S5_PCH_VCCDPHY | Default | d | 0.414 | |
PP1V25_SLPS2R_SMC_AVREF | Default | d | 0.690 | |
PP1V2_AWAKE | Default | d | 0.532 | |
PP1V2_AWAKE_SOC_PCIEPLL_F | Default | d | 0.530 | |
PP1V2_AWAKE_SOC_PCIEREFBUF_F | Default | d | 0.533 | |
PP1V2_AWAKE_SOC_PLLCPU_F | Default | d | 0.528 | |
PP1V2_AWAKE_SOC_PLLSOC_F | Default | d | 0.528 | |
PP1V2_S0SW | Default | d | 0.304 | |
PP1V2_S3 | Default | d | 0.224 | |
PP1V2_S3_CPUDDR | Default | d | 0.219 | |
PP1V2_S3_REG_R | Default | d | 0.224 | |
PP1V5_UPC_XA_LDO_CORE | Default | d | 0.520 | |
PP1V5_UPC_XB_LDO_CORE | Default | d | 0.515 | |
PP1V8_ACCEL_FILT | Default | d | OL | |
PP1V8_AWAKE | Default | d | 0.403 | |
PP1V8_AWAKE_SOC_FMON_RC | Default | d | 0.453 | |
PP1V8_AWAKE_SOC_TSADC_RC | Default | d | 0.403 | |
PP1V8_CODEC_VCP | Default | d | 0.305 | |
PP1V8_CODEC_VL | Default | d | 0.306 | |
PP1V8_DFR | Default | d | 0.548 | |
PP1V8_DIS | Default | d | 0.673 | |
PP1V8_DMIC | Default | d | 0.309 | |
PP1V8_G3S | Default | d | 0.308 | |
PP1V8_G3S_REG | Default | d | 0.306 | |
PP1V8_G3S_WLANBT | Default | d | 0.310 | |
PP1V8_IO_SSD0 | Default | d | 0.363 | |
PP1V8_IO_SSD0_R | Default | d | 0.761 | |
PP1V8_IO_SSD0_R2 | Default | d | OL | |
PP1V8_MESA | Default | d | 0.528 | |
PP1V8_MESA_FILT_CONN | Default | d | 0.528 | |
PP1V8_PRIM_PCH_VCCHDA_F | Default | d | 0.314 | |
PP1V8_S0_THMSNSA_R | Default | d | 0.316 | |
PP1V8_S0_THMSNSB_R | Default | d | 0.314 | |
PP1V8_S3 | Default | d | 0.466 | |
PP1V8_S3_MEM | Default | d | 0.466 | |
PP1V8_S5 | Default | d | 0.314 | |
PP1V8_SLPS2R | Default | d | 0.351 | |
PP1V8_SLPS2R_PMUVDDGPIO | Default | d | 0.740 | |
PP1V8_SLPS2R_SOC_LPADC_RC | Default | d | 0.435 | |
PP1V8_SLPS2R_SOC_LPOSC_RC | Default | d | 0.449 | |
PP1V8_SSD0_S4E0_AVDD18_PLL | Default | d | 0.359 | |
PP1V8_SSD0_S4E0_PCI_AVDD_H | Default | d | 0.359 | |
PP1V8_SSD0_S4E1_AVDD18_PLL | Default | d | 0.359 | |
PP1V8_SSD0_S4E1_PCI_AVDD_H | Default | d | 0.359 | |
PP1V8_SSD0_S4E2_AVDD18_PLL | Default | d | 0.363 | |
PP1V8_SSD0_S4E2_PCI_AVDD_H | Default | d | 0.363 | |
PP1V8_SSD0_S4E3_AVDD18_PLL | Default | d | 0.360 | |
PP1V8_SSD0_S4E3_PCI_AVDD_H | Default | d | 0.363 | |
PP1V_PRIM | Default | d | 0.195 | |
PP1V_S0SW | Default | d | 0.223 | |
PP1V_S3 | Default | d | 0.229 | |
PP20V_USBC_XA_VBUS | Default | d | 0.136 | |
PP20V_USBC_XB_VBUS | Default | d | 0.141 | |
PP2V5_ADC2_VREF | Default | d | OL | |
PP2V5_NAND_SSD0 | Default | d | 0.416 | |
PP2V5_SSD0_AGND | Default | d | 0.000 | |
PP3V0_MESA | Default | d | 0.561 | |
PP3V0_MESA_FILT_CONN | Default | d | 0.560 | |
PP3V3_AWAKE | Default | d | 0.646 | |
PP3V3_CODEC_VP | Default | d | 0.368 | |
PP3V3_G3H | Default | d | 0.420 | |
PP3V3_G3H | Default | r | 0.200R | |
PP3V3_G3HSW_DFR | Default | d | 0.570 | |
PP3V3_G3H_BMU | Default | d | 0.414 | |
PP3V3_G3H_DFUMUX | Default | d | OL | |
PP3V3_G3H_MESA_SW | Default | d | 0.370 | |
PP3V3_G3H_PMU_VDDMAIN | Default | d | 0.415 | |
PP3V3_G3H_PMU_VINRTC_R | Default | d | 0.370 | |
PP3V3_G3H_RSLOC | Default | d | 0.371 | |
PP3V3_G3H_RTC | Default | d | 0.371 | |
PP3V3_G3H_RTC_DFR | Default | d | 0.369 | |
PP3V3_G3H_RTC_MESA | Default | d | 0.369 | |
PP3V3_G3H_RTC_REG_R | Default | d | 0.372 | |
PP3V3_G3H_SSD0 | Default | d | 0.420 | |
PP3V3_G3S | Default | d | 0.379 | |
PP3V3_G3S_KBD | Default | d | 0.380 | |
PP3V3_G3S_TPAD | Default | d | 0.379 | |
PP3V3_G3S_WLANBT | Default | d | 0.379 | |
PP3V3_S0SW_LCD | Default | d | 0.494 | |
PP3V3_S0SW_LCD_R | Default | d | 0.494 | |
PP3V3_S0_TBT_X_ISNS_R | Default | d | 0.527 | |
PP3V3_S4SW_SNS | Default | d | 0.541 | |
PP3V3_S5 | Default | d | 0.379 | |
PP3V3_TBT_X_ANA | Default | d | 0.533 | |
PP3V3_TBT_X_ANA_PCIE | Default | d | 0.511 | |
PP3V3_TBT_X_ANA_USB2 | Default | d | 0.492 | |
PP3V3_TBT_X_LC | Default | d | 0.565 | |
PP3V3_TBT_X_S0 | Default | d | 0.528 | |
PP3V3_TBT_X_SX | Default | d | 0.496 | |
PP3V3_TBT_X_SX_R | Default | d | 0.502 | |
PP3V3_UPC_XA_LDO | Default | d | 0.506 | |
PP3V3_UPC_XB_LDO | Default | d | 0.495 | |
PP3V_G3H_RTC | Default | d | 0.457 | |
PP5V_COREVR_VCC | Default | d | 0.423 | |
PP5V_EADC2_AVDD | Default | d | OL | |
PP5V_EDRAM_V5IN | Default | d | 0.423 | |
PP5V_G3H_LDO | Default | d | 0.491 | |
PP5V_G3S | Default | d | 0.428 | |
PP5V_G3S | Default | r | 0.100R | |
PP5V_G3S_ALSCAM | Default | d | 0.423 | |
PP5V_G3S_CPUREG_MISC | Default | d | 0.420 | |
PP5V_G3S_DFR_FILT | Default | d | 0.428 | |
PP5V_G3S_EDRAMPVCC | Default | d | 0.426 | |
PP5V_G3S_EDRAMVCC | Default | d | 0.426 | |
PP5V_G3S_FAN | Default | d | 0.423 | |
PP5V_G3S_KBD | Default | d | 0.426 | |
PP5V_G3S_TPAD | Default | d | 0.423 | |
PP5V_G3S_TPAD_CONN | Default | d | 0.425 | |
PP5V_G3S_VCCIOPVCC | Default | d | 0.425 | |
PP5V_G3S_VCCIOVCC | Default | d | 0.425 | |
PP5V_MAIN_VCCSA | Default | d | 0.424 | |
PP5V_MAIN_VCORE1 | Default | d | 0.425 | |
PP5V_MAIN_VCORE2 | Default | d | 0.423 | |
PP5V_MAIN_VGT1 | Default | d | 0.425 | |
PP5V_MAIN_VGT2 | Default | d | 0.425 | |
PP5V_S0SW_LCD | Default | d | 0.572 | |
PP5V_S0SW_LCD_R | Default | d | 0.572 | |
PP5V_S0_BKLT_A | Default | d | 0.436 | |
PP5V_S0_BKLT_D | Default | d | 0.433 | |
PP5V_S4SW | Default | d | OL | |
PP5V_WLAN_ISNS_D | Default | d | OL | |
PPBUS_G3H | Default | d | 0.336 | |
PPBUS_G3H | Default | v | 12.650 | |
PPBUS_G3H_SPKRAMP_LEFT | Default | d | 0.338 | |
PPBUS_G3H_SPKRAMP_RIGHT | Default | d | 0.338 | |
PPBUS_G3H_SSD0 | Default | d | 0.340 | |
PPBUS_HS_CPU | Default | d | 0.336 | |
PPDCIN_G3H | Default | d | 0.562 | |
PPDCIN_G3H | Default | v | 19.300 | |
PPDCIN_G3H_CHGR | Default | d | 0.562 | |
PPDCIN_XA_G3H_F | Default | d | 0.562 | |
PPDCIN_XB_G3H_F | Default | v | 19.300 | |
PPDCPRTC_PCH | Default | d | 0.672 | |
PPVBAT_G3H_CHGR_R | Default | d | 0.336 | |
PPVBAT_G3H_CHGR_R | Default | v | 12.650 | |
PPVBAT_G3H_CHGR_REG | Default | d | 0.336 | |
PPVBAT_G3H_CHGR_REG | Default | v | 12.650 | |
PPVBAT_G3H_CONN | Default | d | 1.570 | |
PPVCCEDRAM_S0_CPU | Default | d | 0.047 | |
PPVCCEDRAM_S0_REG_R | Default | d | 0.047 | |
PPVCCEDRAM_S0_REG_R | Default | r | 47.500R | |
PPVCCGT_CPU_PH1 | Default | d | 0.006 | |
PPVCCGT_CPU_PH1 | Default | r | 5.100R | |
PPVCCGT_CPU_PH2 | Default | d | 0.006 | |
PPVCCGT_CPU_PH2 | Default | r | 5.100R | |
PPVCCGT_S0_CPU | Default | d | 0.006 | |
PPVCCGT_S0_CPU | Default | r | 5.100R | |
PPVCCIO_S0_CPU | Default | d | 0.124 | |
PPVCCQ_ANI_SSD0 | Default | d | 0.363 | |
PPVCCSA_CPU_R | Default | d | 0.023 | |
PPVCCSA_CPU_R | Default | r | 23.000R | |
PPVCCSA_S0_CPU | Default | d | 0.023 | |
PPVCCSA_S0_CPU | Default | r | 23.000R | |
PPVCC_CPU_PH1 | Default | d | 0.006 | |
PPVCC_CPU_PH1 | Default | r | 5.200R | |
PPVCC_CPU_PH2 | Default | d | 0.006 | |
PPVCC_CPU_PH2 | Default | r | 5.200R | |
PPVCC_S0_CPU | Default | d | 0.006 | |
PPVCC_S0_CPU | Default | r | 5.200R | |
PPVCC_S0_CPU | Default | t | Starts at 0.8V drops to 0V for about 1 second then comes back to 0.6V if CPU is working fine, this bahaivior is equivalent to fan spin. | |
PPVCC_S0_CPU | Default | v | - | |
PPVCC_SW1_TPS62180 | Default | d | 0.416 | |
PPVCC_SW2_TPS62180 | Default | d | 0.416 | |
PPVDDCPUSRAM_AWAKE | Default | d | 0.388 | |
PPVDDCPU_AWAKE | Default | d | 0.012 | |
PPVDDCPU_AWAKE | Default | r | 9.800R | |
PPVDD_SE_VDDA | Default | d | 0.335 | |
PPVIN_G3H_P3V3G3H | Default | d | 0.336 | |
PPVIN_G3H_P3V3G3H | Default | v | 12.650 | |
PPVIN_G3H_P3V3G3HRTC | Default | d | 0.337 | |
PPVIN_G3H_P3V3G3HRTC_R | Default | d | 0.337 | |
PPVIN_G3H_P5VG3S | Default | d | 0.338 | |
PPVIN_S0SW_LCDBKLT | Default | d | 0.899 | |
PPVIN_S0SW_LCDBKLT | Default | r | 0.573R | |
PPVIN_S0SW_LCDBKLT_F | Default | d | 0.336 | |
PPVIN_S0SW_LCDBKLT_F | Default | v | 12.650 | |
PPVIN_S0SW_LCDBKLT_R | Default | d | 0.336 | |
PPVIN_S0SW_LCDBKLT_R | Default | v | 12.650 | |
PPVIN_S0_CPUVR_VIN | Default | d | 0.344 | |
PPVIN_SW_LCDBKLT_SW | Default | d | 0.899 | |
PPVIN_SW_LCDBKLT_SW | Default | r | 0.573R | |
PPVOUT_BKLT_FB2 | Default | d | 0.634 | |
PPVOUT_S0_KBDLED | Default | d | 0.634 | |
PPVOUT_S0_KBDLED_R | Default | d | 0.635 | |
PPVOUT_S0_LCDBKLT | Default | d | 1.250 | |
PPVOUT_S0_LCDBKLT_F | Default | d | 1.256 | |
PPVPCORE_S5 | Default | d | 0.299 | |
PPVTT_VTTREF | Default | d | 0.492 | |
PP_KBDLED_CATHODE1 | Default | d | 0.674 | |
PP_KBDLED_CATHODE1_R | Default | d | OL | |
PP_KBDLED_CATHODE2 | Default | d | 0.671 | |
PP_KBDLED_CATHODE2_R | Default | d | OL | |
PP_SSD0_S4E0_VPP | Default | d | 0.569 | |
PP_SSD0_S4E1_VPP | Default | d | 0.602 | |
PP_SSD0_S4E2_VPP | Default | d | 0.602 | |
PP_SSD0_S4E3_VPP | Default | d | 0.603 | |
PP_VDD_SE_VDDC | Default | d | 0.343 | |
PP_VDD_SE_VDDNV | Default | d | 0.367 | |
PP_VDD_SE_VDDPLL | Default | d | 0.365 | |
PP_VDD_SE_VHV | Default | d | 0.323 | |
PP_VDD_SE_VREF | Default | d | 0.698 | |
PROC_POPIRCOMP | Default | d | 0.053 | |
PROC_POPIRCOMP | Default | r | 50.200R | |
PROG1_CPUCOREVR | Default | d | 0.630 | |
PROG2_CPUCOREVR | Default | d | 0.628 | |
PROG3_CPUCOREVR | Default | d | 0.632 | |
PROG4_CPUCOREVR | Default | d | 0.633 | |
PROG5_CPUCOREVR | Default | d | 0.634 | |
PVCCCGT_PH1_AGND | Default | d | 0.001 | |
PVCCCGT_PH1_AGND | Default | r | 0.600R | |
PVCCCGT_PH2_AGND | Default | d | 0.000 | |
PVCCCGT_PH2_AGND | Default | r | 0.700R | |
PVCCCORE_PH1_AGND | Default | d | 0.001 | |
PVCCCORE_PH1_AGND | Default | r | 0.600R | |
PVCCCORE_PH2_AGND | Default | d | 0.001 | |
PVCCCORE_PH2_AGND | Default | r | 0.600R | |
PVCCCSA_AGND | Default | d | 0.000 | |
PVCCEDRAMS0_AGND | Default | d | 0.000 | |
PVCCEDRAMS0_CS_N | Default | d | 0.047 | |
PVCCEDRAMS0_CS_P | Default | d | 0.047 | |
PVCCEDRAMS0_EN | Default | d | 0.586 | |
PVCCEDRAMS0_EN_FILT | Default | d | 0.478 | |
PVCCEDRAMS0_EN_FILT_BUF | Default | d | 0.524 | |
PVCCEDRAMS0_EN_R | Default | d | 0.490 | |
PVCCEDRAMS0_FB | Default | d | 0.554 | |
PVCCEDRAMS0_FSEL | Default | d | 0.573 | |
PVCCEDRAMS0_OCSET | Default | d | 0.562 | |
PVCCEDRAMS0_RTN | Default | d | 0.556 | |
PVCCEDRAMS0_SREF | Default | d | 0.567 | |
PVCCEDRAMS0_VO | Default | d | 0.561 | |
PVCCEDRAM_BOOT_RC | Default | d | 0.572 | |
PVCCEDRAM_DRVH | Default | d | 0.584 | |
PVCCEDRAM_DRVH_R | Default | d | 0.589 | |
PVCCEDRAM_DRVL | Default | d | 0.474 | |
PVCCEDRAM_DRVL_R | Default | d | 0.476 | |
PVCCEDRAM_LL | Default | d | 0.045 | |
PVCCEDRAM_LL_SNUB | Default | d | OL | |
PVCCEDRAM_PHASE | Default | d | 0.047 | |
PVCCEDRAM_PHASE | Default | r | 47.500R | |
PVCCEDRAM_REFIN | Default | d | 0.699 | |
PVCCEDRAM_VBST | Default | d | 0.570 | |
PVCCEOPIO_EDRAM_PGOOD | Default | d | 0.564 | |
PVCCIOS0_AGND | Default | d | 0.001 | |
PVCCIOS0_AGND | Default | r | 0.900R | |
PVCCIOS0_CS_N | Default | d | 0.124 | |
PVCCIOS0_CS_P | Default | d | 0.124 | |
PVCCIOS0_EN | Default | d | 0.588 | |
PVCCIOS0_EN_FILT | Default | d | 0.482 | |
PVCCIOS0_EN_FILT_BUF | Default | d | 0.522 | |
PVCCIOS0_EN_R | Default | d | 0.501 | |
PVCCIOS0_FB | Default | d | 0.554 | |
PVCCIOS0_FSEL | Default | d | 0.569 | |
PVCCIOS0_RTN | Default | d | 0.553 | |
PVCCIOS0_SREF | Default | d | 0.566 | |
PVCCIOS0_VO | Default | d | 0.560 | |
PVCCIO_BOOT_RC | Default | d | 0.587 | |
PVCCIO_DRVH | Default | d | 0.578 | |
PVCCIO_DRVH_R | Default | d | 0.578 | |
PVCCIO_DRVL | Default | d | 0.472 | |
PVCCIO_DRVL_R | Default | d | 0.472 | |
PVCCIO_EN | Default | d | 0.579 | |
PVCCIO_LL | Default | d | 0.124 | |
PVCCIO_LL_SNUB | Default | d | OL | |
PVCCIO_PGOOD | Default | d | 0.567 | |
PVCCIO_PHASE | Default | d | 0.124 | |
PVCCIO_VBST | Default | d | 0.585 | |
PVCCOIOS0_OCSET | Default | d | 0.560 | |
PVCCPLLOC_EN | Default | d | 0.506 | |
PVCCQSSD_FB | Default | d | 0.766 | |
PVCCQSSD_FB_R | Default | d | 0.362 | |
PVCCQSSD_SW0 | Default | d | 0.363 | |
PVCCQ_LX0 | Default | d | 0.363 | |
PVCCQ_SSD_FB_DIS | Default | d | 0.361 | |
PVCC_FB_N | Default | d | 0.001 | |
PVCC_FB_N | Default | r | 1.400R | |
PVCC_FB_P | Default | d | 0.300 | |
PVDDCPUAWAKE_FB_R | Default | d | 0.011 | |
PVDDCPUAWAKE_FB_R | Default | r | 10.900R | |
PVDDCPUAWAKE_SW2 | Default | d | 0.010 | |
PVDDCPUAWAKE_SW3 | Default | d | 0.010 | |
PVDDCPUSRAMAWAKE_SW0 | Default | d | 0.388 | |
PVDDQ_EN | Default | d | 0.568 | |
PVDDQ_EN_R | Default | d | 0.564 | |
PVDDQ_PGOOD | Default | d | 0.577 | |
PVDD_LX0 | Default | d | 0.378 | |
PVDD_LX1 | Default | d | 0.378 | |
PVDD_SSD_FB_DIS | Default | d | 0.372 | |
PVDD_SSD_FB_R | Default | d | 0.371 | |
PVPCORES5_FB_N | Default | d | 0.002 | |
PVPCORES5_FB_N | Default | r | 1.500R | |
PVPCORES5_FB_P | Default | d | 0.300 | |
PVPCORES5_SW0 | Default | d | 0.299 | |
PVPCORES5_SW1 | Default | d | 0.299 | |
PVTT_VTTSNS | Default | d | 0.137 | |
PWR_SCL_R0 | Default | d | 0.470 | |
PWR_SDA_R0 | Default | d | 0.467 | |
RSLOC_RST_L | Default | d | 0.490 | |
S4E2_DROOP_L | Default | d | 0.535 | |
S4E3_DROOP_L | Default | d | 0.492 | |
SAVE_BAT_G | Default | d | 0.775 | |
SAVE_BAT_S | Default | d | 1.569 | |
SA_ISUMN_R | Default | d | 1.026 | |
SD_RCOMP | Default | d | 0.202 | |
SENSOR_PWR_EN | Default | d | 0.634 | |
SEP_CAM_DISABLE_DFF_L | Default | d | 0.497 | |
SEP_CAM_DISABLE_L | Default | d | 0.468 | |
SEP_DISABLE_STROBE | Default | d | 0.470 | |
SEP_DMIC_DISABLE_L | Default | d | 0.470 | |
SEP_DMIC_DISABLE_OUT_L | Default | d | 0.503 | |
SEP_WP | Default | d | 0.749 | |
SE_CTLR_FW_DWLD | Default | d | 0.471 | |
SE_DEV_WAKE | Default | d | 0.466 | |
SE_HOST_WAKE | Default | d | 0.467 | |
SE_HOST_WAKE_R | Default | d | 0.466 | |
SE_PWR_EN | Default | d | 0.765 | |
SE_RX_N | Default | d | 0.521 | |
SE_RX_P | Default | d | 0.520 | |
SMBUS_3V3_BATT_SCL | Default | d | 0.935 | |
SMBUS_3V3_BATT_SDA | Default | d | 0.937 | |
SMBUS_5_OE | Default | d | OL | |
SMBUS_PCH_CLK | Default | d | 0.803 | |
SMBUS_PCH_DATA | Default | d | 0.802 | |
SMCRST_TIEOFF | Default | d | 0.721 | |
SMC_BMON_ISENSE | Default | d | 0.811 | |
SMC_CALPE_ISENSE | Default | d | 0.813 | |
SMC_CPU_HS_ISENSE | Default | d | 0.808 | |
SMC_DCIN_ISENSE | Default | d | 0.812 | |
SMC_DCIN_VSENSE | Default | d | 0.806 | |
SMC_DEBUGPRT_RX | Default | d | 0.470 | |
SMC_DEBUGPRT_R_RX | Default | d | 0.470 | |
SMC_DEBUGPRT_R_TX | Default | d | 0.469 | |
SMC_DEBUGPRT_TX | Default | d | 0.470 | |
SMC_FAN_0_PWM | Default | d | 0.476 | |
SMC_FAN_0_TACH | Default | d | 0.474 | |
SMC_LID_LEFT | Default | d | 0.460 | |
SMC_LID_RIGHT | Default | d | 0.460 | |
SMC_PBUS_VSENSE | Default | d | 0.807 | |
SMC_PCH_PWROK | Default | d | 0.444 | |
SMC_PCH_SYS_PWROK | Default | d | 0.447 | |
SMC_PECI_RX | Default | d | 0.450 | |
SMC_PECI_TX | Default | d | 0.463 | |
SMC_PECI_TX_R | Default | d | 0.463 | |
SMC_PP1V8_WLANBT_ISENSE | Default | d | 0.813 | |
SMC_PP3V3_WLANBT_ISENSE | Default | d | 0.813 | |
SMC_PROCHOT_L | Default | d | 0.463 | |
SMC_RSMRST_L | Default | d | 0.449 | |
SMC_SYSRST_L | Default | d | 0.447 | |
SML_PCH_0_CLK | Default | d | 0.796 | |
SML_PCH_0_DATA | Default | d | 0.798 | |
SML_PCH_1_CLK | Default | d | 0.507 | |
SML_PCH_1_DATA | Default | d | 0.819 | |
SOC_CLKREQ_L | Default | d | 0.816 | |
SOC_CLKREQ_R_L | Default | d | 0.468 | |
SOC_COLD_RESET_L | Default | d | 0.475 | |
SOC_DDR0_RREF | Default | d | 0.530 | |
SOC_DDR0_ZQ | Default | d | 0.407 | |
SOC_DDR1_RREF | Default | d | 0.526 | |
SOC_DDR2_RREF | Default | d | 0.522 | |
SOC_DDR3_ZQ | Default | d | 0.587 | |
SOC_DEBUGPRT_RX | Default | d | 0.476 | |
SOC_DEBUGPRT_TX | Default | d | 0.476 | |
SOC_DFU_STATUS | Default | d | 0.477 | |
SOC_DOCK_CONNECT | Default | d | 0.473 | |
SOC_FORCE_DFU | Default | d | 0.479 | |
SOC_HOLD_RESET | Default | d | 0.475 | |
SOC_JTAG_SEL | Default | d | 0.469 | |
SOC_KBD_BKLT_PWM | Default | d | 0.465 | |
SOC_KBD_BKLT_PWM_R | Default | d | 0.466 | |
SOC_MIPI0C_REXT | Default | d | 0.815 | |
SOC_MIPI1C_REXT | Default | d | 0.397 | |
SOC_MIPID_REXT | Default | d | 0.774 | |
SOC_PCIE_DN_REXT | Default | d | 0.785 | |
SOC_PCIE_STG0_REXT | Default | d | 0.790 | |
SOC_PCIE_STG1_REXT | Default | d | 0.792 | |
SOC_PCIE_UP_REXT | Default | d | 0.786 | |
SOC_PERST_L | Default | d | 0.463 | |
SOC_SOCHOT_L | Default | d | 0.476 | |
SOC_SWD_MUX_SEL_PCH | Default | d | 0.550 | |
SOC_TESTMODE | Default | d | 0.467 | |
SOC_USB_REXT | Default | d | 0.204 | |
SOC_USB_VBUS | Default | d | 0.401 | |
SOC_WDOG | Default | d | 0.472 | |
SOC_XTAL24M_IN | Default | d | 0.820 | |
SOC_XTAL24M_OUT | Default | d | 0.807 | |
SOC_XTAL24M_OUT_R | Default | d | 0.807 | |
SPARE_UPC_XA_DBG0_R | Default | d | 0.706 | |
SPARE_UPC_XA_DBG1_R | Default | d | 0.699 | |
SPARE_UPC_XA_DBG2_R | Default | d | 0.701 | |
SPARE_UPC_XA_DBG3_R | Default | d | 0.701 | |
SPARE_UPC_XA_USB3_RN | Default | d | 0.733 | |
SPARE_UPC_XA_USB3_RP | Default | d | 0.727 | |
SPARE_UPC_XB_USB2_RN | Default | d | 0.729 | |
SPARE_UPC_XB_USB2_RP | Default | d | 0.702 | |
SPARE_UPC_XB_USB3_RN | Default | d | 0.729 | |
SPARE_UPC_XB_USB3_RP | Default | d | 0.728 | |
SPIROM_USE_MLB | Default | d | 0.815 | |
SPI_ACCEL_CS_L | Default | d | 0.470 | |
SPI_AOP_SENSOR_MISO | Default | d | 0.471 | |
SPI_AOP_SENSOR_MISO_R | Default | d | 0.490 | |
SPI_DFR_CLK | Default | d | 0.491 | |
SPI_DFR_CS_L | Default | d | 0.470 | |
SPI_DFR_MISO | Default | d | 0.471 | |
SPI_DFR_MISO_R | Default | d | 0.491 | |
SPI_DFR_MOSI | Default | d | 0.492 | |
SPI_IO2_STRAP_L | Default | d | 0.766 | |
SPI_MESA_CLK | Default | d | 0.495 | |
SPI_MESA_CLK_CONN | Default | d | 0.494 | |
SPI_MESA_MISO | Default | d | 0.472 | |
SPI_MESA_MISO_CONN | Default | d | 0.474 | |
SPI_MESA_MOSI | Default | d | 0.494 | |
SPI_MESA_MOSI_CONN | Default | d | 0.493 | |
SPI_PCHROM_IO<2> | Default | d | 0.799 | |
SPI_PCHROM_IO<3> | Default | d | 0.804 | |
SPI_PCHROM_MOSI | Default | d | 0.814 | |
SPI_SOCROM_CLK | Default | d | 0.490 | |
SPI_SOCROM_CLK_R | Default | d | 0.473 | |
SPI_SOCROM_CS_L | Default | d | 0.474 | |
SPI_SOCROM_MISO | Default | d | 0.427 | |
SPI_SOCROM_MISO_R | Default | d | 0.420 | |
SPI_SOCROM_MOSI | Default | d | 0.430 | |
SPI_SOCROM_MOSI_R | Default | d | 0.435 | |
SPI_SOCROM_WP_L | Default | d | 0.614 | |
SPI_TPAD_3V3_CLK | Default | d | 0.560 | |
SPI_TPAD_3V3_CLK_R | Default | d | 0.550 | |
SPI_TPAD_3V3_CS_L | Default | d | 0.662 | |
SPI_TPAD_3V3_MISO | Default | d | 0.667 | |
SPI_TPAD_3V3_MOSI | Default | d | 0.684 | |
SPI_TPAD_3V3_MOSI_R | Default | d | 0.664 | |
SPI_TPAD_CLK | Default | d | 0.492 | |
SPI_TPAD_CLK_R | Default | d | 0.475 | |
SPI_TPAD_CS_L | Default | d | 0.468 | |
SPI_TPAD_MISO | Default | d | OL | |
SPI_TPAD_MISO_R | Default | d | 0.494 | |
SPKRAMPL_IOUT | Default | d | OL | |
SPKRAMPR_IOUT | Default | d | OL | |
SPKRAMP_FL_AREG | Default | d | 0.583 | |
SPKRAMP_FL_BSTN | Default | d | 0.778 | |
SPKRAMP_FL_BSTP | Default | d | 0.778 | |
SPKRAMP_FL_DREG | Default | d | 0.536 | |
SPKRAMP_FL_MODE | Default | d | 0.408 | |
SPKRAMP_FL_SNSN | Default | d | 0.485 | |
SPKRAMP_FL_SNSP | Default | d | 0.485 | |
SPKRAMP_FR_BSTN | Default | d | 0.776 | |
SPKRAMP_FR_BSTP | Default | d | 0.777 | |
SPKRAMP_FR_MODE | Default | d | 0.470 | |
SPKRAMP_FR_SNSN | Default | d | 0.492 | |
SPKRAMP_FR_SNSP | Default | d | 0.493 | |
SPKRAMP_RESET_L | Default | d | 0.368 | |
SPKRAMP_RL_AREG | Default | d | 0.587 | |
SPKRAMP_RL_BSTN | Default | d | 0.778 | |
SPKRAMP_RL_BSTP | Default | d | 0.778 | |
SPKRAMP_RL_DREG | Default | d | 0.532 | |
SPKRAMP_RL_MODE | Default | d | 0.000 | |
SPKRAMP_RL_SNSN | Default | d | 0.493 | |
SPKRAMP_RL_SNSP | Default | d | 0.506 | |
SPKRAMP_RR_AREG | Default | d | 0.583 | |
SPKRAMP_RR_BSTP | Default | d | 0.778 | |
SPKRAMP_RR_DREG | Default | d | 0.535 | |
SPKRAMP_RR_MODE | Default | d | 0.463 | |
SPKRAMP_RR_SNSN | Default | d | 0.480 | |
SPKRAMP_RR_SNSP | Default | d | 0.486 | |
SPKRAMP_RW_AREG | Default | d | 0.585 | |
SPKRAMP_RW_DREG | Default | d | 0.536 | |
SPKRCONN_FL_OUTN | Default | d | 0.487 | |
SPKRCONN_FL_OUTP | Default | d | 0.492 | |
SPKRCONN_FR_OUTN | Default | d | 0.492 | |
SPKRCONN_FR_OUTP | Default | d | 0.490 | |
SPKRCONN_RL_OUTN | Default | d | 0.497 | |
SPKRCONN_RL_OUTP | Default | d | 0.499 | |
SPKRCONN_RR_OUTN | Default | d | 0.482 | |
SPKRCONN_RR_OUTP | Default | d | 0.483 | |
SPKR_ID0 | Default | d | 0.477 | |
SPKR_ID1 | Default | d | 0.479 | |
SPMI_CLK | Default | d | 0.490 | |
SPMI_CLK_R | Default | d | 0.470 | |
SPMI_DATA | Default | d | 0.400 | |
SPMI_DATA_R | Default | d | 0.414 | |
SSD0_CLK24M | Default | d | 0.435 | |
SSD0_CLK24M_01 | Default | d | 0.436 | |
SSD0_CLK24M_23 | Default | d | 0.447 | |
SSD0_CLK24M_R | Default | d | 0.436 | |
SSD0_CLKREQ0_L | Default | d | 0.455 | |
SSD0_CLKREQ1_L | Default | d | 0.455 | |
SSD0_CLKREQ2_L | Default | d | 0.468 | |
SSD0_CLKREQ3_L | Default | d | 0.456 | |
SSD0_LPB_L | Default | d | 0.438 | |
SSD0_OCARINA_LPB_L | Default | d | 0.439 | |
SSD0_OCARINA_PFN_L | Default | d | 0.442 | |
SSD0_OCARINA_RESET_L | Default | d | 0.435 | |
SSD0_OCARINA_WP_L | Default | d | 0.735 | |
SSD0_PCIE_RESET_L | Default | d | 0.430 | |
SSD0_PMIC_DISCHARGE_EN | Default | d | 0.768 | |
SSD0_PMIC_RESET_L | Default | d | 0.768 | |
SSD0_PMIC_VR_P2V5_EN | Default | d | 0.773 | |
SSD0_RESET_L | Default | d | 0.435 | |
SSD0_S4E0_ANI0_VREF | Default | d | 0.770 | |
SSD0_S4E0_ANI1_VREF | Default | d | 0.770 | |
SSD0_S4E0_DROOP_L | Default | d | 0.489 | |
SSD0_S4E0_JTAG_TDI | Default | d | 0.488 | |
SSD0_S4E0_JTAG_TDO | Default | d | 0.459 | |
SSD0_S4E0_PCIE_RESREF | Default | d | 0.783 | |
SSD0_S4E0_SWD_UID0 | Default | d | 0.481 | |
SSD0_S4E0_SWD_UID1 | Default | d | 0.479 | |
SSD0_S4E0_UART_TX | Default | d | 0.481 | |
SSD0_S4E0_ZQ_C | Default | d | 0.101 | |
SSD0_S4E0_ZQ_L | Default | d | 0.301 | |
SSD0_S4E1_ANI0_VREF | Default | d | 0.781 | |
SSD0_S4E1_ANI1_VREF | Default | d | 0.781 | |
SSD0_S4E1_DROOP_L | Default | d | 0.486 | |
SSD0_S4E1_JTAG_TDO | Default | d | 0.471 | |
SSD0_S4E1_PCIE_RESREF | Default | d | 0.783 | |
SSD0_S4E1_SWD_UID0 | Default | d | 0.481 | |
SSD0_S4E1_SWD_UID1 | Default | d | 0.481 | |
SSD0_S4E1_UART_TX | Default | d | 0.481 | |
SSD0_S4E1_ZQ_C | Default | d | 0.101 | |
SSD0_S4E1_ZQ_L | Default | d | 0.301 | |
SSD0_S4E2_ANI0_VREF | Default | d | 0.790 | |
SSD0_S4E2_ANI1_VREF | Default | d | 0.790 | |
SSD0_S4E2_JATG_TDO | Default | d | 0.477 | |
SSD0_S4E2_PCIE_RESREF | Default | d | 0.794 | |
SSD0_S4E2_SWD_UID0 | Default | d | 0.513 | |
SSD0_S4E2_SWD_UID1 | Default | d | 0.518 | |
SSD0_S4E2_UART_TX | Default | d | 0.519 | |
SSD0_S4E2_ZQ_C | Default | d | 0.101 | |
SSD0_S4E2_ZQ_L | Default | d | 0.305 | |
SSD0_S4E3_ANI0_VREF | Default | d | 0.785 | |
SSD0_S4E3_ANI1_VREF | Default | d | 0.782 | |
SSD0_S4E3_JTAG_TDO | Default | d | 0.488 | |
SSD0_S4E3_PCIE_RESREF | Default | d | 0.786 | |
SSD0_S4E3_SWD_UID0 | Default | d | 0.483 | |
SSD0_S4E3_SWD_UID1 | Default | d | 0.485 | |
SSD0_S4E3_UART_TX | Default | d | 0.484 | |
SSD0_S4E3_ZQ_C | Default | d | 0.101 | |
SSD0_S4E3_ZQ_L | Default | d | 0.301 | |
SSD0_S4E_BOOT2 | Default | d | 0.439 | |
SSD0_S4E_JTAG_SEL | Default | d | 0.441 | |
SSD0_S4E_JTAG_TRST_L | Default | d | 0.438 | |
SSD0_S4E_UART_RX | Default | d | 0.440 | |
SSD0_S4E_UART_TX | Default | d | 0.483 | |
SSD0_STG01_ADDR | Default | d | 0.582 | |
SSD0_SWCLK | Default | d | 0.431 | |
SSD0_SWCLK_R | Default | d | OL | |
SSD0_SWDIO | Default | d | 0.430 | |
SSD0_VR_P2V5_EN | Default | d | 0.647 | |
SSD0_VR_P2V5_PGOOD | Default | d | 0.575 | |
SSD0_WP_L | Default | d | 0.732 | |
SSDNAND_IOUT | Default | d | OL | |
SSD_BFH | Default | d | 0.430 | |
SSD_PMU_RESET_L | Default | d | 0.474 | |
SWD_SOC_DEBUG_SWCLK | Default | d | 0.505 | |
SWD_SOC_DEBUG_SWDIO | Default | d | 0.498 | |
SWD_SOC_SWCLK | Default | d | 0.471 | |
SWD_SOC_SWCLK_XB | Default | d | 0.505 | |
SWD_SOC_SWDIO | Default | d | 0.471 | |
SWD_SOC_SWDIO_XB | Default | d | 0.506 | |
SYS_DETECT | Default | d | OL | |
SYS_DETECT_L | Default | d | 0.482 | |
TBTTHMSNS_D1_N | Default | d | 0.000 | |
TBTTHMSNS_D1_P | Default | d | 0.649 | |
TBTXP3V3_IOUT | Default | d | OL | |
TBT_POC_RESET | Default | d | 0.313 | |
TBT_PWR_EN | Default | d | 0.569 | |
TBT_T_PLUG_EVENT_L | Default | d | 0.812 | |
TBT_WAKE_3V3_L | Default | d | 0.582 | |
TBT_WAKE_L | Default | d | 0.472 | |
TBT_XA_USB2_MXCTL | Default | d | 0.589 | |
TBT_XA_USB2_RBIAS | Default | d | 0.202 | |
TBT_XB_USB2_RBIAS | Default | d | 0.203 | |
TBT_X_BATLOW_L | Default | d | 0.591 | |
TBT_X_CIO_PWR_EN | Default | d | 0.541 | |
TBT_X_CLKREQ_L | Default | d | 0.807 | |
TBT_X_CLKREQ_R_L | Default | d | 0.588 | |
TBT_X_HDMI_DDC_DATA | Default | d | 0.589 | |
TBT_X_PCIE_BIAS | Default | d | 0.791 | |
TBT_X_PCI_RESET_L | Default | d | 0.551 | |
TBT_X_PLUG_EVENT_L | Default | d | 0.585 | |
TBT_X_PWR_EN_1V8 | Default | d | 0.570 | |
TBT_X_RBIAS | Default | d | 0.776 | |
TBT_X_ROM_HOLD_L | Default | d | 0.708 | |
TBT_X_ROM_WP_L | Default | d | 0.584 | |
TBT_X_RSENSE | Default | d | 0.473 | |
TBT_X_RTD3_PWR_EN | Default | d | 0.594 | |
TBT_X_SPI_ARK_CLK | Default | d | OL | |
TBT_X_SPI_CLK | Default | d | 0.563 | |
TBT_X_SPI_CS_L | Default | d | 0.592 | |
TBT_X_SPI_DBG_CLK | Default | d | OL | |
TBT_X_SPI_DBG_CS_L | Default | d | OL | |
TBT_X_SPI_DBG_MISO | Default | d | OL | |
TBT_X_SPI_DBG_MOSI | Default | d | OL | |
TBT_X_SPI_MISO | Default | d | 0.592 | |
TBT_X_SPI_MOSI | Default | d | 0.594 | |
TBT_X_TEST_EN | Default | d | 0.100 | |
TBT_X_TEST_PWR_GOOD | Default | d | 0.101 | |
TBT_X_USB_PWR_EN | Default | d | 0.544 | |
TEST_CPU_A35 | Default | d | 0.291 | |
TEST_CPU_BJ34 | Default | d | 0.309 | |
TEST_CPU_BJ36 | Default | d | 0.309 | |
TEST_CPU_CN36 | Default | d | 0.340 | |
TEST_CPU_D34 | Default | d | 0.294 | |
TEST_CPU_F34 | Default | d | 0.346 | |
TEST_CPU_F37 | Default | d | 0.350 | |
TEST_NOA_N_10 | Default | d | 0.821 | |
TEST_NOA_N_11 | Default | d | 0.822 | |
THMSNSA_ADDR_SEL | Default | d | 0.651 | |
THMSNSA_D2_N | Default | d | 0.000 | |
THMSNSA_D2_P | Default | d | 0.651 | |
THMSNSA_D3_N | Default | d | 0.000 | |
THMSNSA_D3_P | Default | d | 0.649 | |
THMSNSA_D4_N | Default | d | 0.000 | |
THMSNSA_D4_P | Default | d | 0.651 | |
THMSNSA_DN | Default | d | 0.000 | |
THMSNSB_ADDR_SEL | Default | d | 0.650 | |
THMSNSB_D1_N | Default | d | 0.000 | |
THMSNSB_D1_P | Default | d | 0.653 | |
THMSNSB_D2_N | Default | d | 0.000 | |
THMSNSB_D2_N | Default | r | 1.200R | |
THMSNSB_D2_P | Default | d | 0.648 | |
THMSNSB_D3_N | Default | d | 0.002 | |
THMSNSB_D3_N | Default | r | 1.700R | |
THMSNSB_D3_P | Default | d | 0.648 | |
THMSNSB_D4_N | Default | d | 0.000 | |
THMSNSB_D4_P | Default | d | 0.649 | |
THMSNSB_DN | Default | d | 0.000 | |
TPADP3V3_IOUT | Default | d | OL | |
TPADP5V_IOUT | Default | d | OL | |
TPAD_3V3_ACTUATOR_DISABLE_L | Default | d | 0.919 | |
TPAD_3V3_SPI_EN | Default | d | 0.590 | |
TPAD_3V3_SPI_INT_L | Default | d | 0.928 | |
TPAD_ACTUATOR_DISABLE_L | Default | d | 0.470 | |
TPAD_KBD_WAKE_L | Default | d | 0.470 | |
TPAD_SPI_EN | Default | d | 0.467 | |
TPAD_SPI_INT_L | Default | d | 0.472 | |
TPS62180_FB | Default | d | 1.530 | |
TPS62180_FB_R | Default | d | 0.426 | |
TP_CPU_PWRGD | Default | d | 0.338 | |
TP_DFR_TOUCH_GPIO2 | Default | d | OL | |
TP_DFR_TOUCH_PANEL_DETECT | Default | d | OL | |
TP_DFR_TOUCH_ROM_WC | Default | d | OL | |
TP_FAN_RT_OTP1 | Default | d | OL | |
TP_FAN_RT_OTP2 | Default | d | OL | |
TP_JTAG_SOC_TRST_L | Default | d | 0.472 | |
TP_LCD_IRQ_L | Default | d | OL | |
TP_P3V3G3H_EN2 | Default | d | 0.593 | |
TP_SMC_FIXTURE_MODE_L | Default | d | 0.470 | |
TP_SPI_PCHROM_CLK | Default | d | 0.817 | |
TP_SPI_PCHROM_CS_L | Default | d | 0.803 | |
TP_USBC_PP20V_XA | Default | d | 0.000 | |
TP_USBC_PP20V_XB | Default | d | 0.000 | |
TP_USB_FIXT2_N | Default | d | 0.475 | |
TP_USB_FIXT2_P | Default | d | 0.468 | |
TP_WLAN_JTAG_SEL | Default | d | 0.554 | |
TP_WLAN_JTAG_TCK | Default | d | 0.570 | |
TP_WLAN_JTAG_TDI | Default | d | 0.561 | |
TP_WLAN_JTAG_TDO | Default | d | 0.563 | |
TP_WLAN_JTAG_TRST_L | Default | d | 0.562 | |
UART_BT_LH_D2R | Default | d | 0.468 | |
UART_BT_LH_R2D | Default | d | 0.469 | |
UART_SE_D2R | Default | d | 0.465 | |
UART_SE_D2R_CTS_L | Default | d | 0.464 | |
UART_SE_R2D | Default | d | 0.452 | |
UART_SE_R2D_RTS_L | Default | d | 0.450 | |
UART_WLAN_D2R | Default | d | 0.467 | |
UART_WLAN_D2R_CTS_L | Default | d | 0.467 | |
UART_WLAN_R2D | Default | d | 0.467 | |
UART_WLAN_R2D_RTS_L | Default | d | 0.467 | |
UPC_I2C_INT_L | Default | d | 0.466 | |
UPC_PMU_RESET | Default | d | 0.640 | |
UPC_XA_FAULT_L | Default | d | 0.662 | |
UPC_XA_FAULT_L_R | Default | d | 0.677 | |
UPC_XA_RESET | Default | d | 0.004 | |
UPC_XA_RESET | Default | r | 1.000R | |
UPC_XA_R_OSC | Default | d | 0.471 | |
UPC_XA_SER_DBG | Default | d | OL | |
UPC_XA_SS | Default | d | 0.582 | |
UPC_XA_SWD_CLK | Default | d | 0.597 | |
UPC_XA_SWD_DATA | Default | d | 0.706 | |
UPC_XA_UART_RX | Default | d | 0.552 | |
UPC_XA_UART_TX | Default | d | 0.552 | |
UPC_XA_VDDIO_CFG | Default | d | 0.341 | |
UPC_XB_FAULT_L | Default | d | 0.670 | |
UPC_XB_FAULT_L_R | Default | d | 0.674 | |
UPC_XB_RESET | Default | d | 0.003 | |
UPC_XB_RESET | Default | r | 0.500R | |
UPC_XB_R_OSC | Default | d | 0.465 | |
UPC_XB_SER_DBG | Default | d | 0.679 | |
UPC_XB_SPI_CLK | Default | d | 0.577 | |
UPC_XB_SPI_CS_L | Default | d | 0.606 | |
UPC_XB_SPI_MISO | Default | d | 0.606 | |
UPC_XB_SPI_MOSI | Default | d | 0.608 | |
UPC_XB_SWD_DATA | Default | d | 0.712 | |
UPC_XB_VDDIO_CFG | Default | d | 0.580 | |
UPC_X_SPI_CS_L | Default | d | 0.583 | |
USB2_UPC_PCH_XA_F_N | Default | d | 0.474 | |
USB2_UPC_PCH_XA_F_P | Default | d | 0.474 | |
USB2_UPC_PCH_XA_N | Default | d | 0.474 | |
USB2_UPC_PCH_XA_P | Default | d | 0.474 | |
USB2_UPC_PCH_XB_F_N | Default | d | 0.475 | |
USB2_UPC_PCH_XB_F_P | Default | d | 0.475 | |
USB2_UPC_PCH_XB_N | Default | d | 0.475 | |
USB2_UPC_PCH_XB_P | Default | d | 0.475 | |
USB3_BSSB_D2R_N | Default | d | 0.349 | |
USB3_BSSB_D2R_P | Default | d | 0.348 | |
USB3_BSSB_D2R_R_N | Default | d | 0.349 | |
USB3_BSSB_D2R_R_P | Default | d | 0.348 | |
USB3_BSSB_R2D_C_N | Default | d | 0.334 | |
USB3_BSSB_R2D_C_P | Default | d | 0.335 | |
USB3_BSSB_R2D_N | Default | d | 0.705 | |
USB3_BSSB_R2D_P | Default | d | 0.703 | |
USBC_XA_CC1 | Default | d | 0.590 | |
USBC_XA_CC2 | Default | d | 0.579 | |
USBC_XA_D2R_CR_N<1> | Default | d | 0.000 | |
USBC_XA_D2R_CR_N<2> | Default | d | 0.000 | |
USBC_XA_D2R_CR_P<1> | Default | d | 0.000 | |
USBC_XA_D2R_CR_P<2> | Default | d | 0.000 | |
USBC_XA_R2D_N<1> | Default | d | 0.000 | |
USBC_XA_R2D_N<2> | Default | d | 0.000 | |
USBC_XA_R2D_P<1> | Default | d | 0.000 | |
USBC_XA_R2D_P<2> | Default | d | 0.000 | |
USBC_XA_SBU1 | Default | d | 0.661 | |
USBC_XA_SBU2 | Default | d | 0.655 | |
USBC_XA_USB_BOT_N | Default | d | 0.759 | |
USBC_XA_USB_BOT_P | Default | d | 0.762 | |
USBC_XA_USB_TOP_N | Default | d | 0.762 | |
USBC_XA_USB_TOP_P | Default | d | 0.762 | |
USBC_XB_CC1 | Default | d | 0.582 | |
USBC_XB_CC2 | Default | d | 0.582 | |
USBC_XB_D2R_CR_N<1> | Default | d | 0.000 | |
USBC_XB_D2R_CR_N<2> | Default | d | 0.000 | |
USBC_XB_D2R_CR_P<1> | Default | d | 0.000 | |
USBC_XB_D2R_CR_P<2> | Default | d | 0.000 | |
USBC_XB_R2D_N<1> | Default | d | 0.000 | |
USBC_XB_R2D_N<2> | Default | d | 0.000 | |
USBC_XB_R2D_P<1> | Default | d | 0.000 | |
USBC_XB_R2D_P<2> | Default | d | 0.000 | |
USBC_XB_SBU1 | Default | d | 0.655 | |
USBC_XB_SBU2 | Default | d | 0.655 | |
USBC_XB_USB_BOT_N | Default | d | 0.757 | |
USBC_XB_USB_BOT_P | Default | d | 0.756 | |
USBC_XB_USB_TOP_N | Default | d | 0.740 | |
USBC_XB_USB_TOP_P | Default | d | 0.760 | |
USBC_X_RESET_L | Default | d | 0.661 | |
USB_EXTA_N | Default | d | 0.471 | |
USB_EXTA_P | Default | d | 0.468 | |
USB_SOC_DEBUG_N | Default | d | OL | |
USB_SOC_DEBUG_P | Default | d | OL | |
USB_SOC_N | Default | d | 0.714 | |
USB_SOC_P | Default | d | 0.715 | |
USB_SOC_TYPEC_N | Default | d | 0.717 | |
USB_SOC_TYPEC_P | Default | d | 0.715 | |
UVP_DIS_L | Default | d | 0.567 | |
VR0V9_IND_TBT_X | Default | d | 0.282 | |
WC_L | Default | d | 0.740 | |
WLANBTP1V8_IOUT | Default | d | OL | |
WLANBTP3V3_IOUT | Default | d | OL | |
WLAN_AUDIO_SYNC | Default | d | 0.470 | |
WLAN_OP_EN | Default | d | OL | |
WLAN_OP_EN_L | Default | d | OL | |
WLAN_PWR_EN | Default | d | 0.764 | |
WLAN_SROM_CLK | Default | d | 0.632 | |
WLAN_SROM_CS | Default | d | 0.704 | |
WLAN_SROM_CS_R | Default | d | 0.607 | |
WLAN_SROM_DIN | Default | d | 0.565 | |
WLAN_SROM_DOUT | Default | d | 0.636 | |
WLAN_SROM_ORG | Default | d | 0.705 | |
WLAN_THROTTLE | Default | d | 0.463 | |
WLBT_HOST_WAKE | Default | d | 0.464 | |
XDP_BPM_L<0> | Default | d | 0.291 | |
XDP_CPU_PRDY_L | Default | d | 0.255 | |
XDP_CPU_PREQ_L | Default | d | 0.269 | |
XDP_CPU_PWRBTN_L | Default | d | 0.773 | |
XDP_CPU_TCK | Default | d | 0.052 | |
XDP_CPU_TCK | Default | r | 51.800R | |
XDP_CPU_TDI | Default | d | 0.239 | |
XDP_CPU_TDO | Default | d | 0.229 | |
XDP_CPU_TMS | Default | d | 0.239 | |
XDP_CPU_TRST_L | Default | d | 0.284 | |
XDP_DBRESET_L | Default | d | 0.810 | |
XDP_DP_INT_HPD | Default | d | 0.530 | |
XDP_PCH_OBSDATA_A0 | Default | d | 0.819 | |
XDP_PCH_OBSDATA_A1 | Default | d | 0.820 | |
XDP_PCH_OBSDATA_A2 | Default | d | 0.821 | |
XDP_PCH_OBSDATA_A3 | Default | d | 0.819 | |
XDP_PCH_OBSDATA_B0 | Default | d | 0.819 | |
XDP_PCH_OBSDATA_D1 | Default | d | 0.821 | |
XDP_PCH_OBSDATA_D2 | Default | d | 0.819 | |
XDP_PCH_OBSDATA_D3 | Default | d | 0.818 | |
XDP_PCH_OBSFN_C1 | Default | d | 0.819 | |
XDP_PCH_TCK | Default | d | 0.312 | |
XDP_PCH_TDI | Default | d | 0.240 | |
XDP_PCH_TDO | Default | d | 0.230 | |
XDP_PCH_TMS | Default | d | 0.240 | |
XDP_PCH_TRST_L | Default | d | 0.285 | |
XDP_PM_RSMRST_L | Default | d | 1.509 | |
XDP_PRESENT_CPU | Default | d | 1.291 | |
XDP_PRESENT_L | Default | d | 0.473 | |
XDP_USB_EXTC_OC_L | Default | d | 0.806 | |
XDP_USB_EXTD_OC_L | Default | d | 0.807 | |