Netname | Condition | Type | Value | Comment |
ACT_GND | Default | d | 0.000 | |
AGND_P2V5_NAND0 | Default | d | 0.000 | |
AGND_P5VUSBC23 | Default | d | 0.000 | |
AIRFLOW_C_THMSNS | Default | d | 0.775 | |
AIRFLOW_L_THMSNS | Default | d | 0.770 | |
AIRFLOW_R_THMSNS | Default | d | 0.770 | |
ALS_INT_L | Default | d | 0.305 | |
AMR1_OR_ND_1V8 | Default | d | 0.570 | |
AOP_HDMI_CEC_R | Default | d | 0.300 | |
ATC01_P0V805_DSCHG_EN_RC | Default | d | 0.445 | |
ATC01_P0V805_VR_EN_R | Default | d | 0.560 | |
ATC01_P0V855_DSCHG_EN_RC | Default | d | 0.530 | |
ATC01_P0V855_VR_EN_R | Default | d | 0.560 | |
ATC01_P1V2_DSCHG_EN_RC | Default | d | 0.445 | |
ATC01_P1V2_VR_EN_R | Default | d | 0.560 | |
ATC01_VDDCIO_VR_EN | Default | d | 0.560 | |
ATC01_VDDCIO_VR_EN_R | Default | d | 0.560 | |
ATC01_VDDFIXED_VR_EN | Default | d | 0.560 | |
ATC01_VDDFIXED_VR_EN_R | Default | d | 0.560 | |
ATC01_VDDIO_VR_EN | Default | d | 0.560 | |
ATC01_VDDIO_VR_EN_R | Default | d | 0.560 | |
ATC0_24M_O_R | Default | d | 1.350 | |
ATC1_24M_O_R | Default | d | 1.345 | |
ATC2_24M_O_R | Default | d | 1.345 | |
ATC2_P0V805_DSCHG_EN_RC | Default | d | 0.520 | |
ATC2_P0V805_VR_EN_R | Default | d | 0.560 | |
ATC2_P0V855_DSCHG_EN_RC | Default | d | 0.510 | |
ATC2_P0V855_VR_EN_R | Default | d | 0.560 | |
ATC2_P1V2_DSCHG_EN_RC | Default | d | 0.520 | |
ATC2_P1V2_VR_EN_R | Default | d | 0.565 | |
ATC2_VDDCIO_VR_EN | Default | d | 0.560 | |
ATC2_VDDCIO_VR_EN_R | Default | d | 0.560 | |
ATC2_VDDFIXED_VR_EN | Default | d | 0.570 | |
ATC2_VDDFIXED_VR_EN_R | Default | d | 0.560 | |
ATC2_VDDIO_VR_EN | Default | d | 0.565 | |
ATC2_VDDIO_VR_EN_R | Default | d | 0.565 | |
ATCRTMR0_CFP_RCAL_NEG | Default | d | 0.415 | |
ATCRTMR0_CFP_RCAL_POS | Default | d | 0.545 | |
ATCRTMR0_COLD_RESET_L | Default | d | 0.335 | |
ATCRTMR0_FORCE_DFU | Default | d | 0.335 | |
ATCRTMR0_JTAGL_SEL | Default | d | 0.330 | |
ATCRTMR0_JTAG_TDO | Default | d | 0.330 | |
ATCRTMR0_LSTX_DIR | Default | d | 0.335 | |
ATCRTMR0_RESET_1V2_1V8_MCW_L | Default | d | -0.335 | |
ATCRTMR0_RESET_1V2_L | Default | d | 0.335 | |
ATCRTMR0_RESET_INV | Default | d | 0.615 | |
ATCRTMR0_RESET_L | Default | d | 0.660 | |
ATCRTMR0_SFP_RCAL_NEG | Default | d | 0.410 | |
ATCRTMR0_SFP_RCAL_POS | Default | d | 0.545 | |
ATCRTMR0_TESTMODE | Default | d | 0.330 | |
ATCRTMR0_XTAL24M_IN | Default | d | 0.845 | |
ATCRTMR0_XTAL24M_OUT | Default | d | 0.845 | |
ATCRTMR1_CFP_RCAL_NEG | Default | d | 0.400 | |
ATCRTMR1_CFP_RCAL_POS | Default | d | 0.530 | |
ATCRTMR1_COLD_RESET_L | Default | d | 0.320 | |
ATCRTMR1_FORCE_DFU | Default | d | 0.325 | |
ATCRTMR1_JTAGL_SEL | Default | d | 0.330 | |
ATCRTMR1_JTAG_TDO | Default | d | 0.330 | |
ATCRTMR1_LSTX_DIR | Default | d | 0.325 | |
ATCRTMR1_RESET_1V2_L | Default | d | 0.325 | |
ATCRTMR1_RESET_INV | Default | d | 0.620 | |
ATCRTMR1_RESET_L | Default | d | 0.660 | |
ATCRTMR1_SFP_RCAL_NEG | Default | d | 0.400 | |
ATCRTMR1_SFP_RCAL_POS | Default | d | 0.530 | |
ATCRTMR1_TESTMODE | Default | d | 0.330 | |
ATCRTMR1_XTAL24M_IN | Default | d | 0.845 | |
ATCRTMR1_XTAL24M_OUT | Default | d | 0.845 | |
ATCRTMR2_BOOT_CONFIG0 | Default | d | 0.330 | |
ATCRTMR2_BOOT_CONFIG1 | Default | d | 0.330 | |
ATCRTMR2_BOOT_CONFIG2 | Default | d | 0.330 | |
ATCRTMR2_CFP_RCAL_NEG | Default | d | 0.405 | |
ATCRTMR2_CFP_RCAL_POS | Default | d | 0.535 | |
ATCRTMR2_CFSB | Default | d | 0.330 | |
ATCRTMR2_CHIPID_0 | Default | d | 0.330 | |
ATCRTMR2_CHIPID_1 | Default | d | 0.330 | |
ATCRTMR2_COLD_RESET_L | Default | d | 0.330 | |
ATCRTMR2_FORCE_DFU | Default | d | 0.330 | |
ATCRTMR2_JTAGL_SEL | Default | d | 0.335 | |
ATCRTMR2_JTAG_TDO | Default | d | 0.335 | |
ATCRTMR2_LSTX_DIR | Default | d | 0.330 | |
ATCRTMR2_RESET_1V2_L | Default | d | 0.330 | |
ATCRTMR2_RESET_INV | Default | d | 0.660 | |
ATCRTMR2_RESET_L | Default | d | 0.655 | |
ATCRTMR2_SFP_RCAL_NEG | Default | d | 0.405 | |
ATCRTMR2_SFP_RCAL_POS | Default | d | 0.530 | |
ATCRTMR2_TESTMODE | Default | d | 0.335 | |
ATCRTMR2_XTAL24M_IN | Default | d | 0.845 | |
ATCRTMR2_XTAL24M_OUT | Default | d | 0.845 | |
ATCRTMR_ACTIVE_READY_3V3 | Default | d | 0.460 | |
AUDIO_JACK_CH_GND | Default | d | 0.000 | |
AUDIO_JACK_CH_MIC | Default | d | 0.645 | |
AUDIO_JACK_GB_GND | Default | d | 0.000 | |
AUDIO_JACK_GB_MIC | Default | d | 0.645 | |
AUDIO_JACK_LEFT_OUT | Default | d | 0.830 | |
AUDIO_JACK_LEFT_SNS | Default | d | 1.180 | |
AUDIO_JACK_RIGHT_OUT | Default | d | 0.830 | |
AUDIO_JACK_RIGHT_SNS | Default | d | 2.300 | |
AUDIO_JACK_RING_SNS | Default | d | 0.645 | |
AUDIO_JACK_TIP_SNS | Default | d | 1.675 | |
AUD_CONN_HP_LEFT | Default | d | 0.830 | |
AUD_CONN_HP_RIGHT | Default | d | 0.830 | |
AUD_CONN_HP_SENSE_L | Default | d | 1.180 | |
AUD_CONN_HP_SENSE_R | Default | d | 2.300 | |
AUD_CONN_RING2 | Default | d | 0.000 | |
AUD_CONN_RING2_XW | Default | d | 0.645 | |
AUD_CONN_RING_SENSE | Default | d | OL | |
AUD_CONN_SLEEVE | Default | d | 0.000 | |
AUD_CONN_SLEEVE_XW | Default | d | 0.645 | |
AUD_CONN_TIP_SENSE | Default | d | OL | |
BKLT_BOOST_THROTTLE_CONN_L | Default | d | 0.625 | |
BKLT_BOOST_THROTTLE_L | Default | d | 0.310 | |
BKLT_BOOST_THROTTLE_LUXE_L | Default | d | 0.625 | |
BKLT_BOOST_THROTTLE_R_L | Default | d | 0.625 | |
BKLT_HS_IOUT | Default | d | 0.720 | |
BKLT_HS_ISENSE | Default | d | 0.730 | |
BL_PMIC_PWR_EN | Default | d | 0.760 | |
BL_PWR_EN | Default | d | 0.405 | |
BL_PWR_EN_R | Default | d | 0.405 | |
BMON_ISENSE | Default | d | 0.730 | |
BOARD_ID0 | Default | d | 0.305 | |
BOARD_ID1 | Default | d | 0.300 | |
BOARD_ID2 | Default | d | 0.300 | |
BOARD_ID3 | Default | d | 0.305 | |
BOARD_ID4 | Default | d | 0.300 | |
BOARD_ID5 | Default | d | 0.305 | |
BOARD_REV0 | Default | d | 0.290 | |
BOARD_REV1 | Default | d | 0.290 | |
BOARD_REV2 | Default | d | 0.300 | |
BOARD_REV3 | Default | d | 0.295 | |
BOOT_CONFIG0 | Default | d | 0.310 | |
BOOT_CONFIG1 | Default | d | 0.310 | |
BOOT_CONFIG2 | Default | d | 0.305 | |
BT_LHL_GPIO2 | Default | d | 0.620 | |
BT_TIME_SYNC | Default | d | 0.310 | |
CAPSLOCK_LED_EN | Default | d | 0.570 | |
CEC_FLT | Default | d | 0.540 | |
CEC_FLT_PULL | Default | d | 0.780 | |
CEC_FLT_R | Default | d | 0.550 | |
CEC_PFET_GATE_R | Default | d | OL | |
CHGR_AMON | Default | d | 0.625 | |
CHGR_AUX_DET | Default | d | 0.465 | |
CHGR_AUX_DET_3V3 | Default | d | 0.600 | |
CHGR_AUX_OK | Default | d | 0.620 | |
CHGR_BGATE | Default | d | 0.690 | |
CHGR_BMON | Default | d | 0.625 | |
CHGR_BOOT1 | Default | d | 0.590 | |
CHGR_BOOT1_RC | Default | d | 0.590 | |
CHGR_BOOT2 | Default | d | 0.590 | |
CHGR_BOOT2_RC | Default | d | 0.595 | |
CHGR_COMP | Default | d | 0.625 | |
CHGR_CSI_FILT_N | Default | d | 0.570 | |
CHGR_CSI_FILT_P | Default | d | 0.570 | |
CHGR_CSI_N | Default | d | 0.570 | |
CHGR_CSI_P | Default | d | 0.570 | |
CHGR_CSO_FILT_N | Default | d | 0.490 | |
CHGR_CSO_FILT_P | Default | d | 0.490 | |
CHGR_CSO_N | Default | d | 0.490 | |
CHGR_CSO_P | Default | d | 0.490 | |
CHGR_EN_MVR | Default | d | 0.620 | |
CHGR_EN_MVR_1V8 | Default | d | 0.690 | |
CHGR_EN_MVR_A | Default | d | OL | |
CHGR_EN_MVR_DLY | Default | d | 0.710 | |
CHGR_GATE_Q1 | Default | d | 0.865 | |
CHGR_GATE_Q1_R | Default | d | 0.860 | |
CHGR_GATE_Q2 | Default | d | 0.465 | |
CHGR_GATE_Q2_R | Default | d | 0.435 | |
CHGR_GATE_Q3 | Default | d | 0.480 | |
CHGR_GATE_Q3_R | Default | d | 0.460 | |
CHGR_GATE_Q4 | Default | d | 0.895 | |
CHGR_GATE_Q4_R | Default | d | 0.890 | |
CHGR_INT_1V8_L | Default | d | 0.605 | |
CHGR_LDSW_EN | Default | d | 0.675 | |
CHGR_LX1 | Default | d | 0.430 | |
CHGR_LX2 | Default | d | 0.430 | |
CHGR_PHASE1 | Default | d | 0.430 | |
CHGR_PHASE2 | Default | d | 0.430 | |
CHGR_RST_IN | Default | d | 0.610 | |
CHGR_SNB1 | Default | d | OL | |
CHGR_SNB2 | Default | d | OL | |
CHGR_THMSNS | Default | d | 0.770 | |
CHGR_VBAT | Default | d | 0.695 | |
CHGR_VBAT_XW | Default | d | 1.620 | |
CIO_ATC2_LSRX | Default | d | 0.295 | |
CIO_ATC2_LSTX | Default | d | 0.295 | |
COBRA_SPI_GNT | Default | d | 0.750 | |
COBRA_SPI_WR_PROT | Default | d | 0.590 | |
COBRA_TEST_MODE_L | Default | d | 0.610 | |
COBRA_XIN | Default | d | 0.760 | |
COBRA_XIN_R_R | Default | d | 0.760 | |
COBRA_XOUT | Default | d | 0.755 | |
COBRA_XOUT_R_L | Default | d | 1.755 | |
CODEC_AGND | Default | d | 0.000 | |
CODEC_CP_LDO_FILT | Default | d | 0.610 | |
CODEC_FILT | Default | d | 0.800 | |
CODEC_FLY1M | Default | d | 0.430 | |
CODEC_FLY1P | Default | d | 0.380 | |
CODEC_FLY2M | Default | d | 1.365 | |
CODEC_FLY2P | Default | d | 0.390 | |
CODEC_HSBIAS_FILT | Default | d | 0.715 | |
CODEC_HSBIAS_FILT_REF | Default | d | 0.645 | |
CODEC_INT_L | Default | d | 0.305 | |
CODEC_RESET_L | Default | d | 0.305 | |
CODEC_VCP_FILTM | Default | d | 1.045 | |
CODEC_VCP_FILTP | Default | d | 0.560 | |
CODEC_VCP_FILT_GND | Default | d | 0.000 | |
CODEC_WAKE_L | Default | d | 0.710 | |
DBGLED_LCH | Default | d | OL | |
DBGLED_RETURN | Default | d | OL | |
DBGLED_RTN | Default | d | OL | |
DBL_CLICK_DET | Default | d | 0.305 | |
DEBUG_SPMU_GPIO16 | Default | d | 0.755 | |
DFUMUX_SEL | Default | d | OL | |
DISP_2DBL_FSYNC | Default | d | 0.310 | |
DISP_BKLT_LSYNC | Default | d | 0.305 | |
DMIC_DISABLE_L | Default | d | 0.300 | |
DMIC_DISABLE_WARN_L | Default | d | 0.300 | |
DP2HDMI_1.5G_FILT_EN | Default | d | 0.610 | |
DP2HDMI_CEXT | Default | d | 0.535 | |
DP2HDMI_PWR_EN | Default | d | OL | |
DP2HDMI_PWR_EN_PMU | Default | d | 0.645 | |
DP2HDMI_PWR_EN_R | Default | d | OL | |
DP2HDMI_PW_EN_DSCHG_R | Default | d | OL | |
DP2HDMI_RESET_R_L | Default | d | 0.655 | |
DP2HDMI_REXT | Default | d | 0.580 | |
DPRX_AUX_N | Default | d | 0.055 | |
DPRX_AUX_N | Default | r | 55.400R | |
DPRX_AUX_P | Default | d | 0.055 | |
DPRX_AUX_P | Default | r | 55.500R | |
DPRX_INT_HPD | Default | d | 0.300 | |
EDP_BKLT_1V29_EN | Default | d | 0.690 | |
EDP_PANEL_1V8_EN | Default | d | 0.670 | |
EDP_PANEL_DISCHARGE | Default | d | 0.685 | |
EDP_PANEL_PWR_EN | Default | d | 0.540 | |
EUSB_ATC0_DBG_N | Default | d | 0.320 | |
EUSB_ATC0_DBG_P | Default | d | 0.315 | |
EUSB_ATC0_N | Default | d | 0.320 | |
EUSB_ATC0_P | Default | d | 0.320 | |
EUSB_ATC1_DBG_N | Default | d | 0.450 | |
EUSB_ATC1_DBG_P | Default | d | 0.450 | |
EUSB_ATC1_N | Default | d | 0.320 | |
EUSB_ATC1_P | Default | d | 0.320 | |
EUSB_ATC2_N | Default | d | 0.320 | |
EUSB_ATC2_P | Default | d | 0.320 | |
EUSB_VBUS_DETECT | Default | d | 0.240 | |
FAN_0_PWM_5V | Default | d | 0.735 | |
FAN_0_TACH | Default | d | 0.325 | |
FAN_1_PWM_5V | Default | d | 0.730 | |
FAN_1_TACH | Default | d | 0.320 | |
FB_BLKT_2D | Default | d | 0.720 | |
FINSTACK_L_THMSNS | Default | d | 0.775 | |
FINSTACK_R_THMSNS | Default | d | 0.775 | |
FTCAM_ENABLE_1V8_OUT | Default | d | 0.460 | |
FTCAM_RESET_1V8_R_L | Default | d | 0.460 | |
FTCAM_RESET_L | Default | d | 0.300 | |
GND_KBDBKLT_SGND | Default | d | 0.000 | |
GND_P3V3SD_AGND | Default | d | 0.000 | |
GYRO_INT | Default | d | 0.300 | |
GYRO_MOTION_INT | Default | d | 0.300 | |
HDMI_5V_FAULT | Default | d | 0.580 | |
HDMI_5V_ISET | Default | d | 0.550 | |
HDMI_5V_ON | Default | d | 0.580 | |
HDMI_AOP_HPD_R | Default | d | 0.405 | |
HDMI_CEC | Default | d | 0.730 | |
HDMI_CECFET_EN | Default | d | 0.760 | |
HDMI_CECFET_EN_Q | Default | d | 0.495 | |
HDMI_CEC_AOP_RX | Default | d | 0.300 | |
HDMI_CEC_AOP_TX | Default | d | 0.300 | |
HDMI_CEC_CONN | Default | d | 0.545 | |
HDMI_CEC_R | Default | d | 0.730 | |
HDMI_DDC_5V_CONN_SCL | Default | d | 0.715 | |
HDMI_DDC_5V_CONN_SDA | Default | d | 0.715 | |
HDMI_DDC_5V_FLT_SCL | Default | d | 0.715 | |
HDMI_DDC_5V_FLT_SDA | Default | d | 0.715 | |
HDMI_DDC_5V_SCL | Default | d | 0.685 | |
HDMI_DDC_5V_SDA | Default | d | 0.685 | |
HDMI_HPD_AOP | Default | d | 0.305 | |
HDMI_HPD_IN | Default | d | 0.665 | |
HDMI_HPD_IN_CONN | Default | d | 0.670 | |
HDMI_HPD_IN_FLT | Default | d | 0.670 | |
HDMI_HPD_IN_R | Default | d | 0.670 | |
HDMI_PIND_VBIAS | Default | d | OL | |
HDMI_PWR_EN | Default | d | 0.590 | |
HDMI_RSVD | Default | d | 0.000 | |
I2C_ALS_1V8_SCL | Default | d | 0.560 | |
I2C_ALS_1V8_SDA | Default | d | 0.560 | |
I2C_AOP_ALS_SCL | Default | d | 0.300 | |
I2C_AOP_ALS_SDA | Default | d | 0.300 | |
I2C_CAM_1V8_SCL | Default | d | 0.560 | |
I2C_CAM_1V8_SDA | Default | d | 0.560 | |
I2C_CAM_SCL | Default | d | 0.300 | |
I2C_CAM_SDA | Default | d | 0.300 | |
I2C_CODEC_SCL | Default | d | 0.300 | |
I2C_CODEC_SDA | Default | d | 0.305 | |
I2C_HDMI_DEBUG_SCL | Default | d | 0.300 | |
I2C_HDMI_DEBUG_SDA | Default | d | 0.300 | |
I2C_KBD_SCL | Default | d | 0.720 | |
I2C_KBD_SDA | Default | d | 0.690 | |
I2C_LUXE_DEBUG_SCL | Default | d | 0.405 | |
I2C_LUXE_DEBUG_SDA | Default | d | 0.405 | |
I2C_NAND_PMIC_SCL_1V8 | Default | d | 0.530 | |
I2C_NAND_PMIC_SDA_1V8 | Default | d | 0.530 | |
I2C_SD_DEBUG_3V3_SCL | Default | d | 0.560 | |
I2C_SD_DEBUG_3V3_SDA | Default | d | 0.560 | |
I2C_SD_SCL | Default | d | 0.300 | |
I2C_SD_SDA | Default | d | 0.300 | |
I2C_SEEPROM_SCL | Default | d | 0.300 | |
I2C_SEEPROM_SDA | Default | d | 0.300 | |
I2C_SMC_IPD_SCL | Default | d | 0.300 | |
I2C_SMC_IPD_SDA | Default | d | 0.300 | |
I2C_SMC_NAND_SCL | Default | d | 0.300 | |
I2C_SMC_NAND_SDA | Default | d | 0.300 | |
I2C_SMC_PWR_1V8_SCL | Default | d | 0.530 | |
I2C_SMC_PWR_1V8_SDA | Default | d | 0.525 | |
I2C_SMC_PWR_SCL | Default | d | 0.300 | |
I2C_SMC_PWR_SDA | Default | d | 0.300 | |
I2C_SMC_SNS0_SCL | Default | d | 0.300 | |
I2C_SMC_SNS0_SCL_1V8 | Default | d | 0.555 | |
I2C_SMC_SNS0_SDA | Default | d | 0.300 | |
I2C_SMC_SNS0_SDA_1V8 | Default | d | 0.555 | |
I2C_SMC_UPC2_3V3_SCL | Default | d | OL | |
I2C_SMC_UPC2_3V3_SDA | Default | d | OL | |
I2C_SMC_UPC_SCL | Default | d | 0.300 | |
I2C_SMC_UPC_SDA | Default | d | 0.300 | |
I2C_SPKRAMP_L_SCL | Default | d | 0.350 | |
I2C_SPKRAMP_L_SDA | Default | d | 0.300 | |
I2C_SPKRAMP_R_SCL | Default | d | 0.300 | |
I2C_SPKRAMP_R_SDA | Default | d | 0.300 | |
I2C_TCON_BKLT_SCL | Default | d | 0.300 | |
I2C_TCON_BKLT_SCL_1V8 | Default | d | 0.590 | |
I2C_TCON_BKLT_SDA | Default | d | 0.300 | |
I2C_TCON_BKLT_SDA_1V8 | Default | d | 0.590 | |
I2C_TPAD_CONN_SCL | Default | d | 0.560 | |
I2C_TPAD_CONN_SDA | Default | d | 0.560 | |
I2C_UPC01_3V3_SCL | Default | d | OL | |
I2C_UPC01_3V3_SDA | Default | d | OL | |
I2C_UPC0_ATCRTMR0_SCL | Default | d | 0.520 | |
I2C_UPC0_ATCRTMR0_SCL_1V2 | Default | d | 0.335 | |
I2C_UPC0_ATCRTMR0_SDA | Default | d | 0.520 | |
I2C_UPC0_ATCRTMR0_SDA_1V2 | Default | d | 0.335 | |
I2C_UPC1_ATCRTMR1_SCL | Default | d | 0.520 | |
I2C_UPC1_ATCRTMR1_SCL_1V2 | Default | d | 0.320 | |
I2C_UPC1_ATCRTMR1_SDA | Default | d | 0.520 | |
I2C_UPC1_ATCRTMR1_SDA_1V2 | Default | d | 0.320 | |
I2C_UPC2_ATCRTMR2_SCL | Default | d | 0.520 | |
I2C_UPC2_ATCRTMR2_SCL_1V2 | Default | d | 0.325 | |
I2C_UPC2_ATCRTMR2_SDA | Default | d | 0.520 | |
I2C_UPC2_ATCRTMR2_SDA_1V2 | Default | d | 0.325 | |
I2C_UPC5_SCL | Default | d | 0.590 | |
I2C_UPC5_SDA | Default | d | 0.590 | |
I2C_UPC_SCL | Default | d | 0.305 | |
I2C_UPC_SDA | Default | d | 0.305 | |
INT_I2C_EUSBLS0_L | Default | d | 0.460 | |
INT_I2C_EUSBLS1_L | Default | d | 0.460 | |
INT_I2C_EUSBLS2_L | Default | d | 0.460 | |
INT_I2C_UPC0_ATCRTMR0_L | Default | d | 0.330 | |
INT_I2C_UPC1_ATCRTMR1_L | Default | d | 0.320 | |
INT_I2C_UPC2_ATCRTMR2_L | Default | d | 0.330 | |
IOXP1_INT_L | Default | d | 0.640 | |
IOXP1_RESET_L | Default | d | 0.740 | |
IOXP2_ADDR | Default | d | 0.730 | |
IOXP2_INT_L | Default | d | 0.640 | |
IOXP2_RESET_L | Default | d | 0.740 | |
IOXP_I2C_SCL | Default | d | 0.690 | |
IOXP_I2C_SDA | Default | d | 0.665 | |
IPD_LID_OPEN_1V8 | Default | d | 0.750 | |
IPD_LID_OPEN_R_1V8 | Default | d | 0.705 | |
IPD_MCU_INT_CONN_L | Default | d | 0.805 | |
IPD_MCU_INT_L | Default | d | 0.300 | |
IPD_MCU_RESET_L | Default | d | 0.755 | |
IPD_MTP_FUNC_1 | Default | d | 0.300 | |
IPD_MTP_FUNC_1_CONN | Default | d | 0.625 | |
IPD_PWR_EN | Default | d | 0.530 | |
IPD_PWR_EN_PMU | Default | d | 0.700 | |
IPD_PWR_HOLD | Default | d | 0.680 | |
IPD_SYS_AWAKE | Default | d | 0.300 | |
IPD_SYS_AWAKE_CONN | Default | d | 0.460 | |
IPD_TOUCH_CLK_CONN | Default | d | OL | |
IPD_TOUCH_INT_CONN_L | Default | d | 0.805 | |
IPD_TOUCH_INT_L | Default | d | 0.300 | |
IPD_TOUCH_RESET_L | Default | d | 0.755 | |
IPD_WAKE_L | Default | d | 0.740 | |
ISNS_PP3V8_AON_MPMU_N | Default | d | 0.365 | |
ISNS_PP3V8_AON_MPMU_P | Default | d | 0.365 | |
ISNS_PP3V8_AON_SPMU_N | Default | d | 0.365 | |
ISNS_PP3V8_AON_SPMU_P | Default | d | 0.365 | |
ISNS_PPBUS_AON_LUXE_N | Default | d | 0.490 | |
ISNS_PPBUS_AON_LUXE_P | Default | d | 0.490 | |
ISNS_PPVIN_P1V8VDDH_N | Default | d | 0.490 | |
ISNS_PPVIN_P1V8VDDH_P | Default | d | 0.490 | |
ISNS_PPVIN_P5VS2TPS_N | Default | d | 0.490 | |
ISNS_PPVIN_P5VS2TPS_P | Default | d | 0.490 | |
KBDBKLT_EN | Default | d | 0.570 | |
KBDBKLT_FB2 | Default | d | 0.590 | |
KBDBKLT_ISET_KEYB | Default | d | 0.680 | |
KBDBKLT_SENSE_OUT | Default | d | 0.730 | |
KBDBKLT_SW2 | Default | d | 0.400 | |
KBDLED_CATHODE1 | Default | d | 0.670 | |
KBDLED_CATHODE2 | Default | d | 0.665 | |
KBDLED_KEYB1 | Default | d | 0.660 | |
KBDLED_KEYB2 | Default | d | 0.650 | |
KBD_BKLT_5V_ISENSE | Default | d | 0.735 | |
KBD_BKLT_PWM | Default | d | 0.300 | |
KBD_BKLT_PWM_3V3 | Default | d | 0.455 | |
KBD_BKLT_PWM_R | Default | d | 0.300 | |
KBD_CAP_CATHODE | Default | d | 0.495 | |
KBD_CONTROL_KEY | Default | d | 0.475 | |
KBD_CONTROL_L | Default | d | 0.470 | |
KBD_DRIVE_Y0 | Default | d | 0.605 | |
KBD_DRIVE_Y1 | Default | d | 0.580 | |
KBD_DRIVE_Y10 | Default | d | 0.595 | |
KBD_DRIVE_Y11 | Default | d | 0.600 | |
KBD_DRIVE_Y2 | Default | d | 0.600 | |
KBD_DRIVE_Y3 | Default | d | 0.600 | |
KBD_DRIVE_Y4 | Default | d | 0.605 | |
KBD_DRIVE_Y5 | Default | d | 0.595 | |
KBD_DRIVE_Y6 | Default | d | 0.540 | |
KBD_DRIVE_Y7 | Default | d | 0.535 | |
KBD_DRIVE_Y8 | Default | d | 0.533 | |
KBD_DRIVE_Y9 | Default | d | 0.540 | |
KBD_ID1 | Default | d | 0.785 | |
KBD_ID2 | Default | d | 0.785 | |
KBD_ID_DETECT2 | Default | d | 0.600 | |
KBD_INT_L | Default | d | 0.670 | |
KBD_LAYOUT_DETECT | Default | d | 0.590 | |
KBD_LED1 | Default | d | 0.490 | |
KBD_LEFT_OPTION_KEY | Default | d | 0.475 | |
KBD_LEFT_OPTION_L | Default | d | 0.465 | |
KBD_RIGHT_SHIFT_KEY | Default | d | 0.475 | |
KBD_RIGHT_SHIFT_L | Default | d | 0.465 | |
KBD_SENSE_X0 | Default | d | 0.600 | |
KBD_SENSE_X1 | Default | d | 0.595 | |
KBD_SENSE_X10 | Default | d | 0.600 | |
KBD_SENSE_X11 | Default | d | 0.600 | |
KBD_SENSE_X12 | Default | d | 0.600 | |
KBD_SENSE_X2 | Default | d | 0.595 | |
KBD_SENSE_X3 | Default | d | 0.590 | |
KBD_SENSE_X4 | Default | d | 0.595 | |
KBD_SENSE_X5 | Default | d | 0.590 | |
KBD_SENSE_X6 | Default | d | 0.540 | |
KBD_SENSE_X7 | Default | d | 0.535 | |
KBD_SENSE_X8 | Default | d | 0.540 | |
KBD_SENSE_X9 | Default | d | 0.545 | |
LCD_PWR_EN | Default | d | 0.575 | |
LED_ACTV_RDY_R | Default | d | OL | |
LED_CTRL | Default | d | 0.560 | |
LED_ISET | Default | d | 0.570 | |
LED_PMU_RST_R | Default | d | OL | |
LED_PWR_AON_R | Default | d | OL | |
LED_PWR_S2_R | Default | d | OL | |
LED_SOC_DFU_R | Default | d | OL | |
LED_SOC_SWDBG_R | Default | d | OL | |
LED_SYS_ALIVE_R | Default | d | OL | |
LP5_IN_RESET_L | Default | d | 0.745 | |
LP5_IN_RESET_PMU_L | Default | d | 0.745 | |
LPDP_FTCAM_AUX | Default | d | 1.015 | |
LPDP_FTCAM_DATA_C_N<0> | Default | d | OL | |
LPDP_FTCAM_DATA_C_P<0> | Default | d | OL | |
LPDP_INT_AUX_C_N | Default | d | 0.340 | |
LPDP_INT_AUX_C_P | Default | d | 0.340 | |
LPDP_INT_AUX_N | Default | d | OL | |
LPDP_INT_AUX_P | Default | d | OL | |
LPDP_INT_DATA_C_N<0> | Default | d | 0.355 | |
LPDP_INT_DATA_C_N<1> | Default | d | 0.355 | |
LPDP_INT_DATA_C_N<2> | Default | d | 0.355 | |
LPDP_INT_DATA_C_N<3> | Default | d | 0.355 | |
LPDP_INT_DATA_C_P<0> | Default | d | 0.355 | |
LPDP_INT_DATA_C_P<1> | Default | d | 0.355 | |
LPDP_INT_DATA_C_P<2> | Default | d | 0.355 | |
LPDP_INT_DATA_C_P<3> | Default | d | 0.355 | |
LPDP_INT_DATA_N<0> | Default | d | OL | |
LPDP_INT_DATA_N<1> | Default | d | OL | |
LPDP_INT_DATA_N<2> | Default | d | OL | |
LPDP_INT_DATA_N<3> | Default | d | OL | |
LPDP_INT_DATA_P<0> | Default | d | OL | |
LPDP_INT_DATA_P<1> | Default | d | OL | |
LPDP_INT_DATA_P<2> | Default | d | OL | |
LPDP_INT_DATA_P<3> | Default | d | OL | |
LPDP_INT_HPD | Default | d | 0.305 | |
LUXE_AGND | Default | d | 0.000 | |
LUXE_BT_C1 | Default | d | 0.590 | |
LUXE_BT_C2 | Default | d | 0.590 | |
LUXE_COMP | Default | d | 0.610 | |
LUXE_COMP_R | Default | d | OL | |
LUXE_C_VDD | Default | d | 0.495 | |
LUXE_FAULT | Default | d | 0.625 | |
LUXE_ISH_N | Default | d | 0.490 | |
LUXE_ISH_P | Default | d | 0.490 | |
LUXE_ISH_R_N | Default | d | 0.485 | |
LUXE_ISH_R_P | Default | d | 0.490 | |
LUXE_ISL_N | Default | d | 0.000 | |
LUXE_ISL_P | Default | d | 0.000 | |
LUXE_ISL_R_N | Default | d | 0.000 | |
LUXE_ISL_R_P | Default | d | 0.000 | |
LUXE_LG1 | Default | d | 0.460 | |
LUXE_LG1_R | Default | d | 0.455 | |
LUXE_LG2 | Default | d | 0.455 | |
LUXE_LG2_R | Default | d | 0.460 | |
LUXE_UG1 | Default | d | 0.865 | |
LUXE_UG1_R | Default | d | 0.850 | |
LUXE_UG2 | Default | d | 0.860 | |
LUXE_UG2_R | Default | d | 0.850 | |
LUXE_VPROG_TEST | Default | d | 0.605 | |
MACAW0_CLK24M_IN | Default | d | 0.485 | |
MACAW0_CLK24M_OUT | Default | d | 0.485 | |
MACAW0_CLK24M_OUT_R | Default | d | 0.485 | |
MACAW0_RESREF | Default | d | 0.490 | |
MACAW1_CLK24M_IN | Default | d | 0.485 | |
MACAW1_CLK24M_OUT | Default | d | 0.485 | |
MACAW1_CLK24M_OUT_R | Default | d | 0.485 | |
MACAW1_RESREF | Default | d | 0.490 | |
MGL_1V8 | Default | d | 0.720 | |
MPMU_3V8_IOUT | Default | d | 0.720 | |
MPMU_3V8_ISENSE | Default | d | 0.785 | |
MPMU_BUCK0_FB | Default | d | 0.225 | |
MPMU_BUCK0_FB_R | Default | d | 0.220 | |
MPMU_BUCK0_LX0 | Default | d | 0.215 | |
MPMU_BUCK0_LX1 | Default | d | 0.215 | |
MPMU_BUCK0_LX2 | Default | d | 0.215 | |
MPMU_BUCK0_LX3 | Default | d | 0.215 | |
MPMU_BUCK10_FB | Default | d | 0.130 | |
MPMU_BUCK10_FB_R | Default | d | 0.130 | |
MPMU_BUCK10_LX0 | Default | d | 0.125 | |
MPMU_BUCK10_LX1 | Default | d | 0.125 | |
MPMU_BUCK1_FB | Default | d | 0.280 | |
MPMU_BUCK1_FB_R | Default | d | 0.280 | |
MPMU_BUCK1_LX0 | Default | d | 0.270 | |
MPMU_BUCK1_LX1 | Default | d | 0.270 | |
MPMU_BUCK3_FB | Default | d | 0.475 | |
MPMU_BUCK3_FB_R | Default | d | 0.470 | |
MPMU_BUCK3_LX0 | Default | d | 0.470 | |
MPMU_BUCK4_FB | Default | d | 0.040 | |
MPMU_BUCK4_FB | Default | r | 38.300R | |
MPMU_BUCK4_FB_R | Default | d | 0.038 | |
MPMU_BUCK4_LX0 | Default | d | 0.035 | |
MPMU_BUCK4_LX0 | Default | r | 34.400R | |
MPMU_BUCK4_LX1 | Default | d | 0.035 | |
MPMU_BUCK4_LX2 | Default | d | 0.035 | |
MPMU_BUCK4_LX3 | Default | d | 0.035 | |
MPMU_BUCK5_FB | Default | d | 0.180 | |
MPMU_BUCK5_FB_R | Default | d | 0.175 | |
MPMU_BUCK5_LX0 | Default | d | 0.175 | |
MPMU_BUCK5_LX1 | Default | d | 0.175 | |
MPMU_BUCK5_LX2 | Default | d | 0.175 | |
MPMU_BUCK5_LX3 | Default | d | 0.175 | |
MPMU_BUCK6_FB | Default | d | 0.440 | |
MPMU_BUCK6_FB_R | Default | d | 0.440 | |
MPMU_BUCK6_LX0 | Default | d | 0.440 | |
MPMU_BUCK7_FB | Default | d | 0.265 | |
MPMU_BUCK7_FB_R | Default | d | 0.260 | |
MPMU_BUCK7_LX0 | Default | d | 0.270 | |
MPMU_BUCK7_LX1 | Default | d | 0.255 | |
MPMU_BUCK7_LX2 | Default | d | 0.255 | |
MPMU_BUCK8_FB | Default | d | 0.245 | |
MPMU_BUCK8_FB_R | Default | d | 0.245 | |
MPMU_BUCK8_LX0 | Default | d | 0.245 | |
MPMU_BUCK9_FB | Default | d | 0.225 | |
MPMU_BUCK9_FB_R | Default | d | 0.220 | |
MPMU_BUCK9_LX0 | Default | d | 0.220 | |
MPMU_IREF | Default | d | 0.750 | |
MPMU_TCAL | Default | d | 0.775 | |
MPMU_THERMCRASH_L | Default | d | 0.690 | |
MPMU_THMSNS | Default | d | 0.770 | |
MPMU_VREF1V2 | Default | d | 0.630 | |
MPMU_VSS_A_BUCK0 | Default | d | 0.000 | |
MPMU_VSS_A_BUCK4 | Default | d | 0.000 | |
MPMU_VSS_A_BUCK5 | Default | d | 0.000 | |
NAND0_BCM_L | Default | d | 0.320 | |
NAND0_BOOT2 | Default | d | 0.000 | |
NAND0_CLK24M_0123_R | Default | d | 0.300 | |
NAND0_CLK24M_R | Default | d | 0.295 | |
NAND0_CLKREQ0_L | Default | d | 0.295 | |
NAND0_CLKREQ0_R_L | Default | d | 0.295 | |
NAND0_CLKREQ1_L | Default | d | 0.300 | |
NAND0_CLKREQ1_R_L | Default | d | 0.300 | |
NAND0_CLKREQ2_L | Default | d | 0.300 | |
NAND0_CLKREQ2_R_L | Default | d | 0.305 | |
NAND0_CLKREQ3_L | Default | d | 0.300 | |
NAND0_CLKREQ3_R_L | Default | d | 0.300 | |
NAND0_FORCE_EN | Default | d | 0.580 | |
NAND0_JTAG_SEL | Default | d | 0.330 | |
NAND0_JTAG_TRST_L | Default | d | 0.330 | |
NAND0_LPB_L | Default | d | 0.330 | |
NAND0_OCARINA_IREF | Default | d | 0.745 | |
NAND0_OCARINA_PGOOD | Default | d | 0.755 | |
NAND0_OCARINA_TCAL | Default | d | 0.770 | |
NAND0_OCARINA_TDEV1 | Default | d | 0.765 | |
NAND0_OCARINA_TDEV2 | Default | d | 0.770 | |
NAND0_OCARINA_VREF | Default | d | 0.760 | |
NAND0_PCIE_RESET_L | Default | d | 0.290 | |
NAND0_PFN_L | Default | d | 0.330 | |
NAND0_RESET_L | Default | d | 0.330 | |
NAND0_S5E0_PCIE_RESREF | Default | d | 0.200 | |
NAND0_S5E0_SWD_UID0 | Default | d | 0.340 | |
NAND0_S5E0_SWD_UID1 | Default | d | 0.340 | |
NAND0_S5E0_ZQ_0 | Default | d | 0.300 | |
NAND0_S5E0_ZQ_1 | Default | d | 0.300 | |
NAND0_S5E1_JTAG_TDO | Default | d | 0.370 | |
NAND0_S5E1_PCIE_RESREF | Default | d | 0.200 | |
NAND0_S5E1_SWD_UID0 | Default | d | 0.370 | |
NAND0_S5E1_SWD_UID1 | Default | d | 0.370 | |
NAND0_S5E1_ZQ_0 | Default | d | 0.300 | |
NAND0_S5E1_ZQ_1 | Default | d | 0.300 | |
NAND0_S5E2_PCIE_RESREF | Default | d | OL | |
NAND0_S5E2_SWD_UID1 | Default | d | OL | |
NAND0_S5E2_ZQ_0 | Default | d | OL | |
NAND0_S5E2_ZQ_1 | Default | d | OL | |
NAND0_S5E3_PCIE_RESREF | Default | d | OL | |
NAND0_S5E3_SWD_UID0 | Default | d | OL | |
NAND0_S5E3_SWD_UID1 | Default | d | OL | |
NAND0_STG01_ADDR | Default | d | 0.570 | |
NAND0_WP_L | Default | d | 0.320 | |
NAND1_CLK24M_0123_R | Default | d | OL | |
NAND1_CLK24M_R | Default | d | 0.300 | |
NAND1_CLKREQ0_L | Default | d | 0.300 | |
NAND1_CLKREQ0_R_L | Default | d | 0.300 | |
NAND1_CLKREQ1_L | Default | d | 0.300 | |
NAND1_CLKREQ1_R_L | Default | d | 0.300 | |
NAND1_CLKREQ2_L | Default | d | 0.300 | |
NAND1_CLKREQ2_R_L | Default | d | 0.300 | |
NAND1_CLKREQ3_L | Default | d | 0.300 | |
NAND1_CLKREQ3_R_L | Default | d | 0.300 | |
NAND1_PCIE_RESET_L | Default | d | 0.300 | |
NC | Default | d | OL | |
OUT123_EN | Default | d | 0.455 | |
P0V805_ATC01_AGND | Default | d | 0.000 | |
P0V805_ATC01_COMP_FSET | Default | d | 1.645 | |
P0V805_ATC01_DSCHG | Default | d | 0.315 | |
P0V805_ATC01_FB_RC | Default | d | OL | |
P0V805_ATC01_PGOOD | Default | d | 0.685 | |
P0V805_ATC01_SVR_PGND | Default | d | 0.000 | |
P0V805_ATC01_SW | Default | d | 0.310 | |
P0V805_ATC2_AGND | Default | d | 0.000 | |
P0V805_ATC2_COMP_FSET | Default | d | 1.630 | |
P0V805_ATC2_DSCHG | Default | d | 0.365 | |
P0V805_ATC2_FB | Default | d | OL | |
P0V805_ATC2_FB_R | Default | d | 1.010 | |
P0V805_ATC2_FB_RC | Default | d | OL | |
P0V805_ATC2_FB_TOP | Default | d | 0.370 | |
P0V805_ATC2_PGOOD | Default | d | 0.690 | |
P0V805_ATC2_SVR_PGND | Default | d | 0.000 | |
P0V805_ATC2_SW | Default | d | 0.355 | |
P0V855_ATC01_AGND | Default | d | 0.000 | |
P0V855_ATC01_COMP_FSET | Default | d | 1.645 | |
P0V855_ATC01_DSCHG | Default | d | 0.250 | |
P0V855_ATC01_FB | Default | d | OL | |
P0V855_ATC01_FB_R | Default | d | 1.935 | |
P0V855_ATC01_FB_RC | Default | d | OL | |
P0V855_ATC01_FB_TOP | Default | d | 0.245 | |
P0V855_ATC01_PGOOD | Default | d | 0.685 | |
P0V855_ATC01_SVR_PGND | Default | d | 0.000 | |
P0V855_ATC01_SW | Default | d | 0.240 | |
P0V855_ATC2_AGND | Default | d | 0.000 | |
P0V855_ATC2_COMP_FSET | Default | d | 1.640 | |
P0V855_ATC2_DSCHG | Default | d | 0.300 | |
P0V855_ATC2_FB | Default | d | OL | |
P0V855_ATC2_FB_R | Default | d | 2.020 | |
P0V855_ATC2_FB_RC | Default | d | OL | |
P0V855_ATC2_FB_TOP | Default | d | OL | |
P0V855_ATC2_FB_TOP_R | Default | d | 0.300 | |
P0V855_ATC2_PGOOD | Default | d | 0.690 | |
P0V855_ATC2_SVR_PGND | Default | d | 0.000 | |
P0V855_ATC2_SW | Default | d | 0.300 | |
P0V95_DSCHG_EN_RC | Default | d | 0.665 | |
P0V95_HDMI_AGND | Default | d | 0.000 | |
P0V95_HDMI_COMP | Default | d | 0.685 | |
P0V95_HDMI_COMP_RC | Default | d | OL | |
P0V95_HDMI_DSCHG | Default | d | 0.420 | |
P0V95_HDMI_EN | Default | d | 0.630 | |
P0V95_HDMI_EN_R | Default | d | 0.630 | |
P0V95_HDMI_FB | Default | d | 0.680 | |
P0V95_HDMI_FB_R | Default | d | 0.900 | |
P0V95_HDMI_FB_TOP | Default | d | 0.435 | |
P0V95_HDMI_FB_TOP_R | Default | d | 0.425 | |
P0V95_HDMI_PGOOD | Default | d | 0.645 | |
P0V95_HDMI_SKIP | Default | d | 0.610 | |
P0V95_HDMI_SS | Default | d | 0.600 | |
P0V95_HDMI_SVR_PGND | Default | d | 0.000 | |
P0V95_HDMI_SW | Default | d | 0.415 | |
P0V9_LX0_NAND0 | Default | d | 0.335 | |
P0V9_LX1_NAND0 | Default | d | 0.335 | |
P1V2_ATC01_DSCHG | Default | d | 0.395 | |
P1V2_ATC01_SVR_PGND | Default | d | 0.000 | |
P1V2_ATC2_AGND | Default | d | 0.000 | |
P1V2_ATC2_COMP_FSET | Default | d | 1.650 | |
P1V2_ATC2_DSCHG | Default | d | 0.440 | |
P1V2_ATC2_FB | Default | d | OL | |
P1V2_ATC2_FB_R | Default | d | 0.755 | |
P1V2_ATC2_FB_RC | Default | d | OL | |
P1V2_ATC2_FB_TOP | Default | d | 0.445 | |
P1V2_ATC2_PGOOD | Default | d | 0.690 | |
P1V2_ATC2_SVR_PGND | Default | d | 0.000 | |
P1V2_ATC2_SW | Default | d | 0.435 | |
P1V2_HDMI_PWR_EN | Default | d | 0.550 | |
P1V2_LX0_NAND0 | Default | d | 0.320 | |
P1V8VDDH_DRMOS_ISENSE2_N | Default | d | 0.540 | |
P1V8VDDH_DRMOS_ISENSE2_P | Default | d | 0.615 | |
P1V8VDDH_DRMOS_ISENSE3_N | Default | d | 0.540 | |
P1V8VDDH_DRMOS_ISENSE3_P | Default | d | 0.615 | |
P1V8VDDH_DRMOS_PWM3 | Default | d | 0.620 | |
P1V8VDDH_DRMOS_TSENSE | Default | d | 0.560 | |
P1V8VDDH_HS_IOUT | Default | d | 0.725 | |
P1V8VDDH_HS_ISENSE | Default | d | 0.730 | |
P1V8VDDH_ILIMIT_THROTTLE_L | Default | d | 0.300 | |
P1V8VDDH_PWR_EN | Default | d | 0.625 | |
P1V8VDDH_RISNS1_N | Default | d | 0.091 | |
P1V8VDDH_RISNS1_P | Default | d | 0.091 | |
P1V8VDDH_RISNS2_N | Default | d | 0.091 | |
P1V8VDDH_RISNS2_P | Default | d | 0.091 | |
P1V8VDDH_RISNS3_N | Default | d | 0.091 | |
P1V8VDDH_RISNS3_P | Default | d | 0.091 | |
P1V8VDDH_SLP_L | Default | d | 0.625 | |
P1V8VDDH_SW1 | Default | d | 0.091 | |
P1V8VDDH_SW1_L | Default | d | 0.091 | |
P1V8VDDH_SW2 | Default | d | 0.091 | |
P1V8VDDH_SW2_L | Default | d | 0.091 | |
P1V8VDDH_SW3 | Default | d | 0.091 | |
P1V8VDDH_SW3_L | Default | d | 0.091 | |
P1V8VDDH_THMSNS_1 | Default | d | 0.775 | |
P1V8VDDH_THMSNS_2 | Default | d | 0.775 | |
P1V8VDDH_THMSNS_3 | Default | d | 0.775 | |
P1V8VDDH_TLIMIT_THROTTLE_L | Default | d | 0.305 | |
P1V8VDDH_TSENSE | Default | d | 0.605 | |
P1V8VDDH_TSENSE_AMP_FB | Default | d | 0.605 | |
P1V8VDDH_TSENSE_AMP_IN | Default | d | 0.675 | |
P1V8VDDH_TSENSE_DIV | Default | d | 0.670 | |
P1V8VDDH_VSENSE | Default | d | 0.725 | |
P2V5_NAND0_BIAS | Default | d | 0.360 | |
P2V5_NAND0_BST | Default | d | 0.585 | |
P2V5_NAND0_BST_R | Default | d | 0.585 | |
P2V5_NAND0_EN | Default | d | 0.675 | |
P2V5_NAND0_EN_R | Default | d | 0.670 | |
P2V5_NAND0_FB | Default | d | OL | |
P2V5_NAND0_FB_C | Default | d | OL | |
P2V5_NAND0_FB_RC | Default | d | OL | |
P2V5_NAND0_FB_RC2 | Default | d | OL | |
P2V5_NAND0_FB_XW | Default | d | 0.305 | |
P2V5_NAND0_PGOOD | Default | d | 0.540 | |
P2V5_NAND0_RT | Default | d | 0.730 | |
P2V5_NAND0_SS | Default | d | 0.715 | |
P2V5_NAND0_SW | Default | d | 0.310 | |
P2V5_NAND0_VC | Default | d | 0.750 | |
P2V5_NAND0_VC_R | Default | d | OL | |
P2V5_NAND1_EN | Default | d | OL | |
P3V3SD_FB | Default | d | 1.390 | |
P3V3SD_FB_R | Default | d | OL | |
P3V3SD_PHASE | Default | d | 0.420 | |
P3V3SD_VOS | Default | d | 0.425 | |
P3V3_HDMI_PWR_EN | Default | d | 0.540 | |
P3V8AONISEN_MUX_EN | Default | d | 0.675 | |
P3V8AONISEN_MUX_EN_L | Default | d | 0.460 | |
P3V8AON_BST1 | Default | d | 0.615 | |
P3V8AON_BST1_RC | Default | d | 0.615 | |
P3V8AON_BST2 | Default | d | 0.615 | |
P3V8AON_BST2_RC | Default | d | 0.615 | |
P3V8AON_BST3 | Default | d | 0.615 | |
P3V8AON_BST3_RC | Default | d | 0.615 | |
P3V8AON_DRVH1 | Default | d | 1.000 | |
P3V8AON_DRVH1_R | Default | d | 1.000 | |
P3V8AON_DRVH2 | Default | d | 1.000 | |
P3V8AON_DRVH2_R | Default | d | 1.000 | |
P3V8AON_DRVH3 | Default | d | 1.000 | |
P3V8AON_DRVH3_R | Default | d | 1.000 | |
P3V8AON_DRVL1 | Default | d | 0.665 | |
P3V8AON_DRVL1_R | Default | d | 0.670 | |
P3V8AON_DRVL2 | Default | d | 0.670 | |
P3V8AON_DRVL2_R | Default | d | 0.670 | |
P3V8AON_DRVL2_RR | Default | d | - | |
P3V8AON_DRVL3 | Default | d | 0.670 | |
P3V8AON_DRVL3_R | Default | d | 0.670 | |
P3V8AON_DRVL3_RR | Default | d | 0.670 | |
P3V8AON_FAULT_L | Default | d | 0.700 | |
P3V8AON_GPIO | Default | d | 0.700 | |
P3V8AON_HS_ISENSE | Default | d | 0.735 | |
P3V8AON_ILIMIT_BUF_L | Default | d | 0.710 | |
P3V8AON_ILIMIT_DIV | Default | d | 0.735 | |
P3V8AON_ILIMIT_L | Default | d | 0.565 | |
P3V8AON_IMON | Default | d | OL | |
P3V8AON_IMON_P3V8AON | Default | d | 0.780 | |
P3V8AON_ISEN1_N | Default | d | 0.365 | |
P3V8AON_ISEN1_P | Default | d | 0.365 | |
P3V8AON_ISEN2_N | Default | d | 0.365 | |
P3V8AON_ISEN2_P | Default | d | 0.365 | |
P3V8AON_ISEN3_N | Default | d | 0.365 | |
P3V8AON_ISEN3_P | Default | d | 0.365 | |
P3V8AON_ISENSE | Default | d | 0.730 | |
P3V8AON_ISENSE_EXT | Default | d | 0.650 | |
P3V8AON_ISENSE_EXT_R | Default | d | 0.730 | |
P3V8AON_ISEN_IN_N | Default | d | 0.600 | |
P3V8AON_ISEN_IN_N_FET | Default | d | 0.670 | |
P3V8AON_ISEN_IN_N_R | Default | d | 0.645 | |
P3V8AON_ISEN_IN_P | Default | d | 0.600 | |
P3V8AON_ISEN_IN_P_FET | Default | d | 0.670 | |
P3V8AON_ISEN_IN_P_R | Default | d | 0.670 | |
P3V8AON_ISNS1_N | Default | d | 0.365 | |
P3V8AON_ISNS1_P | Default | d | 0.365 | |
P3V8AON_ISNS2_N | Default | d | 0.365 | |
P3V8AON_ISNS2_P | Default | d | 0.365 | |
P3V8AON_ISNS3_N | Default | d | 0.365 | |
P3V8AON_ISNS3_P | Default | d | 0.365 | |
P3V8AON_LPM | Default | d | 0.685 | |
P3V8AON_LPM_R | Default | d | 0.680 | |
P3V8AON_PVCC | Default | d | 0.560 | |
P3V8AON_PWR_EN | Default | d | 0.620 | |
P3V8AON_PWR_EN_R | Default | d | 0.620 | |
P3V8AON_SNUB1 | Default | d | 0.365 | |
P3V8AON_SS | Default | d | 0.755 | |
P3V8AON_SW1 | Default | d | 0.365 | |
P3V8AON_SW2 | Default | d | 0.365 | |
P3V8AON_SW3 | Default | d | 0.365 | |
P3V8AON_VRTN | Default | d | 0.000 | |
P3V8AON_VSENSE | Default | d | 0.365 | |
P3V8AON_VSNS_XW_N | Default | d | 0.000 | |
P3V8AON_VSNS_XW_P | Default | d | 0.365 | |
P3V8AON_VSW1 | Default | d | 0.365 | |
P5VS2SN_PGOOD | Default | d | 0.670 | |
P5VS2TPS_PWR_EN | Default | d | 0.580 | |
P5VS2_AGND | Default | d | 0.000 | |
P5VS2_DSCHG | Default | d | 0.490 | |
P5VS2_DSCHG_EN | Default | d | 0.525 | |
P5VS2_DSCHG_EN_L | Default | d | 0.580 | |
P5VS2_EN | Default | d | 0.580 | |
P5VS2_FB | Default | d | 0.750 | |
P5VS2_FB_LPF | Default | d | 0.415 | |
P5VS2_FB_R | Default | d | 0.000 | |
P5VS2_FB_XW | Default | d | 0.400 | |
P5VS2_HS_IOUT | Default | d | 0.720 | |
P5VS2_HS_ISENSE | Default | d | 0.730 | |
P5VS2_PWR_EN | Default | d | 0.700 | |
P5VS2_SS | Default | d | 0.750 | |
P5VS2_SW | Default | d | 0.400 | |
P5VS2_VOS | Default | d | 0.415 | |
P5VUSB01_HS_ISENSE | Default | d | 0.790 | |
P5VUSBC01_AGND | Default | d | 0.000 | |
P5VUSBC01_BIAS | Default | d | 0.310 | |
P5VUSBC01_DSCHG | Default | d | 0.420 | |
P5VUSBC01_DSCHG_EN | Default | d | 0.530 | |
P5VUSBC01_EN | Default | d | 0.675 | |
P5VUSBC01_EN_R | Default | d | 0.670 | |
P5VUSBC01_EN_R2 | Default | d | 0.375 | |
P5VUSBC01_FB | Default | d | 0.750 | |
P5VUSBC01_FB_C | Default | d | OL | |
P5VUSBC01_FB_RC | Default | d | 0.320 | |
P5VUSBC01_FB_RC2 | Default | d | OL | |
P5VUSBC01_FB_XW | Default | d | 0.310 | |
P5VUSBC01_INTVCC | Default | d | 0.565 | |
P5VUSBC01_PGOOD | Default | d | 0.695 | |
P5VUSBC01_RT | Default | d | 0.735 | |
P5VUSBC01_SS | Default | d | 0.720 | |
P5VUSBC01_SW | Default | d | 0.310 | |
P5VUSBC01_VC | Default | d | 0.750 | |
P5VUSBC01_VC_R | Default | d | OL | |
P5VUSBC23_EN | Default | d | 0.640 | |
P5VUSBC23_EN_R | Default | d | 0.650 | |
P5VUSBC23_FB | Default | d | 1.350 | |
P5VUSBC23_FB_R | Default | d | 0.470 | |
P5VUSBC23_PGOOD | Default | d | 0.690 | |
P5VUSBC23_RA | Default | d | OL | |
P5VUSBC23_SS | Default | d | 0.550 | |
P5VUSBC23_SW1 | Default | d | 0.455 | |
P5VUSBC23_SW2 | Default | d | 0.455 | |
PBUS_VSNS_EN_L | Default | d | 0.405 | |
PBUS_VSNS_EN_L_DIV | Default | d | OL | |
PBUS_VSNS_IN | Default | d | 0.490 | |
PBUS_VSNS_OUT | Default | d | OL | |
PCIE_NAND0_D2R_C_N<0> | Default | d | 0.360 | |
PCIE_NAND0_D2R_C_N<1> | Default | d | 0.615 | |
PCIE_NAND0_D2R_C_P<0> | Default | d | 0.360 | |
PCIE_NAND0_D2R_C_P<1> | Default | d | 0.615 | |
PCIE_NAND0_D2R_N<0> | Default | d | 0.410 | |
PCIE_NAND0_D2R_N<1> | Default | d | 0.410 | |
PCIE_NAND0_D2R_P<0> | Default | d | 0.410 | |
PCIE_NAND0_D2R_P<1> | Default | d | 0.410 | |
PCIE_NAND0_R2D_C_N<0> | Default | d | 0.350 | |
PCIE_NAND0_R2D_C_N<1> | Default | d | 0.350 | |
PCIE_NAND0_R2D_C_P<0> | Default | d | 0.350 | |
PCIE_NAND0_R2D_C_P<1> | Default | d | 0.350 | |
PCIE_NAND0_R2D_N<0> | Default | d | 0.385 | |
PCIE_NAND0_R2D_N<1> | Default | d | 0.460 | |
PCIE_NAND0_R2D_P<0> | Default | d | 0.385 | |
PCIE_NAND0_R2D_P<1> | Default | d | 0.460 | |
PDM_DMIC_CLK7_1V8 | Default | d | 0.490 | |
PDM_DMIC_CLK7_1V8_R | Default | d | 0.460 | |
PDM_DMIC_CLK7_R | Default | d | 0.300 | |
PDM_DMIC_CLK8 | Default | d | 0.330 | |
PDM_DMIC_CLK8_1V8 | Default | d | 0.490 | |
PDM_DMIC_CLK8_1V8_R | Default | d | 0.460 | |
PDM_DMIC_DATA1 | Default | d | 0.300 | |
PDM_DMIC_DATA1_1V8 | Default | d | 0.480 | |
PDM_DMIC_DATA1_R | Default | d | 0.330 | |
PDM_DMIC_DATA4 | Default | d | 0.305 | |
PDM_DMIC_DATA4_1V8 | Default | d | 0.480 | |
PDM_DMIC_DATA4_R | Default | d | 0.335 | |
PD_ACE5_VCONN | Default | d | 0.540 | |
PD_ATC2_PWR_EN | Default | d | 0.400 | |
PD_UART_UPC0_RX_TX | Default | d | 0.550 | |
PD_UART_UPC1_RX_TX | Default | d | 0.550 | |
PD_UART_UPC2_RX_TX | Default | d | 0.550 | |
PD_UPC0_GPIO1 | Default | d | 0.670 | |
PD_UPC0_GPIO6 | Default | d | 0.715 | |
PD_UPC0_HPD | Default | d | 0.715 | |
PD_UPC0_HRESET | Default | d | 0.000 | |
PD_UPC0_MRESET | Default | d | 0.680 | |
PD_UPC0_USBP3_RN | Default | d | 0.730 | |
PD_UPC0_USBP3_RP | Default | d | 0.730 | |
PD_UPC1_DBG0_R | Default | d | 0.710 | |
PD_UPC1_DBG1_R | Default | d | 0.700 | |
PD_UPC1_DBG2_R | Default | d | 0.700 | |
PD_UPC1_DBG3_R | Default | d | 0.700 | |
PD_UPC1_DBG4_R | Default | d | 0.700 | |
PD_UPC1_DBG5_R | Default | d | 0.700 | |
PD_UPC1_GPIO1 | Default | d | 0.670 | |
PD_UPC1_GPIO10 | Default | d | 0.710 | |
PD_UPC1_GPIO6 | Default | d | 0.710 | |
PD_UPC1_GPIO7 | Default | d | 0.710 | |
PD_UPC1_GPIO9 | Default | d | 0.705 | |
PD_UPC1_HPD | Default | d | 0.710 | |
PD_UPC1_HRESET | Default | d | 0.000 | |
PD_UPC1_MRESET | Default | d | 0.670 | |
PD_UPC1_USBP2_RN | Default | d | 0.485 | |
PD_UPC1_USBP2_RP | Default | d | 0.480 | |
PD_UPC1_USBP3_RN | Default | d | 0.730 | |
PD_UPC1_USBP3_RP | Default | d | 0.730 | |
PD_UPC2_DBG0_R | Default | d | 0.705 | |
PD_UPC2_DBG1_R | Default | d | 0.700 | |
PD_UPC2_DBG2_R | Default | d | 0.700 | |
PD_UPC2_DBG3_R | Default | d | 0.700 | |
PD_UPC2_DBG4_R | Default | d | 0.700 | |
PD_UPC2_DBG5_R | Default | d | 0.700 | |
PD_UPC2_GPIO1 | Default | d | 0.680 | |
PD_UPC2_GPIO10 | Default | d | 0.710 | |
PD_UPC2_GPIO6 | Default | d | 0.710 | |
PD_UPC2_GPIO7 | Default | d | 0.710 | |
PD_UPC2_GPIO9 | Default | d | 0.710 | |
PD_UPC2_HPD | Default | d | 0.710 | |
PD_UPC2_HRESET | Default | d | 0.000 | |
PD_UPC2_MRESET | Default | d | 0.690 | |
PD_UPC2_USBP2_RN | Default | d | 0.730 | |
PD_UPC2_USBP2_RP | Default | d | 0.725 | |
PD_UPC2_USBP3_RN | Default | d | 0.730 | |
PD_UPC2_USBP3_RP | Default | d | 0.725 | |
PD_UPC5_DBG_R | Default | d | 0.630 | |
PD_UPC5_HPD | Default | d | 0.715 | |
PD_UPC5_HRESET | Default | d | 0.000 | |
PD_UPC5_MRESET | Default | d | 0.700 | |
PD_UPC5_PORT_MUX | Default | d | 0.755 | |
PD_UPC5_USB2 | Default | d | 0.620 | |
PD_UPC5_USB_RP | Default | d | 0.660 | |
PIND_PFET_EN | Default | d | 0.495 | |
PMU_ACTIVE_READY | Default | d | 0.455 | |
PMU_CLK32K_CLVR | Default | d | 0.445 | |
PMU_CLK32K_CLVR_R | Default | d | 0.470 | |
PMU_CLK32K_SOC | Default | d | 0.305 | |
PMU_CLK32K_SOC_R | Default | d | 0.330 | |
PMU_CLK32K_WLBT | Default | d | 0.470 | |
PMU_CLK32K_WLBT_IPD | Default | d | 0.470 | |
PMU_CLK32K_WLBT_IPD_R | Default | d | 0.490 | |
PMU_CRASH_L | Default | d | 0.440 | |
PMU_CRASH_R_L | Default | d | 0.440 | |
PMU_DBGLED_ENABLE | Default | d | 0.755 | |
PMU_FORCE_DFU | Default | d | 0.745 | |
PMU_ONOFF_L | Default | d | 0.680 | |
PMU_ONOFF_L_CONN | Default | d | 0.690 | |
PMU_RESET_L | Default | d | 0.300 | |
PMU_RSLOC_RST_L | Default | d | 0.510 | |
PMU_SCRASH_L | Default | d | 0.690 | |
PMU_SHDN | Default | d | 0.750 | |
PMU_SHDN_DBG | Default | d | OL | |
PMU_SYS_ALIVE | Default | d | 0.530 | |
PMU_UVWARN_ILIMIT_L | Default | d | 0.305 | |
PMU_VDDHI | Default | d | 0.680 | |
PMU_VDDHI_UVWARN_L | Default | d | 0.310 | |
PMU_VDDMAIN_UVWARN_L | Default | d | 0.700 | |
PMU_WAKE2MS | Default | d | 0.720 | |
PP0V805_ATC01_REG_XW | Default | d | 0.310 | |
PP0V805_ATC2_REG_XW | Default | d | 0.355 | |
PP0V805_ATCRTMR01_VDD_FIXED | Default | d | 0.310 | |
PP0V805_ATCRTMR2_VDD_FIXED | Default | d | 0.355 | |
PP0V855_ATC01_REG_XW | Default | d | 0.240 | |
PP0V855_ATC2_REG_XW | Default | d | 0.300 | |
PP0V855_ATCRTMR01_VDD_CIO | Default | d | 0.240 | |
PP0V855_ATCRTMR2_VDD_CIO | Default | d | 0.300 | |
PP0V8_S2_CLVR_VDDDIG | Default | d | 0.310 | |
PP0V95_AWAKESW_DP2HDMI | Default | d | 0.415 | |
PP0V95_DP2HDMI_VDDA | Default | d | 0.415 | |
PP0V95_DP2HDMI_VDDRX | Default | d | 0.415 | |
PP0V95_DP2HDMI_VDDTX | Default | d | 0.415 | |
PP0V9_NAND0 | Default | d | 0.335 | |
PP0V9_NAND0_FB_DIS | Default | d | 0.330 | |
PP0V9_NAND0_S5E0_VDD_PLL | Default | d | 0.335 | |
PP0V9_NAND0_S5E1_VDD_PLL | Default | d | 0.335 | |
PP0V9_NAND0_S5E2_VDD_PLL | Default | d | OL | |
PP16V0_TOUCHID | Default | d | 0.650 | |
PP16V0_TOUCHID_FILT_CONN | Default | d | 0.650 | |
PP16V0_TOUCHID_SW | Default | v | 0.365 | |
PP17V0_LDOIN | Default | d | 0.590 | |
PP1V1_EUSBLS2_VCCD | Default | d | 0.535 | |
PP1V1_MACAW0_VCCD | Default | d | 0.540 | |
PP1V1_MACAW1_VCCD | Default | d | 0.540 | |
PP1V2_AON | Default | d | 0.660 | |
PP1V2_AON_SPMU | Default | d | 0.670 | |
PP1V2_ATC2_REG_XW | Default | d | 0.435 | |
PP1V2_ATCRTMR01_LVL | Default | d | 0.245 | |
PP1V2_ATCRTMR01_VDDIO | Default | d | 0.390 | |
PP1V2_ATCRTMR0_VDDIO_XTAL_F | Default | d | 0.390 | |
PP1V2_ATCRTMR1_VDDIO_XTAL_F | Default | d | 0.390 | |
PP1V2_ATCRTMR2_LVL | Default | d | 0.240 | |
PP1V2_ATCRTMR2_VDDIO | Default | d | 0.435 | |
PP1V2_ATCRTMR2_VDDIO_XTAL_F | Default | d | 0.435 | |
PP1V2_AWAKE | Default | d | 0.245 | |
PP1V2_AWAKESW_BLC | Default | d | 0.715 | |
PP1V2_AWAKESW_DP2HDMI | Default | d | 0.530 | |
PP1V2_CODEC_VL_VD | Default | d | 0.245 | |
PP1V2_DP2HDMI | Default | d | 0.530 | |
PP1V2_GL_LOOP | Default | d | 0.460 | |
PP1V2_GL_LOOP_FL | Default | d | 0.460 | |
PP1V2_NAND0 | Default | d | 0.320 | |
PP1V2_NAND0_FB_DIS | Default | d | 0.320 | |
PP1V2_NAND0_S5E0_AVDD1X_PLL | Default | d | 0.320 | |
PP1V2_NAND0_S5E0_PCI_AVDD_H | Default | d | 0.320 | |
PP1V2_NAND0_S5E1_AVDD1X_PLL | Default | d | 0.320 | |
PP1V2_NAND0_S5E1_PCI_AVDD_H | Default | d | 0.320 | |
PP1V2_NAND0_S5E2_PCI_AVDD_H | Default | d | 0.320 | |
PP1V2_S2 | Default | d | 0.245 | |
PP1V2_S2_CLVR_VDDIO | Default | d | 0.445 | |
PP1V5_AON_VCORE_MPMU | Default | d | 0.380 | |
PP1V5_AON_VCORE_SPMU | Default | d | 0.375 | |
PP1V5_AON_VRTC_MPMU | Default | d | 0.380 | |
PP1V5_AON_VRTC_SPMU | Default | d | 0.380 | |
PP1V5_UPC1_LDO_CORE | Default | d | 0.510 | |
PP1V5_UPC2_LDO_CORE | Default | d | 0.520 | |
PP1V5_UPC5_LDO_CORE | Default | d | 0.510 | |
PP1V85_S2_KBD | Default | d | 0.455 | |
PP1V8_AON | Default | d | 0.450 | |
PP1V8_AON_SPMU | Default | d | 0.535 | |
PP1V8_AWAKE | Default | d | 0.375 | |
PP1V8_CODEC_VA | Default | d | 0.375 | |
PP1V8_CODEC_VCP | Default | d | 0.375 | |
PP1V8_DMIC | Default | d | 0.260 | |
PP1V8_GL_SDCONN | Default | d | 0.455 | |
PP1V8_S1_CLVR_VDDH | Default | d | 0.091 | |
PP1V8_S1_CLVR_VDDH | Default | r | 91.300R | |
PP1V8_S1_CLVR_VDDH_VSNS_IN | Default | d | 0.095 | |
PP1V8_S1_CLVR_VDDH_VSNS_IN | Default | r | 93.000R | |
PP1V8_S2 | Default | d | 0.260 | |
PP1V8_S2SW | Default | d | 0.470 | |
PP1V8_S2SW_CLVR_VDDC1 | Default | d | 0.520 | |
PP1V8_S2SW_SNS | Default | d | 0.530 | |
PP1V8_S2_IMU_FILT | Default | d | 0.260 | |
PP1V8_TOUCHID | Default | d | 0.490 | |
PP1V8_TOUCHID_FILT_CONN | Default | d | 0.490 | |
PP2V5_NAND0 | Default | d | 0.310 | |
PP2V5_NAND0_INTVCC | Default | d | 0.560 | |
PP2V5_NAND1 | Default | d | OL | |
PP2V5_VREF_P3V8AONILIMIT | Default | d | 0.685 | |
PP3V0_TOUCHID | Default | d | 0.570 | |
PP3V0_TOUCHID_FILT_CONN | Default | d | 0.570 | |
PP3V3_AON | Default | d | 0.400 | |
PP3V3_AON_KBD_CONN | Default | d | 0.400 | |
PP3V3_AWAKESW_DP2HDMI | Default | d | 0.455 | |
PP3V3_AWAKE_SW_SD | Default | d | 0.420 | |
PP3V3_AWAKE_SW_SD_FL | Default | d | 0.415 | |
PP3V3_DP2HDMI | Default | d | 0.460 | |
PP3V3_GL_SDCONN | Default | d | 0.455 | |
PP3V3_S2 | Default | d | 0.400 | |
PP3V3_S2_IPD | Default | d | 0.435 | |
PP3V3_S2_MTPFUNC1 | Default | d | 0.590 | |
PP3V3_UPC0_LDO | Default | d | 0.490 | |
PP3V3_UPC1_LDO | Default | d | 0.490 | |
PP3V3_UPC2_LDO | Default | d | 0.485 | |
PP3V3_UPC5_LDO | Default | d | 0.500 | |
PP3V8AON_PH1 | Default | d | 0.365 | |
PP3V8AON_PH2 | Default | d | 0.365 | |
PP3V8AON_PH3 | Default | d | 0.365 | |
PP3V8_AON | Default | d | 0.365 | |
PP3V8_AON_HDMI_BUCK | Default | d | 0.365 | |
PP3V8_AON_MPMU | Default | d | 0.365 | |
PP3V8_AON_SPMU | Default | d | 0.365 | |
PP3V8_AON_WLBT | Default | d | 0.365 | |
PP3V8_ATC01_LDO | Default | d | 0.370 | |
PP3V8_ATC01_VDDCIO_REG | Default | d | 0.370 | |
PP3V8_ATC01_VDDFIXED_REG | Default | d | 0.360 | |
PP3V8_ATC01_VDDIO_REG | Default | d | 0.000 | |
PP3V8_ATC2_LDO | Default | d | 0.365 | |
PP3V8_ATC2_VDDCIO_REG | Default | d | 0.360 | |
PP3V8_ATC2_VDDFIXED_REG | Default | d | 0.360 | |
PP3V8_ATC2_VDDIO_REG | Default | d | 0.355 | |
PP3V8_AWAKESW_TCON | Default | d | 0.545 | |
PP3V8_CODEC_VP | Default | d | 0.365 | |
PP3V8_HDMI_VDD_REG | Default | d | 0.360 | |
PP3V8_IPDLDO_VIN | Default | d | 0.365 | |
PP5V0_HDMI_DDC_CONN | Default | d | 0.580 | |
PP5V0_HDMI_DDC_LDSW | Default | d | 0.580 | |
PP5V0_S2SW_HDMI_D | Default | d | 0.730 | |
PP5V_AON_P3V8AON | Default | d | 0.520 | |
PP5V_CHGR | Default | d | 0.550 | |
PP5V_CHGR_SW | Default | d | 0.450 | |
PP5V_KBDBKLT | Default | d | 0.400 | |
PP5V_KBDBKLT_BEN_A | Default | d | 0.410 | |
PP5V_KBDBKLT_BEN_D | Default | d | 0.410 | |
PP5V_P1V8VDDH_DRMOS_VCC2 | Default | d | 0.400 | |
PP5V_S2SW_USBC01 | Default | d | 0.310 | |
PP5V_S2SW_USBC23 | Default | d | 0.455 | |
PP5V_S2_CAMERA | Default | d | 0.400 | |
PP5V_S2_HDMI | Default | d | 0.530 | |
PP5V_S2_HDMI_LDO | Default | d | 0.400 | |
PP5V_S2_LUXE_VDDA | Default | d | 0.410 | |
PP5V_S2_MAIN | Default | d | 0.400 | |
PP5V_S2_TPAD_CONN | Default | d | 0.400 | |
PPBCON_AWAKESW_BKLTCONN | Default | d | 0.710 | |
PPBCON_AWAKESW_BKLTCONN_VIN | Default | d | 0.720 | |
PPBUS_AON | Default | d | 0.490 | |
PPBUS_AON_LUXE | Default | d | 0.490 | |
PPBUS_AON_MPMU | Default | d | 0.490 | |
PPBUS_AON_P3V8AONISEN | Default | d | 0.555 | |
PPBUS_AON_SPKRAMP_ABC | Default | d | 0.490 | |
PPBUS_AON_SPKRAMP_DEF | Default | d | 0.490 | |
PPBUS_NAND0 | Default | d | 0.490 | |
PPBUS_NAND1 | Default | d | 0.490 | |
PPCHGR_VDDA | Default | d | 0.455 | |
PPCHGR_VDDP | Default | d | 0.450 | |
PPDCIN_AON | Default | d | 0.570 | |
PPDCIN_AON_CHGR_R | Default | d | 0.570 | |
PPHV_INT0_AONSW | Default | d | 0.570 | |
PPHV_INT1_AONSW | Default | d | 0.570 | |
PPHV_INT2_AONSW | Default | d | 0.570 | |
PPHV_INT5_AONSW | Default | d | 0.570 | |
PPLUXE_INPUT_R_V | Default | d | 0.490 | |
PPLUXE_LG1_S | Default | d | 0.000 | |
PPLUXE_LX1 | Default | d | 0.525 | |
PPLUXE_LX2 | Default | d | 0.525 | |
PPMDB_AWAKESW_TCON | Default | d | 0.545 | |
PPPANEL_PANEL_DISCHARGE | Default | d | 0.340 | |
PPVBAT_AON | Default | d | 1.620 | |
PPVBAT_AON_CHGR_R | Default | d | 0.490 | |
PPVBAT_AON_CHGR_REG | Default | d | 0.490 | |
PPVBUS_USBC0 | Default | d | 0.180 | |
PPVBUS_USBC1 | Default | d | 0.180 | |
PPVBUS_USBC2 | Default | d | 0.150 | |
PPVBUS_USBC5 | Default | d | 0.180 | |
PPVDD2H0_S2SW | Default | d | 0.035 | |
PPVDD2H0_S2SW | Default | r | 34.400R | |
PPVDD2H1_S2SW | Default | d | 0.035 | |
PPVDD2H1_S2SW | Default | r | 34.400R | |
PPVDDQ0_S1 | Default | d | 0.125 | |
PPVDDQ1_S1 | Default | d | 0.125 | |
PPVDD_AMPH0_S2SW | Default | d | 0.435 | |
PPVDD_AMPH1_S2SW | Default | d | 0.440 | |
PPVDD_AVEMSR_AWAKESW | Default | d | 0.255 | |
PPVDD_CIO_S2SW | Default | d | 0.215 | |
PPVDD_DCS_S1 | Default | d | 0.205 | |
PPVDD_DISP_AWAKESW | Default | d | 0.175 | |
PPVDD_ECPU_AWAKESW | Default | d | 0.215 | |
PPVDD_ECPU_SRAM_AWAKESW | Default | d | 0.345 | |
PPVDD_FIXED_S1 | Default | d | 0.220 | |
PPVDD_GPU_BMPR_S1 | Default | d | 0.270 | |
PPVDD_LDO_NAND0_OCARINA | Default | d | 0.365 | |
PPVDD_LOW_S2 | Default | d | 0.260 | |
PPVDD_P2V5VREF | Default | d | 0.400 | |
PPVDD_P3V8AONISEN | Default | d | 0.400 | |
PPVDD_SOC_S1 | Default | d | 0.140 | |
PPVDD_SRAM_S1 | Default | d | 0.215 | |
PPVDD_VPUMP_MPMU | Default | d | 0.710 | |
PPVDD_VPUMP_SPMU | Default | d | 0.710 | |
PPVIN_5VUSBC01 | Default | d | 0.490 | |
PPVIN_5VUSBC23 | Default | d | 0.490 | |
PPVIN_P1V8VDDH | Default | d | 0.490 | |
PPVIN_P3V3SD | Default | d | 0.490 | |
PPVIN_P3V8AON | Default | d | 0.490 | |
PPVIN_P3V8NAND0 | Default | d | 0.365 | |
PPVIN_P3V8NAND1 | Default | d | 0.560 | |
PPVIN_P5VS2 | Default | d | 0.490 | |
PPVOUT_KBDLED_CONN | Default | d | 0.590 | |
PPVOUT_LUXE | Default | d | 0.620 | |
PPVOUT_LUXE_XW | Default | d | 0.620 | |
PVBAT_ILIMIT_L | Default | d | 0.300 | |
PVDD1_PWR_EN | Default | d | 0.575 | |
PVOUT_LUXE_R | Default | d | 0.620 | |
QH900_D | Default | d | 0.515 | |
RF_ANT_0 | Default | r | 2.300R | |
RF_ANT_1 | Default | d | - | |
RF_ANT_1 | Default | r | 2.100R | |
RF_BT_DED_ANT | Default | r | 1.600R | |
ROM_UPC0_HOLD_L | Default | d | 0.665 | |
ROM_UPC0_WP_L | Default | d | 0.670 | |
ROM_UPC1_HOLD_L | Default | d | 0.660 | |
ROM_UPC1_WP_L | Default | d | 0.660 | |
ROM_UPC2_HOLD_L | Default | d | 0.700 | |
ROM_UPC2_WP_L | Default | d | 0.700 | |
ROM_UPC5_HOLD_L | Default | d | 0.705 | |
ROM_UPC5_WP_L | Default | d | 0.705 | |
RSLOC_RST_L | Default | d | 0.480 | |
RTMRMUX_OE_L | Default | d | OL | |
SAVE_BAT_G | Default | d | 0.765 | |
SAVE_BAT_S | Default | d | 1.620 | |
SDCONN_CLK_CONN | Default | d | 0.435 | |
SDCONN_CLK_CONN_FL | Default | d | 0.435 | |
SDCONN_CLK_R | Default | d | 0.435 | |
SDCONN_CMD | Default | d | 0.435 | |
SDCONN_CMD_R | Default | d | 0.435 | |
SDCONN_CMD_R_FL | Default | d | 0.435 | |
SDCONN_D0 | Default | d | 0.430 | |
SDCONN_D0_R | Default | d | 0.430 | |
SDCONN_D0_R_FL | Default | d | 0.430 | |
SDCONN_D1 | Default | d | 0.430 | |
SDCONN_D1_R | Default | d | 0.430 | |
SDCONN_D1_R_FL | Default | d | 0.430 | |
SDCONN_D2 | Default | d | 0.435 | |
SDCONN_D2_R | Default | d | 0.435 | |
SDCONN_D2_R_FL | Default | d | 0.435 | |
SDCONN_D3 | Default | d | 0.435 | |
SDCONN_D3_R | Default | d | 0.435 | |
SDCONN_D3_R_FL | Default | d | 0.435 | |
SDCONN_DETECT | Default | d | 0.022 | |
SDCONN_DETECT_R | Default | d | 0.000 | |
SDCONN_SD0_UHS2_N | Default | d | 0.315 | |
SDCONN_SD0_UHS2_P | Default | d | 0.315 | |
SDCONN_SD1_UHS2_N | Default | d | 0.315 | |
SDCONN_SD1_UHS2_P | Default | d | 0.315 | |
SDCONN_STATE_CHANGE | Default | d | 0.590 | |
SDCONN_WP | Default | d | 0.022 | |
SDCONN_WP_R | Default | d | 0.000 | |
SD_HS_IOUT | Default | d | OL | |
SD_HS_ISENSE | Default | d | 0.730 | |
SD_PWR_EN | Default | d | 0.570 | |
SD_UHS2_CLKREQ_L | Default | d | 0.300 | |
SD_UHS2_RESET_L | Default | d | 0.300 | |
SENSE_PPDCIN_DEBUG | Default | d | OL | |
SE_IRQ_WAKE | Default | d | 0.300 | |
SE_PWR_EN | Default | d | 0.750 | |
SGPIO_PMU_CLVR1_CLK | Default | d | 0.455 | |
SGPIO_PMU_CLVR1_DATA | Default | d | 0.455 | |
SGPIO_PMU_CLVR_CLK | Default | d | 0.455 | |
SGPIO_PMU_CLVR_CLK_R | Default | d | 0.475 | |
SGPIO_PMU_DATA | Default | d | 0.455 | |
SGPIO_PMU_DATA_R | Default | d | 0.475 | |
SGPIO_PMU_SPMU_CLK | Default | d | 0.725 | |
SGPIO_PMU_SPMU_CLK_R | Default | d | 0.730 | |
SGPIO_PMU_SPMU_DATA | Default | d | 0.475 | |
SMBUS_BATT_SCL | Default | d | 0.530 | |
SMBUS_BATT_SDA | Default | d | 0.520 | |
SMC_FAN_0_PWM | Default | d | 0.305 | |
SMC_FAN_0_TACH | Default | d | 0.305 | |
SMC_FAN_1_PWM | Default | d | 0.305 | |
SMC_FAN_1_TACH | Default | d | 0.300 | |
SMC_FIXTURE_MODE_L | Default | d | 0.300 | |
SOC_ATCPHY0_RCAL_N | Default | d | 0.395 | |
SOC_ATCPHY0_RCAL_P | Default | d | 0.510 | |
SOC_ATCPHY1_RCAL_N | Default | d | 0.395 | |
SOC_ATCPHY1_RCAL_P | Default | d | 0.510 | |
SOC_ATCPHY2_RCAL_N | Default | d | 0.395 | |
SOC_ATCPHY2_RCAL_P | Default | d | 0.515 | |
SOC_ATCPHY3_RCAL_N | Default | d | 0.395 | |
SOC_ATCPHY3_RCAL_P | Default | d | 0.510 | |
SOC_DBG_USB_RESREF | Default | d | 0.200 | |
SOC_DFU_STATUS | Default | d | 0.310 | |
SOC_DOCK_CONNECT | Default | d | 0.305 | |
SOC_DOCK_CONNECT_UPC | Default | d | 0.405 | |
SOC_DOMAIN_GPIO_GRP0 | Default | d | 0.305 | |
SOC_DOMAIN_HGPIO_GRP0_0 | Default | d | 0.300 | |
SOC_DOMAIN_NGPIO_AOP1_0 | Default | d | 0.300 | |
SOC_DOMAIN_SGPIO_GRP1 | Default | d | 0.310 | |
SOC_FORCE_DFU | Default | d | 0.305 | |
SOC_FORCE_DFU_DBG | Default | d | OL | |
SOC_HOLD_RESET | Default | d | 0.305 | |
SOC_JTAG_SEL | Default | d | 0.300 | |
SOC_JTAG_TDI | Default | d | 0.300 | |
SOC_KIS_DFU_SELECT | Default | d | OL | |
SOC_LPDPRX_RCAL_N | Default | d | 0.390 | |
SOC_LPDPRX_RCAL_P | Default | d | 0.510 | |
SOC_LPDPTX_RCAL_N | Default | d | 0.390 | |
SOC_LPDPTX_RCAL_P | Default | d | 0.510 | |
SOC_REQUEST_DFU1_L | Default | d | 0.300 | |
SOC_REQUEST_DFU2_L | Default | d | 0.300 | |
SOC_SOCHOT_L | Default | d | 0.300 | |
SOC_ST0_PCIE_RCAL_N | Default | d | 0.390 | |
SOC_ST0_PCIE_RCAL_P | Default | d | 0.510 | |
SOC_ST1_PCIE_RCAL_N | Default | d | 0.390 | |
SOC_ST1_PCIE_RCAL_P | Default | d | 0.510 | |
SOC_STOP_CLK_L | Default | d | 0.300 | |
SOC_TESTMODE | Default | d | 0.305 | |
SOC_THMSNS_1 | Default | d | 0.770 | |
SOC_USB_C0_RESREF | Default | d | 0.200 | |
SOC_USB_C1_RESREF | Default | d | 0.200 | |
SOC_USB_C2_RESREF | Default | d | 0.200 | |
SOC_USB_C3_RESREF | Default | d | 0.200 | |
SPI_AOP_GYRO_CLK | Default | d | 0.315 | |
SPI_AOP_GYRO_MISO | Default | d | 0.300 | |
SPI_AOP_GYRO_MISO_R | Default | d | 0.320 | |
SPI_AOP_GYRO_MOSI | Default | d | 0.320 | |
SPI_AOP_GYRO_MOSI_R | Default | d | 0.300 | |
SPI_AOP_GYRO_SCLK_R | Default | d | 0.300 | |
SPI_AOP_LAS_MISO_1V8 | Default | d | 0.810 | |
SPI_AOP_LAS_MISO_1V8_R | Default | d | 0.830 | |
SPI_AOP_LAS_MOSI_1V8 | Default | d | 0.510 | |
SPI_AOP_LAS_SCLK_1V8 | Default | d | 0.510 | |
SPI_AOP_SENSOR_MISO | Default | d | 0.310 | |
SPI_AOP_SENSOR_MISO_R | Default | d | 0.330 | |
SPI_AOP_SENSOR_MOSI | Default | d | 0.320 | |
SPI_AOP_SENSOR_MOSI_1V8_R | Default | d | 0.490 | |
SPI_AOP_SENSOR_MOSI_R | Default | d | 0.300 | |
SPI_AOP_SENSOR_SCLK | Default | d | 0.320 | |
SPI_AOP_SENSOR_SCLK_1V8_R | Default | d | 0.490 | |
SPI_AOP_SENSOR_SCLK_R | Default | d | 0.300 | |
SPI_ATCRTMR0_CLK | Default | d | 0.330 | |
SPI_ATCRTMR0_CLK_R | Default | d | 0.350 | |
SPI_ATCRTMR0_CS_L | Default | d | 0.330 | |
SPI_ATCRTMR0_DIO<0> | Default | d | 0.330 | |
SPI_ATCRTMR0_DIO<1> | Default | d | 0.330 | |
SPI_ATCRTMR0_DIO<2> | Default | d | 0.330 | |
SPI_ATCRTMR0_DIO<3> | Default | d | 0.330 | |
SPI_ATCRTMR0_R_DIO<0> | Default | d | 0.350 | |
SPI_ATCRTMR0_R_DIO<1> | Default | d | 0.350 | |
SPI_ATCRTMR0_R_DIO<2> | Default | d | 0.350 | |
SPI_ATCRTMR0_R_DIO<3> | Default | d | 0.350 | |
SPI_ATCRTMR1_CLK | Default | d | 0.330 | |
SPI_ATCRTMR1_CLK_R | Default | d | 0.355 | |
SPI_ATCRTMR1_CS_L | Default | d | 0.330 | |
SPI_ATCRTMR1_DIO<0> | Default | d | 0.330 | |
SPI_ATCRTMR1_DIO<1> | Default | d | 0.335 | |
SPI_ATCRTMR1_DIO<2> | Default | d | 0.335 | |
SPI_ATCRTMR1_DIO<3> | Default | d | 0.330 | |
SPI_ATCRTMR1_R_DIO<0> | Default | d | 0.355 | |
SPI_ATCRTMR1_R_DIO<1> | Default | d | 0.355 | |
SPI_ATCRTMR1_R_DIO<2> | Default | d | 0.355 | |
SPI_ATCRTMR1_R_DIO<3> | Default | d | 0.355 | |
SPI_ATCRTMR2_CLK | Default | d | 0.335 | |
SPI_ATCRTMR2_CLK_R | Default | d | 0.360 | |
SPI_ATCRTMR2_CS_L | Default | d | 0.335 | |
SPI_ATCRTMR2_DIO<0> | Default | d | 0.335 | |
SPI_ATCRTMR2_DIO<1> | Default | d | 0.335 | |
SPI_ATCRTMR2_DIO<2> | Default | d | 0.335 | |
SPI_ATCRTMR2_DIO<3> | Default | d | 0.335 | |
SPI_ATCRTMR2_R_DIO<0> | Default | d | 0.360 | |
SPI_ATCRTMR2_R_DIO<1> | Default | d | 0.360 | |
SPI_ATCRTMR2_R_DIO<2> | Default | d | 0.360 | |
SPI_ATCRTMR2_R_DIO<3> | Default | d | 0.360 | |
SPI_DISP_BKLT_CLK | Default | d | 0.330 | |
SPI_DISP_BKLT_CLK_CONN | Default | d | 0.330 | |
SPI_DISP_BKLT_CLK_R | Default | d | 0.310 | |
SPI_DISP_BKLT_CS_L | Default | d | 0.310 | |
SPI_DISP_BKLT_MISO | Default | d | 0.310 | |
SPI_DISP_BKLT_MISO_CONN | Default | d | 0.310 | |
SPI_DISP_BKLT_MOSI | Default | d | 0.330 | |
SPI_DISP_BKLT_MOSI_CONN | Default | d | 0.330 | |
SPI_DISP_BKLT_MOSI_R | Default | d | 0.310 | |
SPI_DP2HDMI_CLK | Default | d | 0.725 | |
SPI_DP2HDMI_CS_L | Default | d | 0.715 | |
SPI_DP2HDMI_DI | Default | d | 0.590 | |
SPI_DP2HDMI_DO | Default | d | 0.610 | |
SPI_DP2HDMI_HOLD_L | Default | d | 0.305 | |
SPI_DP2HDMI_HOLD_L_3V3 | Default | d | 0.460 | |
SPI_GYRO_CS_L | Default | d | 0.300 | |
SPI_IPD_CLK | Default | d | 0.320 | |
SPI_IPD_MCU_CS_L | Default | d | 0.300 | |
SPI_IPD_MISO | Default | d | 0.305 | |
SPI_IPD_MISO_R | Default | d | 0.325 | |
SPI_IPD_MOSI | Default | d | 0.320 | |
SPI_IPD_TOUCH_CS_CONN_L | Default | d | 0.480 | |
SPI_IPD_TOUCH_CS_CONN_R_L | Default | d | 0.460 | |
SPI_IPD_TOUCH_CS_L | Default | d | 0.300 | |
SPI_LAS_CS_1V8_L | Default | d | 0.465 | |
SPI_LAS_CS_L | Default | d | 0.310 | |
SPI_SOCROM_CLK | Default | d | 0.335 | |
SPI_SOCROM_CLK_R | Default | d | 0.310 | |
SPI_SOCROM_MOSI | Default | d | 0.330 | |
SPI_SOCROM_MOSI_R | Default | d | 0.310 | |
SPI_TCON_CLK | Default | d | 0.345 | |
SPI_TCON_CLK_CONN | Default | d | 0.340 | |
SPI_TCON_CLK_R | Default | d | 0.310 | |
SPI_TCON_CS_L | Default | d | 0.330 | |
SPI_TCON_CS_R_L | Default | d | 0.305 | |
SPI_TCON_MISO | Default | d | 0.310 | |
SPI_TCON_MISO_CONN | Default | d | 0.310 | |
SPI_TCON_MOSI | Default | d | 0.340 | |
SPI_TCON_MOSI_CONN | Default | d | 0.340 | |
SPI_TCON_MOSI_R | Default | d | 0.310 | |
SPI_TOUCHID_CLK | Default | d | 0.330 | |
SPI_TOUCHID_CLK_1V8 | Default | d | 0.520 | |
SPI_TOUCHID_CLK_1V8_CONN | Default | d | 0.520 | |
SPI_TOUCHID_CLK_1V8_R | Default | d | 0.490 | |
SPI_TOUCHID_CLK_R | Default | d | 0.310 | |
SPI_TOUCHID_MISO | Default | d | 0.310 | |
SPI_TOUCHID_MISO_1V8_CONN | Default | d | 0.805 | |
SPI_TOUCHID_MOSI | Default | d | 0.330 | |
SPI_TOUCHID_MOSI_1V8 | Default | d | 0.520 | |
SPI_TOUCHID_MOSI_1V8_CONN | Default | d | 0.520 | |
SPI_TOUCHID_MOSI_1V8_R | Default | d | 0.490 | |
SPI_TOUCHID_MOSI_R | Default | d | 0.310 | |
SPI_TPAD_CLK_CONN | Default | d | 0.525 | |
SPI_TPAD_CLK_CONN_R | Default | d | 0.505 | |
SPI_TPAD_MCU_CS_CONN_L | Default | d | 0.700 | |
SPI_TPAD_MCU_CS_CONN_R_L | Default | d | 0.680 | |
SPI_TPAD_MISO_CONN | Default | d | 0.505 | |
SPI_TPAD_MOSI_CONN | Default | d | 0.525 | |
SPI_TPAD_MOSI_CONN_R | Default | d | 0.505 | |
SPI_UPC0_CLK | Default | d | 0.695 | |
SPI_UPC0_CLK_DBG | Default | d | 0.795 | |
SPI_UPC0_CS_L | Default | d | 0.680 | |
SPI_UPC0_MISO | Default | d | 0.650 | |
SPI_UPC0_MOSI | Default | d | 0.660 | |
SPI_UPC0_R_CLK | Default | d | 0.695 | |
SPI_UPC0_R_CS_L | Default | d | 0.690 | |
SPI_UPC0_R_MISO | Default | d | 0.660 | |
SPI_UPC0_R_MOSI | Default | d | 0.670 | |
SPI_UPC1_CLK | Default | d | 0.690 | |
SPI_UPC1_CLK_DBG | Default | d | 0.795 | |
SPI_UPC1_CS_L | Default | d | 0.680 | |
SPI_UPC1_MISO | Default | d | 0.645 | |
SPI_UPC1_MOSI | Default | d | 0.660 | |
SPI_UPC1_R_CLK | Default | d | 0.690 | |
SPI_UPC1_R_CS_L | Default | d | 0.685 | |
SPI_UPC1_R_MISO | Default | d | 0.655 | |
SPI_UPC1_R_MOSI | Default | d | 0.675 | |
SPI_UPC2_CLK | Default | d | 0.605 | |
SPI_UPC2_CLK_DBG | Default | d | 0.700 | |
SPI_UPC2_CS_L | Default | d | 0.670 | |
SPI_UPC2_MISO | Default | d | 0.680 | |
SPI_UPC2_MOSI | Default | d | 0.690 | |
SPI_UPC2_R_CLK | Default | d | 0.620 | |
SPI_UPC2_R_CS_L | Default | d | 0.675 | |
SPI_UPC2_R_MISO | Default | d | 0.685 | |
SPI_UPC2_R_MOSI | Default | d | 0.690 | |
SPI_UPC5_CLK | Default | d | 0.605 | |
SPI_UPC5_CS_L | Default | d | 0.675 | |
SPI_UPC5_MISO | Default | d | 0.680 | |
SPI_UPC5_MOSI | Default | d | 0.685 | |
SPI_UPC5_R_CLK | Default | d | 0.620 | |
SPI_UPC5_R_CS_L | Default | d | 0.680 | |
SPI_UPC5_R_MISO | Default | d | 0.690 | |
SPI_UPC5_R_MOSI | Default | d | 0.690 | |
SPKRAMP_ABC_ICC | Default | d | 0.405 | |
SPKRAMP_A_ADDR | Default | d | 0.000 | |
SPKRAMP_A_BOOTN | Default | d | 0.730 | |
SPKRAMP_A_BOOTP | Default | d | 0.730 | |
SPKRAMP_A_DREG | Default | d | 0.555 | |
SPKRAMP_A_ICC_R | Default | d | 0.420 | |
SPKRAMP_A_OUTN | Default | d | 0.470 | |
SPKRAMP_A_OUTN_R | Default | d | 0.470 | |
SPKRAMP_A_OUTP | Default | d | 0.470 | |
SPKRAMP_A_OUTP_R | Default | d | 0.470 | |
SPKRAMP_B_ADDR | Default | d | 0.400 | |
SPKRAMP_B_BOOTN | Default | d | 0.730 | |
SPKRAMP_B_BOOTP | Default | d | 0.730 | |
SPKRAMP_B_DREG | Default | d | 0.555 | |
SPKRAMP_B_ICC_R | Default | d | 0.420 | |
SPKRAMP_B_OUTN | Default | d | 0.470 | |
SPKRAMP_B_OUTN_R | Default | d | 0.470 | |
SPKRAMP_B_OUTP | Default | d | 0.470 | |
SPKRAMP_B_OUTP_R | Default | d | 0.470 | |
SPKRAMP_C_ADDR | Default | d | 0.450 | |
SPKRAMP_C_BOOTN | Default | d | 0.730 | |
SPKRAMP_C_BOOTP | Default | d | 0.730 | |
SPKRAMP_C_DREG | Default | d | 0.555 | |
SPKRAMP_C_ICC_R | Default | d | 0.420 | |
SPKRAMP_C_OUTN | Default | d | 0.470 | |
SPKRAMP_C_OUTN_R | Default | d | 0.470 | |
SPKRAMP_C_OUTP | Default | d | 0.470 | |
SPKRAMP_C_OUTP_R | Default | d | 0.470 | |
SPKRAMP_DEF_ISENSE | Default | d | 0.735 | |
SPKRAMP_D_OUTN | Default | d | 0.480 | |
SPKRAMP_D_OUTN_R | Default | d | 0.480 | |
SPKRAMP_D_OUTP | Default | d | 0.480 | |
SPKRAMP_D_OUTP_R | Default | d | 0.480 | |
SPKRAMP_E_OUTN | Default | d | 0.480 | |
SPKRAMP_E_OUTN_R | Default | d | 0.480 | |
SPKRAMP_E_OUTP | Default | d | 0.480 | |
SPKRAMP_E_OUTP_R | Default | d | 0.480 | |
SPKRAMP_F_OUTN | Default | d | 0.480 | |
SPKRAMP_F_OUTN_R | Default | d | 0.480 | |
SPKRAMP_F_OUTP | Default | d | 0.480 | |
SPKRAMP_F_OUTP_R | Default | d | 0.480 | |
SPKRAMP_ICC | Default | d | 0.405 | |
SPKRAMP_INT_L | Default | d | 0.305 | |
SPKRAMP_RESET_L | Default | d | 0.305 | |
SPKR_ID0 | Default | d | 0.305 | |
SPKR_ID1 | Default | d | 0.310 | |
SPMI_CLVR0_CLK | Default | d | 0.340 | |
SPMI_CLVR0_CLK_R | Default | d | 0.305 | |
SPMI_CLVR0_DATA | Default | d | 0.340 | |
SPMI_CLVR0_DATA_R | Default | d | 0.305 | |
SPMI_DISP_BKLT_CLK | Default | d | 0.320 | |
SPMI_DISP_BKLT_CLK_R | Default | d | 0.305 | |
SPMI_DISP_BKLT_DATA | Default | d | 0.320 | |
SPMI_DISP_BKLT_DATA_R | Default | d | 0.305 | |
SPMI_NUB_MPMU_CLK | Default | d | 0.335 | |
SPMI_NUB_MPMU_CLK_R | Default | d | 0.300 | |
SPMI_NUB_MPMU_DATA | Default | d | 0.335 | |
SPMI_NUB_MPMU_DATA_R | Default | d | 0.300 | |
SPMI_NUB_P1V8VDDH_CLK | Default | d | 0.370 | |
SPMI_NUB_P1V8VDDH_DATA | Default | d | 0.360 | |
SPMI_NUB_SPMU_CLK | Default | d | 0.370 | |
SPMI_NUB_SPMU_DATA | Default | d | 0.370 | |
SPMI_NUB_SPMU_P1V8VDDH_CLK | Default | d | 0.320 | |
SPMI_NUB_SPMU_P1V8VDDH_CLK_R | Default | d | 0.300 | |
SPMI_NUB_SPMU_P1V8VDDH_DATA | Default | d | 0.320 | |
SPMI_NUB_SPMU_P1V8VDDH_DATA_R | Default | d | 0.300 | |
SPMI_SE_CLK | Default | d | 0.335 | |
SPMI_SE_DATA | Default | d | 0.335 | |
SPMI_WLBT_CLK | Default | d | 0.335 | |
SPMI_WLBT_CLK_R | Default | d | 0.300 | |
SPMI_WLBT_DATA | Default | d | 0.335 | |
SPMI_WLBT_DATA_R | Default | d | 0.300 | |
SPMU_3V8_ISENSE | Default | d | 0.730 | |
SPMU_BUCK0_FB | Default | d | 0.210 | |
SPMU_BUCK0_FB_R | Default | d | 0.210 | |
SPMU_BUCK0_LX0 | Default | d | 0.205 | |
SPMU_BUCK0_LX1 | Default | d | 0.205 | |
SPMU_BUCK0_LX2 | Default | d | 0.205 | |
SPMU_BUCK0_LX3 | Default | d | 0.205 | |
SPMU_BUCK10_FB | Default | d | 0.220 | |
SPMU_BUCK10_FB_R | Default | d | 0.225 | |
SPMU_BUCK10_LX0 | Default | d | 0.215 | |
SPMU_BUCK10_LX1 | Default | d | 0.215 | |
SPMU_BUCK10_LX2 | Default | d | 0.215 | |
SPMU_BUCK1_FB | Default | d | 0.130 | |
SPMU_BUCK1_FB_R | Default | d | 0.130 | |
SPMU_BUCK1_LX0 | Default | d | 0.125 | |
SPMU_BUCK1_LX1 | Default | d | 0.125 | |
SPMU_BUCK2_FB | Default | d | 0.345 | |
SPMU_BUCK2_FB_R | Default | d | 0.345 | |
SPMU_BUCK2_LX0 | Default | d | 0.345 | |
SPMU_BUCK3_FB | Default | d | 0.260 | |
SPMU_BUCK3_FB_R | Default | d | 0.260 | |
SPMU_BUCK3_LX0 | Default | d | 0.260 | |
SPMU_BUCK4_FB | Default | r | 0.370R | |
SPMU_BUCK4_FB_R | Default | d | 0.037 | |
SPMU_BUCK4_FB_R | Default | r | 37.000R | |
SPMU_BUCK4_LX0 | Default | d | 0.035 | |
SPMU_BUCK4_LX1 | Default | d | 0.035 | |
SPMU_BUCK4_LX2 | Default | d | 0.035 | |
SPMU_BUCK4_LX3 | Default | d | 0.035 | |
SPMU_BUCK5_FB | Default | d | 0.150 | |
SPMU_BUCK5_FB_R | Default | d | 0.150 | |
SPMU_BUCK5_LX0 | Default | d | 0.140 | |
SPMU_BUCK5_LX1 | Default | d | 0.140 | |
SPMU_BUCK5_LX2 | Default | d | 0.140 | |
SPMU_BUCK5_LX3 | Default | d | 0.140 | |
SPMU_BUCK6_FB | Default | d | 0.220 | |
SPMU_BUCK6_FB_R | Default | d | 0.220 | |
SPMU_BUCK6_LX0 | Default | d | 0.215 | |
SPMU_BUCK8_FB | Default | d | 0.240 | |
SPMU_BUCK8_FB_R | Default | d | 0.240 | |
SPMU_BUCK8_LX0 | Default | d | 0.245 | |
SPMU_BUCK9_FB | Default | d | 0.440 | |
SPMU_BUCK9_FB_R | Default | d | 0.470 | |
SPMU_BUCK9_LX0 | Default | d | 0.435 | |
SPMU_CRASH_L | Default | d | 0.750 | |
SPMU_IREF | Default | d | 0.750 | |
SPMU_TCAL | Default | d | 0.770 | |
SPMU_THERMCRASH_L | Default | d | 0.690 | |
SPMU_THMSNS | Default | d | 0.775 | |
SPMU_VREF1V2 | Default | d | 0.630 | |
SPMU_VSS_A_BUCK0 | Default | d | 0.000 | |
SPMU_VSS_A_BUCK4 | Default | d | 0.000 | |
SPMU_VSS_A_BUCK5 | Default | d | 0.000 | |
SWD_IPD_CLK_CONN | Default | d | OL | |
SWD_IPD_DATA_CONN | Default | d | OL | |
SWD_NAND0_S5E2_S5E3_SWCLK | Default | d | OL | |
SWD_NAND0_S5E2_S5E3_SWDIO | Default | d | OL | |
SWD_NAND0_SWCLK | Default | d | 0.305 | |
SWD_NAND0_SWCLK_R | Default | d | 0.295 | |
SWD_NAND0_SWDIO | Default | d | 0.300 | |
SWD_NAND0_SWDIO_R | Default | d | 0.295 | |
SWD_NAND1_SWCLK | Default | d | OL | |
SWD_NAND1_SWCLK_R | Default | d | 0.305 | |
SWD_NAND1_SWDIO | Default | d | OL | |
SWD_NAND1_SWDIO_R | Default | d | 0.305 | |
SWD_NUB_ATCRTMR0_SWCLK_R | Default | d | 0.290 | |
SWD_NUB_ATCRTMR0_SWDIO_R | Default | d | 0.290 | |
SWD_NUB_ATCRTMR1_SWCLK | Default | d | 0.310 | |
SWD_NUB_ATCRTMR1_SWCLK_R | Default | d | 0.295 | |
SWD_NUB_ATCRTMR1_SWDIO | Default | d | 0.315 | |
SWD_NUB_ATCRTMR1_SWDIO_R | Default | d | 0.295 | |
SWD_NUB_MPMU_SWCLK | Default | d | 0.370 | |
SWD_NUB_MPMU_SWDIO | Default | d | 0.370 | |
SWD_NUB_PMU_SWCLK | Default | d | 0.320 | |
SWD_NUB_PMU_SWDIO | Default | d | 0.320 | |
SWD_SOC_SWCLK | Default | d | 0.310 | |
SWD_SOC_SWCLK_R | Default | d | 0.300 | |
SWD_SOC_SWDIO | Default | d | 0.300 | |
SWD_SOC_SWDIO_R | Default | d | 0.305 | |
SWD_UPC_SWCLK0 | Default | d | 0.350 | |
SWD_UPC_SWCLK1 | Default | d | 0.350 | |
SWD_UPC_SWCLK_R | Default | d | 0.300 | |
SWD_UPC_SWDIO0 | Default | d | 0.305 | |
SWD_UPC_SWDIO0_R | Default | d | 0.300 | |
SWD_UPC_SWDIO1 | Default | d | 0.300 | |
SWD_UPC_SWDIO1_R | Default | d | 0.300 | |
SWD_UPC_SWDIO2 | Default | d | 0.300 | |
SWD_UPC_SWDIO2_R | Default | d | 0.300 | |
SWD_UPC_SWDIO3 | Default | d | 0.310 | |
SWD_UPC_SWDIO3_R | Default | d | 0.300 | |
SYS_ALIVE_BUFF | Default | d | OL | |
SYS_DETECT | Default | d | OL | |
SYS_DETECT_L | Default | d | 0.425 | |
TDM_CODEC_BCLK | Default | d | 0.330 | |
TDM_CODEC_BCLK_R | Default | d | 0.310 | |
TDM_CODEC_D2R | Default | d | 0.310 | |
TDM_CODEC_D2R_R | Default | d | 0.345 | |
TDM_CODEC_FSYNC | Default | d | 0.330 | |
TDM_CODEC_FSYNC_R | Default | d | 0.310 | |
TDM_CODEC_R2D | Default | d | 0.330 | |
TDM_CODEC_R2D_R | Default | d | 0.305 | |
TDM_SPKRAMP_A_D2R_R | Default | d | 0.340 | |
TDM_SPKRAMP_B_D2R_R | Default | d | 0.340 | |
TDM_SPKRAMP_C_D2R_R | Default | d | 0.340 | |
TDM_SPKRAMP_L_BCLK | Default | d | 0.325 | |
TDM_SPKRAMP_L_BCLK_R | Default | d | 0.310 | |
TDM_SPKRAMP_L_D2R | Default | d | 0.305 | |
TDM_SPKRAMP_L_FSYNC | Default | d | 0.330 | |
TDM_SPKRAMP_L_FSYNC_R | Default | d | 0.310 | |
TDM_SPKRAMP_L_R2D | Default | d | 0.330 | |
TDM_SPKRAMP_L_R2D_R | Default | d | 0.310 | |
TDM_SPKRAMP_R_BCLK | Default | d | 0.325 | |
TDM_SPKRAMP_R_BCLK_R | Default | d | 0.305 | |
TDM_SPKRAMP_R_D2R | Default | d | 0.310 | |
TDM_SPKRAMP_R_FSYNC | Default | d | 0.325 | |
TDM_SPKRAMP_R_FSYNC_R | Default | d | 0.310 | |
TDM_SPKRAMP_R_R2D | Default | d | 0.325 | |
TDM_SPKRAMP_R_R2D_R | Default | d | 0.310 | |
THMSNS_MPMU1_N | Default | d | 0.000 | |
THMSNS_MPMU1_P | Default | d | 0.775 | |
THMSNS_MPMU2_N | Default | d | 0.000 | |
THMSNS_MPMU2_P | Default | d | 0.770 | |
THMSNS_MPMU3_N | Default | d | 0.000 | |
THMSNS_MPMU3_P | Default | d | 0.770 | |
THMSNS_MPMU4_N | Default | d | 0.000 | |
THMSNS_MPMU4_P | Default | d | 0.770 | |
THMSNS_MPMU5_N | Default | d | 0.000 | |
THMSNS_MPMU5_P | Default | d | 0.770 | |
THMSNS_MPMU6_N | Default | d | 0.000 | |
THMSNS_MPMU6_P | Default | d | 0.770 | |
THMSNS_MPMU7_N | Default | d | 0.000 | |
THMSNS_MPMU7_P | Default | d | 0.770 | |
THMSNS_MPMU8_N | Default | d | 0.000 | |
THMSNS_MPMU8_P | Default | d | 0.770 | |
THMSNS_SPMU1_N | Default | d | 0.000 | |
THMSNS_SPMU1_P | Default | d | 0.775 | |
THMSNS_SPMU2_N | Default | d | 0.000 | |
THMSNS_SPMU2_P | Default | d | 0.775 | |
THMSNS_SPMU3_N | Default | d | 0.000 | |
THMSNS_SPMU3_P | Default | d | 0.775 | |
THMSNS_SPMU4_N | Default | d | 0.000 | |
THMSNS_SPMU4_P | Default | d | 0.775 | |
THMSNS_SPMU5_N | Default | d | 0.000 | |
THMSNS_SPMU5_P | Default | d | 0.775 | |
THMSNS_SPMU6_N | Default | d | 0.000 | |
THMSNS_SPMU6_P | Default | d | 0.775 | |
THMSNS_SPMU7_N | Default | d | 0.000 | |
THMSNS_SPMU7_P | Default | d | 0.775 | |
THMSNS_SPMU8_N | Default | d | 0.000 | |
THMSNS_SPMU8_P | Default | d | 0.775 | |
TOUCHID_BOOST_EN | Default | d | 0.540 | |
TOUCHID_BOOST_EN_CONN | Default | d | 0.540 | |
TOUCHID_INT | Default | d | 0.300 | |
TOUCHID_INT_1V8_CONN | Default | d | 0.970 | |
TPAD_KBD_WAKE_CONN_L | Default | d | 0.805 | |
TPT_ANALOGMUX_OUT0 | Default | d | 0.825 | |
TPT_AP_GPIO37 | Default | d | 0.310 | |
TPT_AP_GPIO39 | Default | d | 0.310 | |
TPT_BMON_IOUT | Default | d | OL | |
TPT_COBRA_GPIO6 | Default | d | 0.615 | |
TPT_JTAG_SOC_TRST_L | Default | d | 0.300 | |
TPT_MTR_FUNC2 | Default | d | 0.300 | |
TPT_MTR_FUNC6 | Default | d | 0.300 | |
TPT_MTR_FUNC7 | Default | d | 0.300 | |
TP_AOP_LEAP_MADI_IN | Default | d | 0.300 | |
TP_AOP_PDM_IN_CLK1 | Default | d | 0.300 | |
TP_ATCRTMR0_JTAG_TDI | Default | d | 0.330 | |
TP_ATCRTMR0_JTAG_TRESET | Default | d | 0.330 | |
TP_ATCRTMR1_JTAG_TDI | Default | d | 0.330 | |
TP_ATCRTMR1_JTAG_TRESET | Default | d | 0.330 | |
TP_FAN_0_OTP1 | Default | d | OL | |
TP_FAN_0_OTP2 | Default | d | OL | |
TP_FAN_1_OTP1 | Default | d | OL | |
TP_FAN_1_OTP2 | Default | d | OL | |
TP_MACAW0_DEBUG_SWDCLK | Default | d | 0.460 | |
TP_MACAW0_DEBUG_SWDDAT | Default | d | 0.460 | |
TP_MACAW1_DEBUG_SWDCLK | Default | d | 0.460 | |
TP_MACAW1_DEBUG_SWDDAT | Default | d | 0.460 | |
TP_MACAW2_DEBUG_SWDCLK | Default | d | 0.455 | |
TP_MACAW2_DEBUG_SWDDAT | Default | d | 0.455 | |
TP_MTP_I2C0_SCL | Default | d | 0.300 | |
TP_MTP_I2C0_SDA | Default | d | 0.300 | |
TP_NAND0_OCARINA_VCC_DET | Default | d | 0.760 | |
TP_NAND0_OCARINA_VEN2 | Default | d | 0.760 | |
TP_NAND0_S5E0_ANI0_VREF | Default | d | 0.570 | |
TP_NAND0_S5E0_ANI1_VREF | Default | d | 0.565 | |
TP_NAND0_S5E0_DROOP_L | Default | d | 0.340 | |
TP_NAND0_S5E0_JTAG_TDI | Default | d | 0.345 | |
TP_NAND0_S5E0_VPP | Default | d | 0.565 | |
TP_NAND0_S5E1_ANI0_VREF | Default | d | 0.620 | |
TP_NAND0_S5E1_ANI1_VREF | Default | d | 0.610 | |
TP_NAND0_S5E1_DROOP_L | Default | d | 0.370 | |
TP_NAND0_S5E1_VPP | Default | d | 0.565 | |
TP_NAND0_S5E2_ANI1_VREF | Default | d | OL | |
TP_NAND0_S5E2_DROOP_L | Default | d | OL | |
TP_NAND0_S5E3_ANI0_VREF | Default | d | OL | |
TP_NAND0_S5E3_ANI1_VREF | Default | d | OL | |
TP_NAND0_S5E3_DROOP_L | Default | d | OL | |
TP_NAND0_S5E3_JTAG_TDO | Default | d | OL | |
TP_NAND0_S5E3_VPP | Default | d | OL | |
TP_NAND1_OCARINA_VCC_DET | Default | d | OL | |
TP_NAND1_OCARINA_VEN2 | Default | d | OL | |
TP_NAND1_S5E0_DROOP_L | Default | d | OL | |
TP_SE_NFC_GPIO0 | Default | d | 0.555 | |
TP_SE_NFC_GPIO1 | Default | d | 0.555 | |
TP_SPKRAMP_A_LV_EN | Default | d | 0.465 | |
TP_SPKRAMP_B_LV_EN | Default | d | 0.465 | |
TP_SPKRAMP_C_LV_EN | Default | d | 0.465 | |
TP_SPKRAMP_D_LV_EN | Default | d | 0.460 | |
TP_SPKRAMP_E_LV_EN | Default | d | 0.460 | |
TP_SPKRAMP_F_LV_EN | Default | d | 0.460 | |
TP_USB0_3V3_LDO_EN_VITC | Default | d | OL | |
TP_USBC0_PP20V | Default | d | OL | |
TP_USBC1_PP20V | Default | d | OL | |
TP_USBC2_PP20V | Default | d | OL | |
TP_WLAN_JTAG_TCK | Default | d | 0.620 | |
TP_WLAN_JTAG_TDI | Default | d | 0.620 | |
TP_WLAN_JTAG_TDO | Default | d | 0.620 | |
TP_WLAN_JTAG_TMS | Default | d | 0.620 | |
TP_WLAN_JTAG_TRSTN | Default | d | 0.620 | |
UART_DEBUGPRT_D2R | Default | d | 0.310 | |
UART_DEBUGPRT_R2D | Default | d | 0.305 | |
UART_DP2HDMI_D2R | Default | d | 0.305 | |
UART_DP2HDMI_R2D | Default | d | 0.305 | |
UART_DP2HDMI_TXD_R | Default | d | 0.310 | |
UART_SMC_DEBUGPRT_D2R | Default | d | 0.305 | |
UART_SMC_DEBUGPRT_R2D | Default | d | 0.305 | |
UART_TCON_D2R | Default | d | 0.310 | |
UART_TCON_D2R_1V8 | Default | d | 0.800 | |
UART_UPC5 | Default | d | 0.550 | |
UH903_EN | Default | d | 0.580 | |
UH903_FB | Default | d | 0.725 | |
UH903_FB_INT | Default | d | OL | |
UK700_EN | Default | d | 0.605 | |
UPC01_5V_EN | Default | d | 0.640 | |
UPC0_ATCRTMR01_PWR_EN | Default | d | 0.540 | |
UPC0_CHGR_AUX_DET_SHORT | Default | d | 0.590 | |
UPC0_R_OSC | Default | d | 0.465 | |
UPC0_SER_DBG | Default | d | 0.675 | |
UPC0_SS | Default | d | 0.580 | |
UPC1_ATCRTMR01_PWR_EN | Default | d | 0.555 | |
UPC1_CHGR_AUX_DET_SHORT | Default | d | 0.600 | |
UPC1_R_OSC | Default | d | 0.465 | |
UPC1_SER_DBG | Default | d | 0.690 | |
UPC1_SS | Default | d | 0.580 | |
UPC23_5V_EN | Default | d | 0.675 | |
UPC2_ATCRTMR2_PWR_EN | Default | d | 0.535 | |
UPC2_CHGR_AUX_DET_SHORT | Default | d | 0.590 | |
UPC2_I2C_ADDR | Default | d | 0.000 | |
UPC2_I2C_ADDR | Default | r | 0.300R | |
UPC2_R_OSC | Default | d | 0.475 | |
UPC2_SER_DBG | Default | d | 0.660 | |
UPC2_SS | Default | d | 0.580 | |
UPC5_GPIO1 | Default | d | 0.700 | |
UPC5_GPIO10 | Default | d | 0.720 | |
UPC5_GPIO2 | Default | d | 0.705 | |
UPC5_GPIO3 | Default | d | 0.690 | |
UPC5_GPIO4 | Default | d | 0.700 | |
UPC5_GPIO5 | Default | d | 0.690 | |
UPC5_GPIO6 | Default | d | 0.600 | |
UPC5_GPIO7 | Default | d | 0.715 | |
UPC5_GPIO8 | Default | d | 0.700 | |
UPC5_GPIO9 | Default | d | 0.715 | |
UPC5_I2C_ADDR | Default | d | 0.590 | |
UPC5_LV | Default | d | 0.510 | |
UPC5_R_OSC | Default | d | 0.465 | |
UPC5_SER_DBG | Default | d | 0.690 | |
UPC5_SS | Default | d | 0.580 | |
UPC_I2C_INT_L | Default | d | 0.280 | |
UPC_PMU_RESET_1V2 | Default | d | 0.610 | |
UPC_PMU_RESET_1V2_DBG | Default | d | OL | |
UPC_PMU_RESET_1V2_R | Default | d | 0.615 | |
UPC_SMC_I2C_INT_L | Default | d | 0.305 | |
USB2_ATC0_LS_MUX_N | Default | d | 0.480 | |
USB2_ATC0_LS_MUX_P | Default | d | 0.480 | |
USB2_ATC0_LS_N | Default | d | 0.480 | |
USB2_ATC0_LS_P | Default | d | 0.485 | |
USB2_ATC1_LS_N | Default | d | 0.485 | |
USB2_ATC1_LS_P | Default | d | 0.485 | |
USB2_ATC2_LS_N | Default | d | 0.480 | |
USB2_ATC2_LS_P | Default | d | 0.480 | |
USB2_UPC0_P1_N | Default | d | 0.480 | |
USB2_UPC0_P1_P | Default | d | 0.485 | |
USB2_UPC1_P1_N | Default | d | 0.485 | |
USB2_UPC1_P1_P | Default | d | 0.485 | |
USB2_UPC2_P1_N | Default | d | 0.480 | |
USB2_UPC2_P1_P | Default | d | 0.480 | |
USBC0_CC1 | Default | d | 0.460 | |
USBC0_CC1_CONN | Default | d | 0.630 | |
USBC0_CC2 | Default | d | 0.460 | |
USBC0_CC2_CONN | Default | d | 0.630 | |
USBC0_CIO_LSRX_3V3 | Default | d | 0.500 | |
USBC0_CIO_LSTX | Default | d | 0.340 | |
USBC0_CIO_LSTX_3V3 | Default | d | 0.500 | |
USBC0_D2R_CR_N<1> | Default | d | OL | |
USBC0_D2R_CR_N<2> | Default | d | OL | |
USBC0_D2R_CR_P<1> | Default | d | OL | |
USBC0_D2R_CR_P<2> | Default | d | OL | |
USBC0_R2D_N<1> | Default | d | OL | |
USBC0_R2D_N<2> | Default | d | OL | |
USBC0_R2D_P<1> | Default | d | OL | |
USBC0_R2D_P<2> | Default | d | OL | |
USBC0_SBU1 | Default | d | 0.660 | |
USBC0_SBU2 | Default | d | 0.660 | |
USBC0_USB_BOT_N | Default | d | 0.765 | |
USBC0_USB_BOT_P | Default | d | 0.765 | |
USBC0_USB_TOP_N | Default | d | 0.765 | |
USBC0_USB_TOP_P | Default | d | 0.765 | |
USBC0_VBIAS_PRT | Default | d | 0.630 | |
USBC1_CC1 | Default | d | 0.460 | |
USBC1_CC1_CONN | Default | d | 0.630 | |
USBC1_CC2 | Default | d | 0.460 | |
USBC1_CC2_CONN | Default | d | 0.630 | |
USBC1_CIO_LSRX_3V3 | Default | d | 0.495 | |
USBC1_CIO_LSTX | Default | d | 0.325 | |
USBC1_CIO_LSTX_3V3 | Default | d | 0.495 | |
USBC1_D2R_CR_N<1> | Default | d | OL | |
USBC1_D2R_CR_N<2> | Default | d | OL | |
USBC1_D2R_CR_P<1> | Default | d | OL | |
USBC1_D2R_CR_P<2> | Default | d | OL | |
USBC1_R2D_N<1> | Default | d | OL | |
USBC1_R2D_N<2> | Default | d | OL | |
USBC1_R2D_P<1> | Default | d | OL | |
USBC1_R2D_P<2> | Default | d | OL | |
USBC1_SBU1 | Default | d | 0.660 | |
USBC1_SBU2 | Default | d | 0.660 | |
USBC1_USB_BOT_N | Default | d | 0.765 | |
USBC1_USB_BOT_P | Default | d | 0.765 | |
USBC1_USB_TOP_N | Default | d | 0.765 | |
USBC1_USB_TOP_P | Default | d | 0.765 | |
USBC1_VBIAS_PRT | Default | d | 0.630 | |
USBC2_AUX_C_N | Default | d | 0.770 | |
USBC2_AUX_C_P | Default | d | 0.770 | |
USBC2_AUX_N | Default | d | 0.345 | |
USBC2_AUX_P | Default | d | 0.345 | |
USBC2_CC1 | Default | d | 0.460 | |
USBC2_CC1_CONN | Default | d | 0.625 | |
USBC2_CC2 | Default | d | 0.460 | |
USBC2_CC2_CONN | Default | d | 0.625 | |
USBC2_CIO_LSRX_3V3 | Default | d | 0.495 | |
USBC2_CIO_LSTX | Default | d | 0.330 | |
USBC2_CIO_LSTX_3V3 | Default | d | 0.495 | |
USBC2_D2R_CR_N<1> | Default | d | OL | |
USBC2_D2R_CR_N<2> | Default | d | OL | |
USBC2_D2R_CR_P<1> | Default | d | OL | |
USBC2_D2R_CR_P<2> | Default | d | OL | |
USBC2_R2D_N<1> | Default | d | OL | |
USBC2_R2D_N<2> | Default | d | OL | |
USBC2_R2D_P<1> | Default | d | OL | |
USBC2_R2D_P<2> | Default | d | OL | |
USBC2_SBU1 | Default | d | 0.650 | |
USBC2_SBU2 | Default | d | 0.650 | |
USBC2_USB_BOT_N | Default | d | 0.765 | |
USBC2_USB_BOT_P | Default | d | 0.765 | |
USBC2_USB_TOP_N | Default | d | 0.765 | |
USBC2_USB_TOP_P | Default | d | 0.765 | |
USBC2_VBIAS_PRT | Default | d | 0.625 | |
USBC5_CC1 | Default | d | 0.575 | |
USBC5_CC2 | Default | d | 0.575 | |
USB_DBG_LS_MUX_N | Default | d | 0.480 | |
USB_DBG_LS_MUX_P | Default | d | 0.480 | |
USB_DBG_LS_N | Default | d | 0.485 | |
USB_DBG_LS_P | Default | d | 0.485 | |
VDDA0_SE | Default | d | 0.485 | |
VDDA_SE | Default | d | 0.265 | |
VDDC_SE | Default | d | 0.265 | |
VDDNV_SE | Default | d | 0.490 | |
VDDRF_SE | Default | d | 0.480 | |
VDD_FIXED_XTAL_ATC0_F | Default | d | 0.320 | |
VDD_FIXED_XTAL_ATC1_F | Default | d | 0.320 | |
VDD_FIXED_XTAL_ATC2_F | Default | d | 0.365 | |
VREFB_ATC0 | Default | d | 0.530 | |
VREFB_ATC1 | Default | d | 0.530 | |
VREFB_ATC2 | Default | d | 0.435 | |
VREF_SE | Default | d | 0.790 | |
VSNS_PVDD2H1_SENSE1_N | Default | d | 0.000 | |
VSNS_PVDD2H1_SENSE1_P | Default | d | 0.000 | |
VSNS_PVDD2H1_SENSE3_N | Default | d | 0.000 | |
VSNS_PVDD2H1_SENSE3_N | Default | r | 0.600R | |
VSNS_PVDD2H1_SENSE3_P | Default | d | 0.035 | |
VSNS_PVDD2H1_SENSE3_P | Default | r | 34.600R | |
VSNS_PVDDAFRCS_SENSE | Default | d | 0.125 | |
VSNS_PVDDANE_SENSE | Default | d | 0.225 | |
VSNS_PVDDDISP_SENSE | Default | d | 0.170 | |
VSNS_PVDDFABRIC_SENSE | Default | d | 0.015 | |
VSNS_PVDDFABRIC_SENSE | Default | r | 15.600R | |
VSNS_PVDDGPU0_SENSE | Default | d | 0.007 | |
VSNS_PVDDGPU0_SENSE | Default | r | 7.200R | |
VSNS_PVDDSRAM_SENSE | Default | d | 0.220 | |
VSNS_PVSS_SENSE | Default | d | 0.000 | |
WING_L_THMSNS | Default | d | 0.770 | |
WING_R_THMSNS | Default | d | 0.770 | |
WLAN_JTAG_SEL | Default | d | 0.620 | |
WLAN_TIME_SYNC | Default | d | 0.310 | |
WLBT_3V8_IOUT | Default | d | OL | |
WLBT_3V8_ISENSE | Default | d | 0.735 | |
WLBT_CLKREQ_L | Default | d | 0.300 | |
WLBT_CLKREQ_R_L | Default | d | 0.515 | |
WLBT_PWR_EN | Default | d | 0.470 | |
WLBT_RESET_L | Default | d | 0.300 | |
WLBT_THMSNS | Default | d | 0.775 | |
WLBT_WAKE | Default | d | 0.630 | |
WL_GPIO_7 | Default | d | 0.620 | |