| Netname | Condition | Type | Value | Comment |
|---|---|---|---|---|
| 5V3V3_REG_EN | Default | d | 0.72 | |
| 5V3V3_REG_EN | Default | v | 3.40 | |
| ADAPTER_SENSE | Default | d | 0.612 | |
| ADAPTER_SENSE | Default | v | 2.900 | |
| ALL_SYS_PWRGD | Default | d | 0.49 | |
| AP_CLKREQ_Q_L | Default | d | 0.479 | |
| AP_RESET_CONN_L | Default | d | 0.482 | |
| AP_TEMP_SMB_SCL_R | Default | d | 0.755 | |
| AUD_CONNJ1_RING | Default | d | 0.648 | |
| AUD_CONNJ1_TIP | Default | d | 0.689 | |
| AUD_CONNJ1_TIPDET | Default | d | 0.733 | |
| AUD_CONNJ1_USGND | Default | d | 0.000 | |
| AUD_CONNJ1_USGND_DET | Default | d | OL | |
| AUD_CONNJ1_USMIC | Default | d | 0.000 | |
| AUD_SPDIF_OUT | Default | d | 0.662 | |
| BTMUX_SEL | Default | d | 0.515 | |
| BTMUX_SEL | Default | v | 3.300 | |
| CHGR_ACIN | Default | d | 0.54 | |
| CHGR_ACIN | Default | v | 3.910 | |
| CHGR_AGATE | Default | d | 0.65 | |
| CHGR_AGATE | Default | v | 0.000 | |
| CHGR_AMON | Default | d | 0.72 | |
| CHGR_AMON | Default | v | 0.350 | |
| CHGR_BGATE | Default | d | 0.67 | |
| CHGR_BGATE | Default | v | 5.170 | |
| CHGR_BMON | Default | d | 0.73 | |
| CHGR_BMON | Default | v | 0.060 | |
| CHGR_BOOT | Default | d | 0.59 | |
| CHGR_BOOT | Default | v | 17.360 | |
| CHGR_CELL | Default | d | 0.71 | |
| CHGR_CELL | Default | v | 3.480 | |
| CHGR_CSI_N | Default | d | 0.64 | |
| CHGR_CSI_N | Default | v | 16.510 | |
| CHGR_CSI_P | Default | d | 0.63 | |
| CHGR_CSI_P | Default | v | 16.530 | |
| CHGR_CSO_N | Default | d | 0.45 | |
| CHGR_CSO_N | Default | v | 12.590 | |
| CHGR_CSO_P | Default | d | 0.45 | |
| CHGR_CSO_P | Default | v | 12.590 | |
| CHGR_CSO_R_N | Default | d | 0.450 | |
| CHGR_CSO_R_P | Default | d | 0.450 | |
| CHGR_ICOMP | Default | d | 0.73 | |
| CHGR_ICOMP | Default | v | 2.110 | |
| CHGR_LGATE | Default | d | 0.46 | |
| CHGR_LGATE | Default | v | 0.940 | |
| CHGR_PHASE | Default | d | 0.45 | |
| CHGR_PHASE | Default | v | 12.670 | |
| CHGR_RST_L | Default | d | 0.50 | |
| CHGR_RST_L | Default | v | 3.440 | |
| CHGR_SGATE | Default | d | 0.656 | |
| CHGR_SGATE | Default | v | 0.020 | |
| CHGR_UGATE | Default | d | 0.92 | |
| CHGR_UGATE | Default | v | 16.210 | |
| CHGR_VCOMP | Default | d | 0.72 | |
| CHGR_VCOMP | Default | v | 1.860 | |
| CHGR_VFRQ | Default | d | 0.53 | |
| CHGR_VFRQ | Default | v | 0.000 | |
| CHGR_VNEG | Default | d | 0.54 | |
| CHGR_VNEG | Default | v | 2.090 | |
| CPUIMVP_AXG_PGOOD | Default | d | 0.62 | |
| CPUIMVP_AXG_PWM2 | Default | d | 0.62 | |
| CPUIMVP_BOOT1 | Default | d | 0.60 | |
| CPUIMVP_BOOT1G | Default | d | 0.60 | |
| CPUIMVP_BOOT2 | Default | d | 0.60 | |
| CPUIMVP_FBA | Default | d | 0.67 | |
| CPUIMVP_FBB | Default | d | 0.67 | |
| CPUIMVP_IMAXA | Default | d | 0.64 | |
| CPUIMVP_IMAXB | Default | d | 0.61 | |
| CPUIMVP_ISNS1G_N | Default | d | 0.012 | |
| CPUIMVP_ISNS1G_P | Default | d | 0.012 | |
| CPUIMVP_ISNS1G_P | Default | r | 11.500R | |
| CPUIMVP_ISNS1_N | Default | d | 0.010 | |
| CPUIMVP_ISNS1_P | Default | d | 0.010 | |
| CPUIMVP_ISNS2G_N | Default | d | 0.012 | |
| CPUIMVP_ISNS2G_P | Default | d | 0.012 | |
| CPUIMVP_ISNS2_N | Default | d | 0.010 | |
| CPUIMVP_ISNS2_N | Default | r | 9.600R | |
| CPUIMVP_ISNS2_P | Default | d | 0.010 | |
| CPUIMVP_ISNS2_P | Default | r | 9.600R | |
| CPUIMVP_ISUM | Default | d | 0.10 | |
| CPUIMVP_ISUM1_P | Default | d | 0.04 | |
| CPUIMVP_ISUM2_P | Default | d | 0.05 | |
| CPUIMVP_ISUMG1_P | Default | d | 0.05 | |
| CPUIMVP_ISUMG2_P | Default | d | 0.38 | |
| CPUIMVP_ISUMG_AVE_P | Default | d | 0.10 | |
| CPUIMVP_ISUMG_N | Default | d | 0.01 | |
| CPUIMVP_ISUM_N | Default | d | 0.00 | |
| CPUIMVP_LGATE1 | Default | d | 0.56 | |
| CPUIMVP_LGATE1G | Default | d | 0.56 | |
| CPUIMVP_LGATE2 | Default | d | 0.52 | |
| CPUIMVP_NTC | Default | d | 0.61 | |
| CPUIMVP_NTCG | Default | d | 0.68 | |
| CPUIMVP_PGOOD | Default | d | 0.60 | |
| CPUIMVP_PHASE1 | Default | d | 0.00 | |
| CPUIMVP_PHASE1G | Default | d | 0.00 | |
| CPUIMVP_PHASE2 | Default | d | 0.00 | |
| CPUIMVP_SLEW | Default | d | 0.69 | |
| CPUIMVP_TONA | Default | d | 0.67 | |
| CPUIMVP_TONB | Default | d | 0.67 | |
| CPUIMVP_UGATE1 | Default | d | 0.68 | |
| CPUIMVP_UGATE1G | Default | d | 0.68 | |
| CPUIMVP_UGATE2 | Default | d | 0.68 | |
| CPUIMVP_VR_ON | Default | d | 0.49 | |
| CPUIMVP_VSWG | Default | d | 0.012 | |
| CPUIMVP_VSWG2 | Default | d | 0.012 | |
| CPUTHMSNS_ALERT_L | Default | d | 0.74 | |
| CPUTHMSNS_THM_L | Default | d | 0.75 | |
| CPUVCCIOS0_AGND | Default | d | 0.00 | |
| CPUVCCIOS0_CS_N | Default | d | 0.013 | |
| CPUVCCIOS0_CS_P | Default | d | 0.013 | |
| CPUVCCIOS0_DRVH | Default | d | 0.55 | |
| CPUVCCIOS0_DRVL | Default | d | 0.44 | |
| CPUVCCIOS0_EN | Default | d | 0.52 | |
| CPUVCCIOS0_FB | Default | d | 0.51 | |
| CPUVCCIOS0_FSEL | Default | d | 0.00 | |
| CPUVCCIOS0_LL | Default | d | 0.013 | |
| CPUVCCIOS0_LL | Default | r | 12.500R | |
| CPUVCCIOS0_LL | Default | v | 1.000 | |
| CPUVCCIOS0_OCSET | Default | d | 0.52 | |
| CPUVCCIOS0_PGOOD | Default | d | 0.50 | |
| CPUVCCIOS0_RTN | Default | d | 0.51 | |
| CPUVCCIOS0_SREF | Default | d | 0.53 | |
| CPUVCCIOS0_VBST | Default | d | 0.53 | |
| CPUVCCIOS0_VO | Default | d | 0.52 | |
| CPU_AXG_SENSE_R | Default | d | 0.01 | |
| CPU_PROCHOT_L | Default | d | 0.07 | |
| CPU_VCCSASENSE_DIV | Default | d | 0.50 | |
| CPU_VCCSA_VID<0> | Default | d | 0.37 | |
| CPU_VCCSA_VID<1> | Default | d | 0.36 | |
| CPU_VCCSENSE_R | Default | d | 0.01 | |
| CPU_VIDALERT_L | Default | d | 0.08 | |
| CPU_VIDSCLK | Default | d | 0.06 | |
| CPU_VIDSOUT | Default | d | 0.07 | |
| DDRREG_1V8_VREF | Default | d | 0.64 | |
| DDRREG_DRVH | Default | d | 0.62 | |
| DDRREG_DRVL | Default | d | 0.45 | |
| DDRREG_EN | Default | d | 0.47 | |
| DDRREG_FB | Default | d | 0.69 | |
| DDRREG_LL | Default | d | 0.127 | |
| DDRREG_LL | Default | r | 126.000 | |
| DDRREG_LL | Default | v | 1.500 | |
| DDRREG_MODE | Default | d | 0.53 | |
| DDRREG_TRIP | Default | d | 0.74 | |
| DDRREG_VBST | Default | d | 0.61 | |
| DDRREG_VDDQSNS | Default | d | 0.14 | |
| DDRREG_VTTSNS | Default | d | 0.46 | |
| FW_5KPD_DET_RC | Default | d | OL | |
| FW_PWR_EN | Default | d | 0.45 | |
| FW_PWR_EN_L | Default | d | 0.43 | |
| GND | Default | v | 0.002 | |
| GND_CHASSIS_AUDIO_JACK | Default | d | - | |
| GND_CPUIMVP_SGND | Default | d | 0.00 | |
| IR_RX_OUT | Default | d | 0.71 | |
| ISNS_1V5_S3_DDR_N | Default | d | 0.127 | |
| ISNS_1V5_S3_DDR_N | Default | r | 126.000 | |
| ISNS_1V5_S3_DDR_P | Default | d | 0.127 | |
| ISNS_1V5_S3_DDR_P | Default | r | 126.000 | |
| LCD_IG_PWR_EN | Default | d | 0.58 | |
| LED_RETURN_1 | Default | d | 0.63 | |
| LED_RETURN_2 | Default | d | 0.63 | |
| LED_RETURN_3 | Default | d | 0.63 | |
| LED_RETURN_4 | Default | d | 0.63 | |
| LED_RETURN_5 | Default | d | 0.63 | |
| LED_RETURN_6 | Default | d | 0.63 | |
| LVDS_CONN_A_CLK_F_N | Default | d | 0.66 | |
| LVDS_CONN_A_CLK_F_P | Default | d | 0.66 | |
| LVDS_DDC_CLK | Default | d | 0.62 | |
| LVDS_DDC_DATA | Default | d | 0.62 | |
| LVDS_IG_A_DATA_N<0> | Default | d | 0.65 | |
| LVDS_IG_A_DATA_N<1> | Default | d | 0.65 | |
| LVDS_IG_A_DATA_N<2> | Default | d | 0.65 | |
| LVDS_IG_A_DATA_P<0> | Default | d | 0.65 | |
| LVDS_IG_A_DATA_P<1> | Default | d | 0.65 | |
| LVDS_IG_A_DATA_P<2> | Default | d | 0.65 | |
| MEMVTT_EN | Default | d | 0.45 | |
| P18V5_DCIN_CONN_R | Default | d | 2.900 | |
| P18V5_DCIN_CONN_R | Default | v | 16.700 | |
| P1V8S0_SW | Default | d | 0.120 | |
| P3V3S5_DRVH | Default | d | 0.64 | |
| P3V3S5_DRVH | Default | v | 3.90 | |
| P3V3S5_DRVL | Default | d | 0.45 | |
| P3V3S5_ENTRIP | Default | d | 0.45 | |
| P3V3S5_ENTRIP | Default | v | 0.70 | |
| P3V3S5_LL | Default | d | 0.13 | |
| P3V3S5_LL | Default | v | 3.30 | |
| P3V3S5_VBST | Default | d | 0.59 | |
| P3V3S5_VBST | Default | v | 7.70 | |
| P3V3S5_VFB | Default | d | 0.72 | |
| P3V3S5_VFB | Default | v | 2.00 | |
| P3V3S5_VO2 | Default | d | 0.13 | |
| P3V3S5_VO2 | Default | v | 3.30 | |
| P3V42G3H_FB | Default | d | 0.558 | |
| P3V42G3H_FB | Default | v | 3.480 | |
| P3V42G3H_REF3 | Default | d | 0.878 | |
| P3V42G3H_REF3 | Default | v | 3.300 | |
| P3V42G3H_SW | Default | d | 0.350 | |
| P3V42G3H_SW | Default | v | 3.500 | |
| P3V42G3H_TON | Default | v | 15.000 | |
| P5V3V3_PGOOD | Default | d | 0.59 | |
| P5V3V3_PGOOD | Default | v | 3.30 | |
| P5V3V3_REG_EN | Default | v | 3.400 | |
| P5VP3V3_REG3 | Default | d | 0.64 | |
| P5VP3V3_REG3 | Default | v | 3.30 | |
| P5VP3V3_VREF | Default | d | 0.68 | |
| P5VP3V3_VREF | Default | v | 2.00 | |
| P5VS3_DRVH | Default | d | 0.87 | |
| P5VS3_DRVH | Default | v | 5.50 | |
| P5VS3_DRVL | Default | d | 0.45 | |
| P5VS3_DRVL | Default | v | 0.60 | |
| P5VS3_ENTRIP | Default | d | 0.44 | |
| P5VS3_ENTRIP | Default | v | 1.10 | |
| P5VS3_EN_L | Default | v | 3.400 | |
| P5VS3_LL | Default | d | 0.43 | |
| P5VS3_LL | Default | v | 5.00 | |
| P5VS3_VBST | Default | d | 0.61 | |
| P5VS3_VBST | Default | v | 9.90 | |
| P5VS3_VFB | Default | d | 0.72 | |
| P5VS3_VFB | Default | v | 2.00 | |
| P5VS3_VO1 | Default | d | 0.43 | |
| P5VS3_VO1 | Default | v | 5.00 | |
| PBUS_G3H_R | Default | d | 0.467 | |
| PBUS_G3H_R | Default | v | 12.580 | |
| PCH_DSWVRMEN | Default | v | 3.300 | |
| PCH_INTVRMEN_L | Default | v | 3.300 | |
| PCH_SRTCRST_L | Default | v | 3.300 | |
| PCIE_AP_D2R_PI_N | Default | d | 0.381 | |
| PCIE_AP_D2R_PI_P | Default | d | 0.380 | |
| PCIE_AP_R2D_N | Default | d | OL | |
| PCIE_AP_R2D_P | Default | d | OL | |
| PCIE_CLK100M_AP_CONN_N | Default | d | 0.400 | |
| PCIE_CLK100M_AP_CONN_P | Default | d | 0.400 | |
| PCIE_WAKE_L | Default | d | 0.580 | |
| PLT_RESET_L | Default | d | 0.42 | |
| PLT_RST_BUF_L | Default | d | 0.00 | |
| PM_DSW_PWRGD | Default | v | 3.300 | |
| PM_PWRBTN_L | Default | v | 3.400 | |
| PM_S0_PGOOD | Default | d | 0.60 | |
| PM_SLP_S4_L | Default | d | 3.300 | |
| PP0V75_S0_DDRVTT | Default | d | 0.45 | |
| PP15V_T29 | Default | d | 0.530 | |
| PP18V5_DCIN_FUSE | Default | d | 2.865 | |
| PP18V5_DCIN_FUSE | Default | v | 16.700 | |
| PP1V05_S0 | Default | d | 0.013 | |
| PP1V05_S0 | Default | r | 12.000R | |
| PP1V05_S0_PCH | Default | d | 0.012 | |
| PP1V05_S0_PCH | Default | r | 12.500R | |
| PP1V05_S0_PCH_VCCADPLL | Default | d | 0.15 | |
| PP1V05_S0_PCH_VCCCLKDMI_R | Default | d | 0.012 | |
| PP1V05_S0_PCH_VCCCLKDMI_R | Default | r | 12.500R | |
| PP1V05_SUS | Default | d | 0.48 | |
| PP1V2_S5_SMC_VDDC | Default | v | 1.200 | |
| PP1V5_S0 | Default | d | 0.29 | |
| PP1V5_S3 | Default | d | 0.127 | |
| PP1V5_S3 | Default | r | 126.000 | |
| PP1V5_S3 | Default | v | 1.500 | |
| PP1V5_S3RS0 | Default | d | 0.100 | |
| PP1V5_S3RS0 | Default | r | 100.000R | |
| PP1V5_S3_DDR | Default | d | 0.127 | |
| PP1V5_S3_DDR | Default | r | 126.000 | |
| PP1V8_S0 | Default | d | 0.120 | |
| PP1V8_S0_CPU_VCCPLL_R | Default | d | 0.110 | |
| PP1V8_S0_CPU_VCCPLL_R | Default | r | 110.000R | |
| PP1V8_S0_PCH_VCCTX_LVDS_F | Default | d | 0.120 | |
| PP3V3_LCDVDD_SW | Default | d | 0.60 | |
| PP3V3_LCDVDD_SW_F | Default | d | 0.60 | |
| PP3V3_S0 | Default | d | 0.339 | |
| PP3V3_S0_CPUTHMSNS_R | Default | d | 0.39 | |
| PP3V3_S0_LCD_F | Default | d | 0.34 | |
| PP3V3_S0_PCH_VCC3_3_CLK_F | Default | d | 0.350 | |
| PP3V3_S0_PCH_VCC3_3_CLK_R | Default | d | 0.350 | |
| PP3V3_S3 | Default | v | 3.300 | |
| PP3V3_S3RS4_BT_F | Default | d | 0.395 | |
| PP3V3_S3RS4_BT_F | Default | v | 3.300 | |
| PP3V3_S4 | Default | v | 3.300 | |
| PP3V3_S5 | Default | d | 0.49 | |
| PP3V3_S5 | Default | v | 3.300 | |
| PP3V3_SUS | Default | d | 0.34 | |
| PP3V3_WLAN | Default | d | 2.710 | |
| PP3V42_G3H | Default | d | 0.35 | |
| PP3V42_G3H | Default | v | 3.480 | |
| PP5V1_CHGR_VDD | Default | d | 0.46 | |
| PP5V1_CHGR_VDD | Default | v | 5.060 | |
| PP5V1_CHGR_VDDP | Default | d | 0.46 | |
| PP5V1_CHGR_VDDP | Default | v | 5.030 | |
| PP5V_S0 | Default | d | 0.37 | |
| PP5V_S0_CPUIMVP_VCC | Default | d | 0.38 | |
| PP5V_S0_CPUVCCIOS0_VCC | Default | d | 0.38 | |
| PP5V_S0_HDD_FLT | Default | d | 0.37 | |
| PP5V_S0_VCCSAS0_VCC | Default | d | 0.37 | |
| PP5V_S3 | Default | d | 0.43 | |
| PP5V_S3 | Default | v | 5.000 | |
| PP5V_S3_IR_R | Default | d | 0.42 | |
| PP5V_S3_USB_A_F | Default | d | 0.518 | |
| PP5V_S5 | Default | d | 0.52 | |
| PP5V_S5 | Default | v | 5.00 | |
| PPBUS_FW_FWPWRSW_D | Default | v | 12.590 | |
| PPBUS_FW_FWPWRSW_F | Default | v | 12.590 | |
| PPBUS_G3H | Default | d | 0.450 | |
| PPBUS_S0_LCDBKLT_FUSED | Default | d | 0.450 | |
| PPBUS_S5_HS_COMPUTING_ISNS | Default | d | 0.050 | |
| PPBUS_S5_HS_COMPUTING_ISNS | Default | r | 52.000R | |
| PPBUS_S5_HS_COMPUTING_ISNS | Default | v | 12.600 | |
| PPBUS_S5_HS_OTHER_ISNS | Default | d | 0.45 | |
| PPBUS_S5_HS_OTHER_ISNS | Default | v | 12.60 | |
| PPBUS_SW_BKL | Default | d | 0.430 | |
| PPBUS_SW_LCDBKLT_PWR_SW | Default | d | 0.430 | |
| PPCHGR_DCIN | Default | d | 0.62 | |
| PPCHGR_DCIN | Default | v | 16.000 | |
| PPCPUVCCIO_S0_REG_R | Default | d | 0.013 | |
| PPCPUVCCIO_S0_REG_R | Default | v | 1.000 | |
| PPDCIN_G3H | Default | d | 2.865 | |
| PPDCIN_G3H | Default | v | 16.700 | |
| PPDCIN_G3H_CHGR | Default | d | 0.640 | |
| PPVBAT_G3H_CHGR_R | Default | d | 0.450 | |
| PPVBAT_G3H_CHGR_REG | Default | d | 0.450 | |
| PPVBAT_G3H_CHGR_REG | Default | v | 12.600 | |
| PPVBAT_G3H_CONN | Default | d | OL | |
| PPVCCSA_S0_CPU | Default | d | 0.053 | |
| PPVCCSA_S0_CPU | Default | r | 52.000R | |
| PPVCCSA_S0_CPU | Default | v | 0.800 | |
| PPVCCSA_S0_REG_R | Default | d | 0.053 | |
| PPVCCSA_S0_REG_R | Default | r | 52.000R | |
| PPVCCSA_S0_REG_R | Default | v | 0.807 | |
| PPVCORE_S0_AXG | Default | d | 0.012 | |
| PPVCORE_S0_AXG2_L | Default | d | 0.012 | |
| PPVCORE_S0_AXG_R | Default | d | 0.012 | |
| PPVCORE_S0_CPU | Default | d | 0.010 | |
| PPVCORE_S0_CPU | Default | r | 9.600R | |
| PPVCORE_S0_CPU | Default | v | 1.100 | |
| PPVCORE_S0_CPU_PH1 | Default | d | 0.010 | |
| PPVCORE_S0_CPU_PH1 | Default | v | 1.100 | |
| PPVCORE_S0_CPU_PH1_L | Default | d | 0.010 | |
| PPVCORE_S0_CPU_PH1_L | Default | v | 1.100 | |
| PPVCORE_S0_CPU_PH2 | Default | d | 0.010 | |
| PPVCORE_S0_CPU_PH2 | Default | r | 9.600R | |
| PPVCORE_S0_CPU_PH2 | Default | v | 1.100 | |
| PPVCORE_S0_CPU_PH2_L | Default | d | 0.010 | |
| PPVCORE_S0_CPU_PH2_L | Default | v | 1.100 | |
| PPVIN_G3H_P3V42G3H | Default | d | 0.570 | |
| PPVIN_G3H_P3V42G3H | Default | v | 15.700 | |
| PPVIN_SW_T29BST | Default | d | 0.450 | |
| PPVOUT_SW_LCDBKLT | Default | d | 0.59 | |
| PPVOUT_SW_LCDBKLT_FB | Default | d | 0.590 | |
| PPVRTC_G3H | Default | d | 0.444 | |
| PPVRTC_G3H | Default | v | 3.300 | |
| PPVTTDDR_S3 | Default | d | 0.49 | |
| PVCCSA_EN | Default | d | 0.53 | |
| PVCCSA_PGOOD | Default | d | 0.50 | |
| RTC_RESET_L | Default | v | 3.300 | |
| SATARDRVR_EN | Default | d | 0.43 | |
| SATARDRVR_I2C_ADDR0 | Default | d | 0.44 | |
| SATARDRVR_I2C_ADDR1 | Default | d | 0.46 | |
| SATARDRVR_I2C_EN_L | Default | d | 0.00 | |
| SATARDRVR_REXT | Default | d | 0.59 | |
| SATARDRVR_TEST | Default | d | 0.44 | |
| SATA_HDD_D2R_C_N | Default | d | OL | |
| SATA_HDD_D2R_C_P | Default | d | OL | |
| SATA_HDD_D2R_N | Default | d | 0.29 | |
| SATA_HDD_D2R_P | Default | d | 0.30 | |
| SATA_HDD_D2R_RDRIN_N | Default | d | 0.02 | |
| SATA_HDD_D2R_RDRIN_P | Default | d | 0.02 | |
| SATA_HDD_D2R_RDROUT_N | Default | d | 0.33 | |
| SATA_HDD_D2R_RDROUT_P | Default | d | 0.33 | |
| SATA_HDD_R2D_C_N | Default | d | 0.27 | |
| SATA_HDD_R2D_C_P | Default | d | 0.27 | |
| SATA_HDD_R2D_N | Default | d | OL | |
| SATA_HDD_R2D_P | Default | d | OL | |
| SATA_HDD_R2D_RDRIN_N | Default | d | 0.02 | |
| SATA_HDD_R2D_RDRIN_P | Default | d | 0.02 | |
| SATA_HDD_R2D_RDROUT_N | Default | d | 0.33 | |
| SATA_HDD_R2D_RDROUT_P | Default | d | 0.33 | |
| SMBUS_PCH_CLK | Default | d | 0.40 | |
| SMBUS_PCH_DATA | Default | d | 0.40 | |
| SMBUS_SMC_1_S0_SCL | Default | d | 0.56 | |
| SMBUS_SMC_1_S0_SDA | Default | d | 0.56 | |
| SMBUS_SMC_5_G3_SCL | Default | d | 0.53 | |
| SMBUS_SMC_5_G3_SCL | Default | v | 3.480 | |
| SMBUS_SMC_5_G3_SDA | Default | d | 0.53 | |
| SMBUS_SMC_5_G3_SDA | Default | v | 3.480 | |
| SMC_BATLOW_L | Default | v | 3.200 | |
| SMC_BC_ACOK | Default | d | 0.50 | |
| SMC_BC_ACOK | Default | v | 3.300 | |
| SMC_BC_ACOK_VCC | Default | d | 0.530 | |
| SMC_BIL_BUTTON_L | Default | d | 0.74 | |
| SMC_DELAYED_PWRGD | Default | d | 0.64 | |
| SMC_LID | Default | v | 3.400 | |
| SMC_LID_R | Default | d | 0.84 | |
| SMC_LRESET_L | Default | v | 3.300 | |
| SMC_ONOFF_L | Default | t | SMC_ONOFF_L not logic work ,SMC_ONOFF_L is connected to signals like G3_POWERON_L and SMC_LID˙˙˙%a | |
| SMC_ONOFF_L | Default | v | 3.400 | |
| SMC_PM_G2_EN | Default | v | 3.400 | |
| SMC_RESET_L | Default | d | 0.492 | |
| SMC_RESET_L | Default | v | 3.400 | |
| SMC_SSD_OOBD2R_R_L | Default | d | 0.54 | |
| SPIROM_USE_MLB | Default | d | 0.53 | |
| SPI_MLB_CLK | Default | d | 0.65 | |
| SPI_MLB_CS_L | Default | d | 0.63 | |
| SPI_MLB_MISO | Default | d | 0.51 | |
| SPI_MLB_MOSI | Default | d | 0.52 | |
| SPI_WP_L | Default | d | 0.64 | |
| SSD_OOB1V0REF | Default | d | 0.65 | |
| SSD_OOBD2R_L | Default | d | 1.31 | |
| SSD_OOBD2R_R_L | Default | d | 0.65 | |
| SSD_OOBR2D_L | Default | d | 0.84 | |
| SYSCLK_CLK25M_X2_R | Default | d | 0.450 | |
| SYS_DETECT_L | Default | d | 2.600 | |
| SYS_LED_ANODE_R | Default | d | OL | |
| SYS_PWROK_R | Default | d | 0.49 | |
| T29BST_BOOST | Default | d | 0.450 | |
| THMSNS_D1_N | Default | d | 0.76 | |
| THMSNS_D1_P | Default | d | 0.77 | |
| THMSNS_D2_N | Default | d | 0.75 | |
| THMSNS_D2_P | Default | d | 0.75 | |
| TP_DDRREG_PGOOD | Default | d | 0.57 | |
| UNCONNECTED_126 | Default | d | 0.62 | |
| UNCONNECTED_144 | Default | d | OL | |
| UNCONNECTED_75 | Default | d | - | |
| UNCONNECTED_76 | Default | d | - | |
| USB3_EXTA_RX_F_N | Default | d | 0.347 | |
| USB3_EXTA_RX_F_P | Default | d | 0.354 | |
| USB3_EXTA_TX_F_N | Default | d | 0.755 | |
| USB3_EXTA_TX_F_P | Default | d | 0.755 | |
| USB_BT_CONN_N | Default | d | 0.710 | |
| USB_BT_CONN_P | Default | d | 0.714 | |
| USB_BT_N | Default | d | 0.703 | |
| USB_BT_P | Default | d | 0.705 | |
| USB_BT_WAKEN | Default | d | 0.712 | |
| USB_BT_WAKEP | Default | d | 0.717 | |
| USB_EXTA_MUXED_F_N | Default | d | 0.572 | |
| USB_EXTA_MUXED_F_P | Default | d | 0.573 | |
| VCCSAS0_AGND | Default | d | - | |
| VCCSAS0_CS_N | Default | d | 0.053 | |
| VCCSAS0_CS_N | Default | r | 52.000R | |
| VCCSAS0_CS_P | Default | d | 0.053 | |
| VCCSAS0_CS_P | Default | r | 52.000R | |
| VCCSAS0_DRVH | Default | d | 0.57 | |
| VCCSAS0_DRVL | Default | d | 0.44 | |
| VCCSAS0_FSEL | Default | d | 0.00 | |
| VCCSAS0_LL | Default | d | 0.050 | |
| VCCSAS0_LL | Default | r | 52.000R | |
| VCCSAS0_LL | Default | v | 0.819 | |
| VCCSAS0_OCSET | Default | d | 0.50 | |
| VCCSAS0_RTN_DIV | Default | d | 0.51 | |
| VCCSAS0_SET0 | Default | d | 0.53 | |
| VCCSAS0_SET1 | Default | d | 0.53 | |
| VCCSAS0_SREF | Default | d | 0.53 | |
| VCCSAS0_VBST | Default | d | 0.53 | |
| VCCSAS0_VO | Default | d | 0.50 | |
| WIFI_EVENT_L_R | Default | d | 0.761 |
| Component | Type | Value |
|---|---|---|
| J9000 | v | 0 |
| R6929 | v | 2.0K |
| R9719 | v | 0 |