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This data released under the ODbL licence.
| Netname | Condition | Type | Value | Comment |
|---|---|---|---|---|
| CHGR_CSI_R_N | Default | d | 0.583 | |
| CHGR_CSI_R_N | Default | v | 14.200 | |
| CHGR_CSI_R_P | Default | d | 0.583 | |
| CHGR_CSI_R_P | Default | v | 14.200 | |
| CHGR_PHASE | Default | v | 8.670 | |
| CPUVR_PHASE1 | Default | v | 1.800 | |
| CPUVR_PHASE2 | Default | v | 1.800 | |
| DCIN_ISOL_GATE | Default | d | 0.771 | |
| DCIN_ISOL_GATE | Default | v | 6.700 | |
| DCIN_ISOL_GATE_R | Default | d | 2.816 | |
| DCIN_ISOL_GATE_R | Default | v | 6.700 | |
| I2C_ALS_1V8_SCL | Default | d | 0.601 | |
| JP600_PIN_32 | Default | d | 0.601 | |
| P1V05S0_LL | Default | v | 1.072 | |
| P3V3SSD_VMON | Default | d | 0.484 | |
| P3V3_S5_REG_L | Default | v | 3.300 | |
| P3V42G3H_BOOST | Default | v | 7.160 | |
| P3V42G3H_FB | Default | v | 1.300 | |
| P3V42G3H_SHDN_L | Default | v | 14.510 | |
| P3V42G3H_SW | Default | d | 0.314 | |
| P3V42G3H_SW | Default | v | 3.400 | |
| P5V_S4RS3_REG_L | Default | v | 5.000 | |
| PDDR_S3_REG_L | Default | v | 1.200 | |
| PP18V5_DCIN_ISOL_R | Default | v | 14.770 | |
| PP1V05_S0_REG_R | Default | v | 1.058 | |
| PP1V2_S3 | Default | v | 1.200 | |
| PP3V3_S0 | Default | d | 0.690 | |
| PP3V3_S0SW_SSD | Default | d | 0.530 | |
| PP3V3_S0SW_SSD_FLT | Default | d | 0.553 | |
| PP3V3_S5 | Default | v | 3.300 | |
| PP3V3_S5_REG_R | Default | v | 3.300 | |
| PP3V42_G3H | Default | d | 0.314 | |
| PP3V42_G3H | Default | v | 3.400 | |
| PP5V1_CHGR_VDD | Default | v | 5.000 | |
| PP5V1_CHGR_VDDP | Default | v | 5.000 | |
| PP5V_S0 | Default | v | 5.000 | |
| PP5V_S4RS3 | Default | d | 0.430 | |
| PP5V_S4RS3 | Default | v | 5.000 | |
| PPBUS_G3H | Default | d | 0.148 | |
| PPBUS_G3H | Default | v | 8.540 | |
| PPBUS_G3H_R | Default | d | 0.155 | |
| PPBUS_G3H_R | Default | v | 8.540 | |
| PPBUS_S5_HS_COMPUTING_ISNS | Default | v | 8.540 | |
| PPBUS_S5_HS_OTHER_ISNS | Default | v | 8.600 | |
| PPDCIN_G3H | Default | d | 0.709 | |
| PPDCIN_G3H | Default | v | 14.400 | |
| PPDCIN_G3H_CHGR | Default | d | 0.583 | |
| PPDCIN_G3H_CHGR | Default | v | 14.360 | |
| PPDCIN_G3H_INRUSH | Default | d | 0.583 | |
| PPDCIN_G3H_INRUSH | Default | v | 14.250 | |
| PPDCIN_G3H_ISOL | Default | v | 14.820 | |
| PPDDR_S3_REG_R | Default | v | 1.200 | |
| PPVBAT_G3H_CHGR_REG | Default | v | 8.600 | |
| PPVCC_S0_CPU | Default | v | 1.800 | |
| PPVCC_S0_CPU_PH1 | Default | v | 1.800 | |
| PPVCC_S0_CPU_PH2 | Default | v | 1.800 | |
| PPVIN_G3H_P3V42G3H | Default | d | 0.399 | |
| PPVIN_G3H_P3V42G3H | Default | v | 14.510 | |
| PPVMEMIO_S0_CPU | Default | v | 1.200 | |
| S0PGD_C | Default | v | 0.130 | |
| SMC_FAN_0_TACH | Default | d | 0.736 | |
| SMC_MANUAL_RST_L | Default | v | 2.700 | |
| SMC_OOB1_D2R_CONN_L | Default | d | OL | |
| SMC_OOB1_D2R_L | Default | d | 0.670 | |
| SMC_OOB1_R2D_CONN_L | Default | d | OL | |
| SMC_OOB1_R2D_L | Default | d | 0.645 | |
| SSD_CLKREQ_CONN_L | Default | d | 0.435 | |
| SSD_CLKREQ_L | Default | d | 0.460 | |
| SSD_PWR_EN | Default | d | 0.360 | |
| SSD_RESET_CONN_L | Default | d | 0.433 | |
| SSD_RESET_L | Default | d | 0.453 | |
| UNCONNECTED_123 | Default | d | OL | |
| UNCONNECTED_123 | Default | v | 14.270 | |
| UNCONNECTED_124 | Default | d | OL | |
| UNCONNECTED_124 | Default | v | 14.270 | |
| UNCONNECTED_125 | Default | d | OL | |
| UNCONNECTED_125 | Default | v | 14.270 | |
| UNCONNECTED_126 | Default | d | OL | |
| UNCONNECTED_126 | Default | v | 14.270 | |
| VMON_3V3_DIV | Default | v | 0.720 | |
| VMON_5V_DIV | Default | v | 0.670 | |
| VMON_Q2_BASE | Default | v | 0.635 | |
| VMON_Q3_BASE | Default | v | 0.656 |
| Component | Type | Value |
|---|