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This data released under the ODbL licence.
| Netname | Condition | Type | Value | Comment |
|---|---|---|---|---|
| CPUVR_PHASE1 | 1.3GHz 4GB | r | 63.47R | |
| CPUVR_PHASE2 | 1.3GHz 4GB | d | - | |
| CPUVR_PHASE2 | 1.3GHz 4GB | r | 63.33R | |
| PPVCC_S0_CPU_PH1 | 1.3GHz 4GB | r | 63.47R | |
| PPVCC_S0_CPU_PH2 | 1.3GHz 4GB | d | - | |
| PPVCC_S0_CPU_PH2 | 1.3GHz 4GB | r | 63.33R | |
| CPUVR_PHASE1 | 1.4GHz 4GB | d | - | |
| CPUVR_PHASE1 | 1.4GHz 4GB | r | 82.25R | |
| CPUVR_PHASE1 | 1.4GHz 4GB | t | 50R | |
| CPUVR_PHASE2 | 1.4GHz 4GB | d | - | |
| CPUVR_PHASE2 | 1.4GHz 4GB | r | 82.52R | |
| CPUVR_PHASE2 | 1.4GHz 4GB | t | ||
| PPVCC_S0_CPU_PH1 | 1.4GHz 4GB | d | - | |
| PPVCC_S0_CPU_PH1 | 1.4GHz 4GB | r | 82.25R | |
| PPVCC_S0_CPU_PH2 | 1.4GHz 4GB | d | - | |
| PPVCC_S0_CPU_PH2 | 1.4GHz 4GB | r | 82.53R | |
| CPUVR_PHASE1 | 1.7GHz 8GB | r | 49.00R | |
| CPUVR_PHASE2 | 1.7GHz 8GB | r | 49.93R | |
| PPVCC_S0_CPU_PH1 | 1.7GHz 8GB | r | 49.00R | |
| PPVCC_S0_CPU_PH2 | 1.7GHz 8GB | r | 49.92R | |
| BKL_EN | Backlight driver off | d | OL | |
| BKL_FAULT | Backlight driver off | d | OL | |
| BKL_FLTR | Backlight driver off | d | OL | |
| BKL_FSET | Backlight driver off | d | OL | |
| BKL_ISEN1 | Backlight driver off | d | OL | |
| BKL_ISEN2 | Backlight driver off | d | OL | |
| BKL_ISEN3 | Backlight driver off | d | OL | |
| BKL_ISEN4 | Backlight driver off | d | OL | |
| BKL_ISEN5 | Backlight driver off | d | OL | |
| BKL_ISEN6 | Backlight driver off | d | OL | |
| BKL_ISET | Backlight driver off | d | OL | |
| BKL_PWM | Backlight driver off | d | 1.24 | |
| BKL_SCL | Backlight driver off | d | 0.90 | |
| BKL_SDA | Backlight driver off | d | 0.90 | |
| BKL_VSYNC_R | Backlight driver off | d | OL | |
| GND_BKL_SGND | Backlight driver off | d | 0.00 | |
| LCDBKLT_BOOST | Backlight driver off | d | 3.18 | |
| PP3V3_S0 | Backlight driver off | d | 0.60 | |
| PP5V_S0 | Backlight driver off | d | 1.51 | |
| PPVOUT_SW_LCDBKLT_FB | Backlight driver off | d | OL | |
| ALL_SYS_PWRGD | Default | v | 3.30 | |
| AP_CLKREQ_Q_L | Default | d | 0.46 | |
| AP_CLKREQ_Q_L | Default | v | 3.250 | |
| AP_CLKREQ_R_L | Default | d | 0.42 | |
| AP_PCIE_WAKE_L | Default | d | 0.5219 | |
| AP_PCIE_WAKE_L | Default | v | 3.316 | |
| AP_RESET_CONN_L | Default | d | 0.4635 | |
| AP_RESET_CONN_L | Default | v | 3.324 | |
| AP_RESET_CONN_R_L | Default | d | 0.45 | |
| AP_RESET_L | Default | d | 0.42 | |
| AUD_PWR_EN | Default | d | 0.6326 | |
| BKLT_PLT_RST_L | Default | d | 0.54 | |
| BKL_FAULT | Default | d | 0.56 | |
| BKL_FLTR | Default | d | 0.560 | |
| BKL_FSET | Default | d | 0.500 | |
| BKL_ISEN1 | Default | d | 0.600 | |
| BKL_ISEN2 | Default | d | 0.640 | |
| BKL_ISEN3 | Default | d | 0.640 | |
| BKL_ISEN4 | Default | d | 0.640 | |
| BKL_ISEN5 | Default | d | 0.640 | |
| BKL_ISEN6 | Default | d | 0.640 | |
| BKL_ISET | Default | d | 0.500 | |
| BKL_PWM | Default | d | 0.500 | |
| BKL_SCL | Default | d | 0.510 | |
| BKL_SDA | Default | d | 0.500 | |
| BKL_VSYNC_R | Default | d | 0.560 | |
| BT_WAKE | Default | d | 0.787 | |
| CAM_SENSOR_WAKE_L_CONN | Default | d | 0.0004 | |
| CHGR_ACIN | Default | d | 0.5262 | |
| CHGR_ACIN | Default | v | 4.10 | |
| CHGR_AGATE | Default | d | 0.6436 | |
| CHGR_AGATE | Default | v | 0.00 | |
| CHGR_AGATE_DIV | Default | d | OL | |
| CHGR_AMON | Default | d | 0.7209 | |
| CHGR_AMON | Default | v | 0.20 | |
| CHGR_BGATE | Default | d | 0.6634 | |
| CHGR_BGATE | Default | v | 1.00 | |
| CHGR_BMON | Default | d | 0.7273 | |
| CHGR_BMON | Default | v | 0.05 | |
| CHGR_BOOT | Default | d | 0.5737 | |
| CHGR_BOOT | Default | v | 13.00 | |
| CHGR_CELL | Default | d | 0.0834 | |
| CHGR_CELL | Default | v | 0.00 | |
| CHGR_CSI_N | Default | d | 0.636 | |
| CHGR_CSI_N | Default | r | 21.500R | |
| CHGR_CSI_N | Default | v | 15.77 | |
| CHGR_CSI_P | Default | d | 0.624 | |
| CHGR_CSI_P | Default | r | 21.500R | |
| CHGR_CSI_P | Default | v | 15.77 | |
| CHGR_CSI_R_N | Default | d | 0.626 | |
| CHGR_CSI_R_P | Default | d | 0.626 | |
| CHGR_CSO_N | Default | d | 0.165 | |
| CHGR_CSO_N | Default | r | 4.000R | |
| CHGR_CSO_N | Default | v | 8.60 | |
| CHGR_CSO_P | Default | d | 0.165 | |
| CHGR_CSO_P | Default | r | 4.000R | |
| CHGR_CSO_P | Default | v | 8.60 | |
| CHGR_CSO_R_N | Default | d | 0.165 | |
| CHGR_CSO_R_P | Default | d | 0.165 | |
| CHGR_DCIN | Default | d | 0.6208 | |
| CHGR_DCIN | Default | v | 15.30 | |
| CHGR_ICOMP | Default | d | 0.7279 | |
| CHGR_ICOMP | Default | v | 1.70 | |
| CHGR_LGATE | Default | d | 0.4556 | |
| CHGR_LGATE | Default | v | 2.00 | |
| CHGR_PHASE | Default | d | 0.165 | |
| CHGR_PHASE | Default | v | 8.500 | |
| CHGR_RST_L | Default | d | 0.4992 | |
| CHGR_RST_L | Default | v | 3.30 | |
| CHGR_SGATE | Default | d | 0.6409 | |
| CHGR_SGATE | Default | v | 0.18 | |
| CHGR_UGATE | Default | d | 0.5937 | |
| CHGR_UGATE | Default | v | 11.00 | |
| CHGR_VCOMP | Default | d | 0.7260 | |
| CHGR_VCOMP | Default | v | 1.40 | |
| CHGR_VFRQ | Default | d | 0.4727 | |
| CHGR_VFRQ | Default | v | 0.00 | |
| CHGR_VNEG | Default | d | 0.5252 | |
| CHGR_VNEG | Default | v | 1.40 | |
| CPUBMONSNS_ALERT_L | Default | d | 0.764 | |
| CPUTHMSNS_ADDR_SEL | Default | d | 0.000 | |
| CPUTHMSNS_ALERT_L | Default | d | 0.595 | |
| CPUTHMSNS_D2_N | Default | d | 0.755 | |
| CPUTHMSNS_D2_P | Default | d | 0.755 | |
| CPUTHMSNS_DUR_SEL | Default | d | 0.774 | |
| CPUTHMSNS_TH_SEL | Default | d | 0.774 | |
| CPUVR_BOOT2 | Default | v | 6.30 | |
| CPUVR_COMP | Default | d | 0.594 | |
| CPUVR_COMP_RC | Default | d | OL | |
| CPUVR_DRSEL | Default | d | 0.000 | |
| CPUVR_FB | Default | d | 0.554 | |
| CPUVR_FB2 | Default | d | 0.578 | |
| CPUVR_FB_RC | Default | d | OL | |
| CPUVR_FCCM | Default | v | 5.00 | |
| CPUVR_ISEN1 | Default | d | 0.606 | |
| CPUVR_ISEN2 | Default | d | 0.600 | |
| CPUVR_ISNS1_N | Default | d | 0.042 | |
| CPUVR_ISNS1_N | Default | r | 147.000 | |
| CPUVR_ISNS1_N | Default | v | 1.800 | |
| CPUVR_ISNS1_P | Default | d | 0.042 | |
| CPUVR_ISNS1_P | Default | r | 147.000 | |
| CPUVR_ISNS1_P | Default | v | 1.800 | |
| CPUVR_ISNS2_N | Default | d | 0.042 | |
| CPUVR_ISNS2_N | Default | r | 147.000 | |
| CPUVR_ISNS2_N | Default | v | 1.800 | |
| CPUVR_ISNS2_P | Default | d | 0.042 | |
| CPUVR_ISNS2_P | Default | r | 147.000 | |
| CPUVR_ISNS2_P | Default | v | 1.800 | |
| CPUVR_ISUMN | Default | d | 0.041 | |
| CPUVR_ISUMN_R | Default | d | 0.297 | |
| CPUVR_ISUMN_RC | Default | d | 0.891 | |
| CPUVR_ISUMP | Default | d | 0.487 | |
| CPUVR_ISUM_IOUT | Default | d | 0.641 | |
| CPUVR_ISUM_R_N | Default | d | 0.791 | |
| CPUVR_ISUM_R_P | Default | d | 0.791 | |
| CPUVR_LGATE2 | Default | v | 3.80 | |
| CPUVR_NTC | Default | d | 0.604 | |
| CPUVR_PHASE1 | Default | d | 0.042 | |
| CPUVR_PHASE1 | Default | r | 147.000R | |
| CPUVR_PHASE1 | Default | t | ||
| CPUVR_PHASE1 | Default | v | 1.800 | |
| CPUVR_PHASE2 | Default | d | 0.042 | |
| CPUVR_PHASE2 | Default | r | 147.000R | |
| CPUVR_PHASE2 | Default | t | ||
| CPUVR_PHASE2 | Default | v | 1.80 | |
| CPUVR_PROG2 | Default | d | 0.595 | |
| CPUVR_PROG3 | Default | d | 0.603 | |
| CPUVR_PWM1 | Default | d | 0.593 | |
| CPUVR_PWM2 | Default | v | 0.00 | |
| CPUVR_SLOPE | Default | d | 0.597 | |
| CPUVR_UGATE2 | Default | v | 2.70 | |
| CPU_PECI_R | Default | d | 0.336 | |
| CPU_PROCHOT_L | Default | d | 0.193 | |
| CPU_RTN | Default | d | 0.002 | |
| CPU_THRMTRIP_3V3 | Default | d | 0.751 | |
| CPU_VCCSENSE_N | Default | d | 0.002 | |
| CPU_VCCSENSE_P | Default | d | 0.041 | |
| CPU_VCCSENSE_P_R | Default | d | 0.041 | |
| CPU_VCCSENSE_P_RC | Default | d | 1.553 | |
| CPU_VIDSCLK | Default | d | 0.185 | |
| CPU_VIDSOUT | Default | d | 0.196 | |
| CPU_VR_EN | Default | d | 0.335 | |
| CPU_VR_READY | Default | d | 0.551 | |
| DCINVSENS_EN_L | Default | d | 0.477 | |
| DCIN_ISOL_GATE | Default | d | 0.785 | |
| DCIN_ISOL_GATE_R | Default | d | OL | |
| DCIN_S5_VSENSE | Default | d | OL | |
| DDRREG_1V8_VREF | Default | v | 1.80 | |
| DDRREG_DRVH | Default | d | 0.64 | |
| DDRREG_DRVH | Default | v | 1.40 | |
| DDRREG_DRVL | Default | d | 0.46 | |
| DDRREG_DRVL | Default | v | 1.40 | |
| DDRREG_EN | Default | v | 3.30 | |
| DDRREG_FB | Default | v | 1.20 | |
| DDRREG_LL | Default | d | 0.15 | |
| DDRREG_LL | Default | v | 1.20 | |
| DDRREG_MODE | Default | d | 0.533 | |
| DDRREG_MODE | Default | v | 0.00 | |
| DDRREG_PGOOD | Default | d | 0.502 | |
| DDRREG_PGOOD | Default | v | 3.30 | |
| DDRREG_TRIP | Default | d | 0.754 | |
| DDRREG_TRIP | Default | v | 0.52 | |
| DDRREG_VBST | Default | d | 0.626 | |
| DDRREG_VBST | Default | v | 6.20 | |
| DDRREG_VBST_RC | Default | d | 0.625 | |
| DDRREG_VDDQSNS | Default | d | 0.151 | |
| DDRREG_VDDQSNS | Default | v | 1.20 | |
| DDRREG_VTTSNS | Default | d | 0.182 | |
| DDRREG_VTTSNS | Default | v | 0.60 | |
| DP_INT_AUX_CH_C_N | Default | d | OL | |
| DP_INT_AUX_CH_C_P | Default | d | OL | |
| DP_INT_HPD_CONN | Default | d | 0.7880 | |
| DP_INT_ML_N<0> | Default | d | OL | |
| DP_INT_ML_P<0> | Default | d | OL | |
| EDP_BKLT_EN | Default | d | 0.697 | |
| EDP_BKLT_PWM | Default | d | 0.560 | |
| FAN_RT_PWM | Default | d | 0.79 | |
| FAN_RT_TACH | Default | d | 0.61 | |
| FINSTACKSNS_ALERT_L | Default | d | 0.5869 | |
| GND | Default | d | 0.0004 | |
| GND_P5VP3V3_SGND | Default | d | 0.00 | |
| GND_P5VP3V3_SGND | Default | v | 0.00 | |
| GND_SMC_AVSS | Default | d | 0.0005 | |
| HDA_BIT_CLK | Default | d | 0.4443 | |
| HDA_RST_L | Default | d | 0.4469 | |
| HDA_SDIN0 | Default | d | 0.4086 | |
| HDA_SDOUT | Default | d | 0.4454 | |
| HDA_SYNC | Default | d | 0.4453 | |
| I2C_CAM_SCK | Default | d | 0.7468 | |
| I2C_CAM_SDA | Default | d | 0.7467 | |
| I2C_TCON_SCL_R | Default | d | 0.7347 | |
| I2C_TCON_SDA_R | Default | d | 0.7306 | |
| INLET_THMSNS_D1_N | Default | d | 0.75 | |
| INLET_THMSNS_D1_P | Default | d | 0.75 | |
| ISNS_1V05_S0_N | Default | d | OL | |
| ISNS_1V05_S0_P | Default | d | OL | |
| ISNS_1V2_S3_N | Default | d | 0.140 | |
| ISNS_1V2_S3_P | Default | d | 0.140 | |
| ISNS_AIRPORT_N | Default | d | 0.508 | |
| ISNS_AIRPORT_P | Default | d | 0.508 | |
| ISNS_CAMERA_N | Default | d | OL | |
| ISNS_CAMERA_P | Default | d | OL | |
| ISNS_CPUDDR_N | Default | d | OL | |
| ISNS_CPUDDR_P | Default | d | OL | |
| ISNS_HS_COMPUTING_IOUT | Default | d | 0.712 | |
| ISNS_HS_COMPUTING_N | Default | d | 0.165 | |
| ISNS_HS_COMPUTING_P | Default | d | 0.165 | |
| ISNS_HS_OTHER_N | Default | d | OL | |
| ISNS_HS_OTHER_P | Default | d | OL | |
| ISNS_LCDBKLT_IOUT | Default | d | OL | |
| ISNS_LCDBKLT_N | Default | d | OL | |
| ISNS_LCDBKLT_P | Default | d | OL | |
| ISNS_P3V3_S0_N | Default | d | OL | |
| ISNS_P3V3_S0_P | Default | d | OL | |
| ISNS_P5VSSD_IOUT | Default | d | 0.712 | |
| ISNS_PANEL_IOUT | Default | d | OL | |
| ISNS_SSD_N | Default | d | 0.563 | |
| ISNS_SSD_P | Default | d | 0.563 | |
| JTAG_TBT_TMS | Default | d | 0.541 | |
| KBDLED_ANODE | Default | v | - | |
| KBDLED_SW | Default | d | 0.430 | |
| LCDBKLT_BOOST | Default | d | 0.427 | |
| LCDBKLT_DISABLE | Default | d | 0.500 | |
| LCDBKLT_EN_DIV_L | Default | d | OL | |
| LCDBKLT_EN_L | Default | d | 0.763 | |
| LED_RETURN_1 | Default | d | 0.6231 | |
| LED_RETURN_2 | Default | d | 0.6231 | |
| LED_RETURN_3 | Default | d | 0.6230 | |
| LED_RETURN_4 | Default | d | 0.6207 | |
| LED_RETURN_5 | Default | d | 0.6213 | |
| LED_RETURN_6 | Default | d | 0.6220 | |
| LPCPLUS_RESET_L | Default | d | 0.5458 | |
| LPC_AD<0> | Default | d | 0.5413 | |
| LPC_AD<1> | Default | d | 0.5391 | |
| LPC_AD<2> | Default | d | 0.5386 | |
| LPC_AD<3> | Default | d | 0.5390 | |
| LPC_CLK24M_LPCPLUS | Default | d | 0.4613 | |
| LPC_CLK24M_SMC | Default | d | 0.478 | |
| LPC_FRAME_L | Default | d | 0.5353 | |
| LPC_PWRDWN_L | Default | d | 0.6104 | |
| LPC_SERIRQ | Default | d | 0.5354 | |
| MAX98300_R_N | Default | d | 0.611 | |
| MAX98300_R_P | Default | d | 0.612 | |
| MEMVTT_PWR_EN | Default | v | 3.20 | |
| MEM_EVENT_L | Default | d | 0.752 | |
| MIPI_CLK_CONN_N | Default | d | 0.4128 | |
| MIPI_CLK_CONN_P | Default | d | 3.0021 | |
| MIPI_DATA_CONN_N | Default | d | 0.4090 | |
| MIPI_DATA_CONN_P | Default | d | 0.4105 | |
| P1V05S0_AGND | Default | d | 0.0004 | |
| P1V05S0_AGND | Default | v | 0.00 | |
| P1V05S0_DRVH | Default | d | 3.4725 | |
| P1V05S0_DRVH | Default | v | 1.60 | |
| P1V05S0_DRVH_R | Default | v | 1.60 | |
| P1V05S0_DRVL | Default | d | 0.4613 | |
| P1V05S0_DRVL | Default | v | 4.30 | |
| P1V05S0_EN | Default | d | 0.4517 | |
| P1V05S0_EN | Default | v | 3.30 | |
| P1V05S0_FB | Default | d | 0.6677 | |
| P1V05S0_FB | Default | v | 1.00 | |
| P1V05S0_LL | Default | d | 0.131 | |
| P1V05S0_LL | Default | r | 151.000R | |
| P1V05S0_LL | Default | v | 1.00 | |
| P1V05S0_MODE | Default | d | 0.5154 | |
| P1V05S0_MODE | Default | v | 0.00 | |
| P1V05S0_PGOOD | Default | d | 0.4822 | |
| P1V05S0_PGOOD | Default | v | 3.30 | |
| P1V05S0_TRIP | Default | d | 0.7359 | |
| P1V05S0_TRIP | Default | v | 0.18 | |
| P1V05S0_VBST | Default | d | 0.5941 | |
| P1V05S0_VBST | Default | v | 6.00 | |
| P1V05S0_VDDQSNS | Default | d | 0.1281 | |
| P1V05S0_VDDQSNS | Default | v | 1.00 | |
| P1V05S0_VTT | Default | d | 0.5862 | |
| P1V05S0_VTT | Default | v | 0.50 | |
| P1V05S0_VTTREF | Default | d | 0.4798 | |
| P1V05S0_VTTREF | Default | v | 0.50 | |
| P1V05S3_EN | Default | d | 0.4836 | |
| P1V05S3_EN | Default | v | 0.00 | |
| P1V05_S0_VREF | Default | d | OL | |
| P1V05_S0_VREF | Default | v | 1.80 | |
| P1V2_CAM_SRVLXC_PHASE | Default | d | 0.276 | |
| P1V35_CAM_SRVLXD_PHASE | Default | d | 0.247 | |
| P1V5S0SW_AUDIO_EN | Default | v | 3.30 | |
| P1V8S3_EN | Default | v | 3.30 | |
| P1V8S3_FB | Default | v | 0.80 | |
| P1V8S3_PGOOD | Default | v | 3.30 | |
| P1V8S3_SW | Default | v | 1.80 | |
| P3V3S5_EN_R | Default | d | 0.53 | |
| P3V3S5_EN_R | Default | v | 3.40 | |
| P3V3WLAN_VMON | Default | d | 0.45 | |
| P3V3_S5_COMP2 | Default | d | 0.74 | |
| P3V3_S5_COMP2 | Default | v | 1.96 | |
| P3V3_S5_COMP2_R | Default | d | OL | |
| P3V3_S5_CSN2 | Default | d | 0.35 | |
| P3V3_S5_CSN2 | Default | v | 3.30 | |
| P3V3_S5_CSP2 | Default | d | 1.32 | |
| P3V3_S5_CSP2 | Default | v | 3.30 | |
| P3V3_S5_CSP2_R | Default | d | 0.360 | |
| P3V3_S5_DRVH | Default | d | 0.89 | |
| P3V3_S5_DRVH | Default | v | 3.90 | |
| P3V3_S5_DRVL | Default | d | 0.53 | |
| P3V3_S5_DRVL | Default | v | 0.96 | |
| P3V3_S5_LL | Default | d | 0.35 | |
| P3V3_S5_LL | Default | v | 3.30 | |
| P3V3_S5_REG_L | Default | d | 0.361 | |
| P3V3_S5_REG_L | Default | r | 320.000R | |
| P3V3_S5_RF | Default | d | 0.59 | |
| P3V3_S5_RF | Default | v | 1.20 | |
| P3V3_S5_VBST | Default | d | 0.62 | |
| P3V3_S5_VBST | Default | v | 8.40 | |
| P3V3_S5_VBST_R | Default | d | 0.567 | |
| P3V3_S5_VFB2 | Default | d | 0.58 | |
| P3V3_S5_VFB2 | Default | v | 1.00 | |
| P3V3_S5_VFB2_R | Default | d | 0.370 | |
| P3V42G3H_BOOST | Default | d | 0.6133 | |
| P3V42G3H_BOOST | Default | v | 7.20 | |
| P3V42G3H_FB | Default | d | 0.7060 | |
| P3V42G3H_FB | Default | v | 1.20 | |
| P3V42G3H_SHDN_L | Default | d | 0.3725 | |
| P3V42G3H_SHDN_L | Default | v | 15.38 | |
| P3V42G3H_SW | Default | d | 0.32 | |
| P3V42G3H_SW | Default | v | 3.40 | |
| P5VP3V3_SKIPSEL | Default | d | 0.48 | |
| P5VP3V3_SKIPSEL | Default | v | 2.00 | |
| P5VP3V3_VREF2 | Default | d | 0.48 | |
| P5VP3V3_VREF2 | Default | v | 2.00 | |
| P5VP3V3_VREG3 | Default | d | 0.56 | |
| P5VP3V3_VREG3 | Default | v | 3.30 | |
| P5VS4RS3_EN | Default | d | 0.489 | |
| P5VS4RS3_EN_D | Default | d | OL | |
| P5VS4RS3_EN_R | Default | d | 0.47 | |
| P5VS4RS3_EN_R | Default | v | 3.30 | |
| P5VS4RS3_EN_RC | Default | d | 0.488 | |
| P5VS4RS3_PGOOD | Default | d | 0.50 | |
| P5VS4RS3_PGOOD | Default | v | 3.30 | |
| P5V_S4RS3_COMP1 | Default | d | 0.74 | |
| P5V_S4RS3_COMP1 | Default | v | 1.96 | |
| P5V_S4RS3_COMP1_R | Default | d | OL | |
| P5V_S4RS3_CSN1 | Default | d | 0.43 | |
| P5V_S4RS3_CSN1 | Default | v | 5.00 | |
| P5V_S4RS3_CSP1 | Default | d | 1.29 | |
| P5V_S4RS3_CSP1 | Default | v | 5.00 | |
| P5V_S4RS3_CSP1_R | Default | d | 0.433 | |
| P5V_S4RS3_DRVH | Default | d | 0.97 | |
| P5V_S4RS3_DRVH | Default | v | 5.20 | |
| P5V_S4RS3_DRVL | Default | d | 0.53 | |
| P5V_S4RS3_DRVL | Default | v | 0.30 | |
| P5V_S4RS3_FUNC | Default | d | 0.00 | |
| P5V_S4RS3_FUNC | Default | v | 0.00 | |
| P5V_S4RS3_LL | Default | d | 0.43 | |
| P5V_S4RS3_LL | Default | v | 5.00 | |
| P5V_S4RS3_REG_L | Default | d | 0.435 | |
| P5V_S4RS3_VBST | Default | d | 0.62 | |
| P5V_S4RS3_VBST | Default | v | 10.10 | |
| P5V_S4RS3_VBST_R | Default | d | 0.638 | |
| P5V_S4RS3_VFB1 | Default | d | 0.58 | |
| P5V_S4RS3_VFB1 | Default | v | 1.00 | |
| P5V_S4RS3_VFB1_R | Default | d | 0.443 | |
| P5V_S4RS3_VFB1_XW | Default | d | 0.433 | |
| PBUSVSENS_EN_L | Default | d | 0.484 | |
| PBUSVSENS_EN_L_DIV | Default | d | OL | |
| PBUS_S0_VSENSE | Default | d | OL | |
| PCH_CLK32K_RTCX1 | Default | d | 0.4425 | |
| PCH_CLK32K_RTCX1 | Default | v | 0.43 | |
| PCH_HSIO_PWR_EN | Default | d | 0.527 | |
| PCH_SML1ALERT_L | Default | d | 0.637 | |
| PCH_STRP_TOPBLK_SWP_L | Default | d | 0.580 | |
| PCIE_AP_D2R_N | Default | d | 0.3738 | |
| PCIE_AP_D2R_N | Default | v | 0.002 | |
| PCIE_AP_D2R_P | Default | d | 0.3761 | |
| PCIE_AP_D2R_P | Default | v | 0.002 | |
| PCIE_AP_R2D_N | Default | d | OL | |
| PCIE_AP_R2D_N | Default | v | 0.002 | |
| PCIE_AP_R2D_P | Default | d | OL | |
| PCIE_AP_R2D_P | Default | v | 0.002 | |
| PCIE_CLK100M_AP_N | Default | d | 0.2827 | |
| PCIE_CLK100M_AP_N | Default | v | 0.000 | |
| PCIE_CLK100M_AP_P | Default | d | 0.2827 | |
| PCIE_CLK100M_AP_P | Default | v | 0.002 | |
| PCIE_CLK100M_SSD_N | Default | d | 0.00 | |
| PCIE_CLK100M_SSD_P | Default | d | 0.29 | |
| PCIE_SSD_D2R_P<0> | Default | d | 0.37 | |
| PCIE_SSD_R2D_N<0> | Default | d | OL | |
| PCIE_SSD_R2D_N<1> | Default | d | OL | |
| PCIE_SSD_R2D_N<2> | Default | d | OL | |
| PCIE_SSD_R2D_N<3> | Default | d | OL | |
| PCIE_SSD_R2D_P<0> | Default | d | OL | |
| PCIE_SSD_R2D_P<1> | Default | d | OL | |
| PCIE_SSD_R2D_P<2> | Default | d | OL | |
| PCIE_SSD_R2D_P<3> | Default | d | OL | |
| PDCINVSENS_EN_L_DIV | Default | d | OL | |
| PDDR_S3_REG_L | Default | d | 0.14 | |
| PDDR_S3_REG_L | Default | v | 1.20 | |
| PLT_RESET_L | Default | v | 3.30 | |
| PLT_RST_BUF_L | Default | v | 3.30 | |
| PM_CLKRUN_L | Default | d | 0.5663 | |
| PM_PCH_PWROK | Default | d | 0.66 | |
| PM_PWRBTN_L | Default | d | 0.629 | |
| PM_SLP_S3_BUF_L | Default | d | 0.46 | |
| PM_SLP_S5_L | Default | d | 0.473 | |
| PM_THRMTRIP_R_L | Default | d | OL | |
| PP0V6_S0_DDRVTT | Default | d | 0.182 | |
| PP0V6_S0_DDRVTT | Default | v | 0.60 | |
| PP15V_TBT | Default | d | 0.56 | |
| PP18V5_DCIN_ISOL_R | Default | d | OL | |
| PP1V05_S0 | Default | d | 0.131 | |
| PP1V05_S0 | Default | v | 1.00 | |
| PP1V05_S0_REG_R | Default | d | 0.131 | |
| PP1V05_S0_REG_R | Default | r | 151.000R | |
| PP1V05_SUS | Default | d | 0.295 | |
| PP1V2_CAM | Default | d | 0.276 | |
| PP1V2_CAM_PCIE_PVDD_FLT | Default | d | 0.342 | |
| PP1V2_CAM_PCIE_VDD_FLT | Default | d | 0.342 | |
| PP1V2_CAM_XTALPCIEVDD | Default | d | 0.3421 | |
| PP1V2_CAM_XTALPCIEVDD | Default | v | 1.10 | |
| PP1V2_S3 | Default | d | 0.140 | |
| PP1V2_S3 | Default | v | 1.20 | |
| PP1V2_S5_SMC_VDDC | Default | d | 0.517 | |
| PP1V35_CAM | Default | d | 0.247 | |
| PP1V5_S0 | Default | v | 1.50 | |
| PP1V5_S0SW_AUDIO | Default | d | 0.3675 | |
| PP1V5_S0SW_AUDIO | Default | v | 1.50 | |
| PP1V8_S3 | Default | d | 0.393 | |
| PP1V8_S3_REG_R | Default | d | 0.393 | |
| PP3V3RHV_S4_TBTAPWR | Default | d | 0.55 | |
| PP3V3RHV_S4_TBTAPWR_F | Default | d | 0.550 | |
| PP3V3_S0 | Default | d | 0.3523 | |
| PP3V3_S0 | Default | v | 3.30 | |
| PP3V3_S0SW_LCD | Default | d | 0.631 | |
| PP3V3_S0SW_LCD_R | Default | d | 0.631 | |
| PP3V3_S0SW_LCD_UF | Default | d | 0.5873 | |
| PP3V3_S0SW_SSD | Default | d | 0.563 | |
| PP3V3_S0SW_SSD_FET_R | Default | d | 0.563 | |
| PP3V3_S0SW_SSD_FLT | Default | d | 0.55 | |
| PP3V3_S0_CPUTHMSNS_R | Default | d | 0.406 | |
| PP3V3_S0_FET_R | Default | d | 0.352 | |
| PP3V3_S3 | Default | d | 0.487 | |
| PP3V3_S3RS0_CAMERA | Default | d | 0.359 | |
| PP3V3_S3RS0_CAMERA_R | Default | d | 0.359 | |
| PP3V3_S3_FET_R | Default | d | 0.487 | |
| PP3V3_S4 | Default | d | 0.3899 | |
| PP3V3_S4 | Default | v | 3.300 | |
| PP3V3_S4_FET_R | Default | d | 0.395 | |
| PP3V3_S4_IPD | Default | d | 0.38 | |
| PP3V3_S4_TBTAPWR | Default | d | 0.36 | |
| PP3V3_S5 | Default | d | 0.3541 | |
| PP3V3_S5 | Default | v | 3.30 | |
| PP3V3_S5RS3RS0_SYSCLKGEN | Default | d | 0.3539 | |
| PP3V3_S5RS3RS0_SYSCLKGEN | Default | v | 3.30 | |
| PP3V3_S5_AVREF_SMC | Default | d | 0.5952 | |
| PP3V3_S5_REG_R | Default | d | 0.361 | |
| PP3V3_S5_REG_R | Default | r | 320.000R | |
| PP3V3_S5_SMC_VDDA | Default | d | 0.320 | |
| PP3V3_SUS | Default | d | 0.350 | |
| PP3V3_SUS_FET_R | Default | d | 0.350 | |
| PP3V3_TBTLC | Default | d | 0.4031 | |
| PP3V3_TBTLC | Default | v | 3.30 | |
| PP3V3_WLAN | Default | d | 0.508 | |
| PP3V3_WLAN | Default | v | 3.310 | |
| PP3V3_WLAN_R | Default | d | 0.508 | |
| PP3V42_G3H | Default | d | 0.320 | |
| PP3V42_G3H | Default | v | 3.40 | |
| PP3V42_G3H_SMC_SPVSR | Default | d | 0.3080 | |
| PP5V1_CHGR_VDD | Default | d | 0.4508 | |
| PP5V1_CHGR_VDD | Default | v | 5.00 | |
| PP5V1_CHGR_VDDP | Default | d | 0.4521 | |
| PP5V1_CHGR_VDDP | Default | v | 5.00 | |
| PP5V_S0 | Default | d | 0.430 | |
| PP5V_S0 | Default | v | - | |
| PP5V_S0_ALT_AUD_LDO_EN | Default | d | OL | |
| PP5V_S0_CPUVR_VDD | Default | d | 0.430 | |
| PP5V_S0_FET_R | Default | d | 0.430 | |
| PP5V_S3RS0_ALSCAM_F | Default | d | 0.4039 | |
| PP5V_S3_RTUSB_A_F | Default | d | 0.493 | |
| PP5V_S3_RTUSB_A_ILIM | Default | d | 0.493 | |
| PP5V_S3_U6210 | Default | d | 0.433 | |
| PP5V_S4RS3 | Default | d | 0.435 | |
| PP5V_S4RS3 | Default | v | 5.00 | |
| PP5V_S4_IPD | Default | d | 0.4374 | |
| PP5V_S5 | Default | d | 0.45 | |
| PP5V_S5 | Default | v | 5.00 | |
| PPBUS_G3H | Default | d | 0.165 | |
| PPBUS_G3H | Default | v | 8.500 | |
| PPBUS_G3H_R | Default | d | 0.170 | |
| PPBUS_S5_HS_COMPUTING_ISNS | Default | d | 0.164 | |
| PPBUS_S5_HS_COMPUTING_ISNS | Default | v | 8.60 | |
| PPBUS_S5_HS_OTHER_ISNS | Default | d | 0.165 | |
| PPBUS_S5_HS_OTHER_ISNS | Default | v | 8.60 | |
| PPCHGR_DCIN_D_R | Default | d | 0.655 | |
| PPDCIN_G3H | Default | d | OL | |
| PPDCIN_G3H_CHGR | Default | d | 0.626 | |
| PPDCIN_G3H_INRUSH | Default | d | 0.626 | |
| PPDCIN_G3H_ISOL | Default | d | OL | |
| PPDDR_S3_REG_R | Default | d | 0.140 | |
| PPHV_S0SW_LCDBKLT | Default | d | 0.608 | |
| PPVBAT_G3H_CHGR_R | Default | d | 0.165 | |
| PPVBAT_G3H_CHGR_REG | Default | d | 0.165 | |
| PPVBAT_G3H_CHGR_REG | Default | v | 8.500 | |
| PPVBAT_G3H_CONN | Default | d | OL | |
| PPVBAT_G3H_CONN | Default | v | - | |
| PPVCC_S0_CPU | Default | d | 0.042 | |
| PPVCC_S0_CPU | Default | r | 147.000 | |
| PPVCC_S0_CPU | Default | v | 1.800 | |
| PPVCC_S0_CPU_PH1 | Default | d | 0.042 | |
| PPVCC_S0_CPU_PH1 | Default | r | 147.000 | |
| PPVCC_S0_CPU_PH1 | Default | v | 1.800 | |
| PPVCC_S0_CPU_PH2 | Default | d | 0.042 | |
| PPVCC_S0_CPU_PH2 | Default | r | 147.000 | |
| PPVCC_S0_CPU_PH2 | Default | v | 1.800 | |
| PPVIN_G3H_P3V42G3H | Default | d | 0.394 | |
| PPVIN_G3H_P3V42G3H | Default | v | 15.38 | |
| PPVIN_S0SW_LCDBKLT | Default | d | 0.427 | |
| PPVIN_S0SW_LCDBKLTFET | Default | d | 0.166 | |
| PPVIN_S0SW_LCDBKLT_FET | Default | d | 0.43 | |
| PPVIN_S0_CPUVR_VIN | Default | d | 0.174 | |
| PPVIN_S4SW_TBTBST_FET | Default | d | 0.537 | |
| PPVMEMIO_S0_CPU | Default | d | 0.140 | |
| PPVOUT_SW_LCDBKLT_FB | Default | d | 0.58 | |
| PPVRTC_G3H | Default | d | 0.4342 | |
| PPVRTC_G3H | Default | v | 3.40 | |
| PPVTT_S3_DDR_BUF | Default | d | 0.490 | |
| PPVTT_S3_DDR_BUF | Default | v | 0.60 | |
| S0PGD_BJT_GND_R | Default | v | 0.09 | |
| S0PGD_C | Default | v | 0.12 | |
| S4_PWR_EN | Default | d | 0.46 | |
| S5_PWRGD | Default | d | 0.57 | |
| S5_PWRGD | Default | v | 3.30 | |
| S5_PWR_EN | Default | d | 0.543 | |
| SMBUS_SMC_1_S0_SCL | Default | d | 0.5476 | |
| SMBUS_SMC_1_S0_SDA | Default | d | 0.5447 | |
| SMBUS_SMC_2_S3_SCL | Default | d | 0.7146 | |
| SMBUS_SMC_2_S3_SDA | Default | d | 0.7165 | |
| SMBUS_SMC_3_SCL | Default | d | 0.7064 | |
| SMBUS_SMC_3_SDA | Default | d | 0.7069 | |
| SMBUS_SMC_5_G3_SCL | Default | d | 0.500 | |
| SMBUS_SMC_5_G3_SCL | Default | v | 3.30 | |
| SMBUS_SMC_5_G3_SDA | Default | d | 0.496 | |
| SMBUS_SMC_5_G3_SDA | Default | v | 3.30 | |
| SMC_1V2S3_ISENSE | Default | d | 0.748 | |
| SMC_BC_ACOK | Default | d | 0.5263 | |
| SMC_BC_ACOK | Default | v | 3.30 | |
| SMC_BIL_BUTTON_L | Default | d | 0.750 | |
| SMC_BMON_DISCRETE_ISENSE | Default | d | 0.748 | |
| SMC_BMON_ISENSE | Default | d | 0.750 | |
| SMC_CAMERA_ISENSE | Default | d | 0.750 | |
| SMC_CLK32K | Default | d | 0.705 | |
| SMC_CPUDDR_ISENSE | Default | d | 0.749 | |
| SMC_CPUVR_ADJUST_ISENSE | Default | d | 0.729 | |
| SMC_CPU_DBGPWR_RD_L | Default | d | 0.29 | |
| SMC_CPU_ISENSE | Default | d | 0.748 | |
| SMC_CPU_VSENSE | Default | d | 0.744 | |
| SMC_DCIN_ISENSE | Default | d | 0.749 | |
| SMC_DCIN_VSENSE | Default | d | 0.745 | |
| SMC_EXTAL | Default | d | 0.777 | |
| SMC_FAN_0_TACH | Default | d | 0.71 | |
| SMC_HS_COMPUTING_ISENSE | Default | d | 0.748 | |
| SMC_LCDBKLT_ISENSE | Default | d | 0.750 | |
| SMC_LID | Default | d | 0.7349 | |
| SMC_LSOC_RST_L | Default | d | OL | |
| SMC_MANUAL_RST_L | Default | d | 0.6581 | |
| SMC_ONOFF_L | Default | d | 0.6517 | |
| SMC_OOB1_R2D_CONN_L | Default | d | 0.699 | |
| SMC_OOB1_R2D_L | Default | d | 0.684 | |
| SMC_OTHER_HI_ISENSE | Default | d | 0.749 | |
| SMC_P1V05S0_ISENSE | Default | d | 0.749 | |
| SMC_P1V05S0_VSENSE | Default | d | 0.743 | |
| SMC_P3V3S0_ISENSE | Default | d | 0.751 | |
| SMC_P3V3S5_ISENSE | Default | d | 0.753 | |
| SMC_PANEL_ISENSE | Default | d | 0.750 | |
| SMC_PBUS_VSENSE | Default | d | 0.744 | |
| SMC_PCH_SUSACK_L | Default | d | 0.614 | |
| SMC_PCH_SUSWARN_L | Default | d | 0.631 | |
| SMC_PECI_L | Default | d | 0.74 | |
| SMC_PECI_L_R | Default | d | 0.750 | |
| SMC_PME_S4_DARK_L | Default | d | 0.529 | |
| SMC_PME_S4_WAKE_L | Default | d | 0.496 | |
| SMC_PM_G2_EN | Default | d | 0.53 | |
| SMC_PM_G2_EN | Default | v | 3.40 | |
| SMC_PROCHOT | Default | d | 0.752 | |
| SMC_RESET_L | Default | d | 0.5000 | |
| SMC_ROMBOOT | Default | d | 1.5659 | |
| SMC_RX_L | Default | d | 0.7385 | |
| SMC_S4_WAKESRC_EN | Default | d | 0.751 | |
| SMC_S5_PWRGD_VIN | Default | d | 0.752 | |
| SMC_SENSOR_ALERT_L | Default | d | 0.519 | |
| SMC_SSD_ISENSE | Default | d | 0.748 | |
| SMC_TCK | Default | d | 0.7356 | |
| SMC_TDI | Default | d | 0.7374 | |
| SMC_TDO | Default | d | 0.7389 | |
| SMC_THRMTRIP | Default | d | 0.749 | |
| SMC_TMS | Default | d | 0.7371 | |
| SMC_TOPBLK_SWP_L | Default | d | 0.710 | |
| SMC_TX_L | Default | d | 0.750 | |
| SMC_VCCIO_CPU_DIV2 | Default | d | 0.744 | |
| SMC_WAKE_L | Default | d | 0.750 | |
| SMC_WIFI_PWR_EN | Default | d | 0.42 | |
| SMC_WLAN_ISENSE | Default | d | 0.751 | |
| SMC_XTAL | Default | d | 0.767 | |
| SMC_XTAL_R | Default | d | OL | |
| SMS_INT_L | Default | d | 0.750 | |
| SPIROM_USE_MLB | Default | d | 0.4771 | |
| SPI_ALT_CLK | Default | d | 0.5581 | |
| SPI_ALT_CS_L | Default | d | 0.5589 | |
| SPI_ALT_MISO | Default | d | 0.5043 | |
| SPI_ALT_MOSI | Default | d | 0.5294 | |
| SPI_MISO_R | Default | d | 0.499 | |
| SPI_MLB_CLK | Default | d | 0.5493 | |
| SPI_MLB_CS_L | Default | d | 0.5523 | |
| SPI_MLB_MISO | Default | d | 0.4898 | |
| SPI_MLB_MOSI | Default | d | 0.4977 | |
| SPI_SMC_CS_L | Default | d | 0.608 | |
| SPI_WP_L | Default | d | 0.6319 | |
| SPKRAMP_INR_N | Default | d | OL | |
| SPKRAMP_INR_P | Default | d | OL | |
| SPKRAMP_ROUT_N | Default | d | 0.517 | |
| SPKRAMP_ROUT_P | Default | d | 0.517 | |
| SPKRAMP_SHDN_L | Default | d | 0.6040 | |
| SSD_CLKREQ_CONN_L | Default | d | 0.47 | |
| SSD_RESET_CONN_L | Default | d | 0.47 | |
| SYSCLK_CLK25M_CAMERA | Default | d | 0.4386 | |
| SYSCLK_CLK25M_CAMERA | Default | v | 0.57 | |
| SYSCLK_CLK25M_TBT | Default | d | 0.4235 | |
| SYSCLK_CLK25M_TBT | Default | v | 1.70 | |
| SYSCLK_CLK25M_X1 | Default | d | 0.4340 | |
| SYSCLK_CLK25M_X1 | Default | v | 1.40 | |
| SYSCLK_CLK25M_X2 | Default | d | 0.441 | |
| SYSCLK_CLK25M_X2_R | Default | d | 0.4359 | |
| SYSCLK_CLK25M_X2_R | Default | v | 0.95 | |
| SYS_DETECT_L | Default | d | 1.722 | |
| SYS_ONEWIRE | Default | d | 0.751 | |
| TBTAPWRSW_ISET_S0 | Default | d | 0.48 | |
| TBTAPWRSW_ISET_S3 | Default | d | 0.48 | |
| TBTAPWRSW_ISET_V3P3 | Default | d | 0.00 | |
| TBTBST_BOOST | Default | d | 0.537 | |
| TBT_A_HV_EN | Default | d | 0.47 | |
| TPAD_SPI_CLK | Default | d | 0.538 | |
| TPAD_SPI_CLK_R | Default | d | 0.5413 | |
| TPAD_SPI_CS_L | Default | d | 0.562 | |
| TPAD_SPI_CS_R_L | Default | d | 0.74 | |
| TPAD_SPI_IF_EN_CONN | Default | d | 0.69 | |
| TPAD_SPI_INT_L | Default | d | 0.634 | |
| TPAD_SPI_INT_S4_WAKE_L_CONN | Default | d | 0.4934 | |
| TPAD_SPI_MISO | Default | d | 0.525 | |
| TPAD_SPI_MISO_R | Default | d | 0.5307 | |
| TPAD_SPI_MOSI | Default | d | 0.547 | |
| TPAD_SPI_MOSI_R | Default | d | 0.5514 | |
| TPAD_USB_IF_EN_CONN | Default | d | 0.6759 | |
| TPAD_WAKE_L | Default | d | 0.0004 | |
| TP_SMC_5VSW_PWR_EN | Default | d | 0.751 | |
| TP_SMC_MD1 | Default | d | OL | |
| TP_SMC_TRST_L | Default | d | OL | |
| UNCONNECTED_172 | Default | v | 0.00 | |
| UNCONNECTED_251 | Default | v | 0.11 | |
| UNCONNECTED_252 | Default | v | 0.09 | |
| USB3_EXTB_D2R_RC_N | Default | d | 0.3608 | |
| USB3_EXTB_D2R_RC_P | Default | d | 0.3630 | |
| USB3_EXTB_R2D_N | Default | d | OL | |
| USB3_EXTB_R2D_P | Default | d | OL | |
| USB_BT_CONN_N | Default | d | 0.7779 | |
| USB_BT_CONN_N | Default | v | 0.027 | |
| USB_BT_CONN_P | Default | d | 0.7773 | |
| USB_BT_CONN_P | Default | v | 3.320 | |
| USB_EXTB_N | Default | d | 0.4309 | |
| USB_EXTB_P | Default | d | 0.4299 | |
| USB_PWR_EN | Default | d | 0.4658 | |
| USB_TPAD_N | Default | d | 0.7927 | |
| USB_TPAD_P | Default | d | 0.4290 | |
| VMON_Q2_BASE | Default | v | 0.65 | |
| VMON_Q3_BASE | Default | v | 0.66 | |
| VMON_Q4_BASE | Default | v | 0.74 | |
| VREFMRGN_MEMVREG_BUF | Default | d | OL | |
| WIFI_EVENT_L | Default | d | 0.7347 | |
| WIFI_EVENT_L | Default | v | 3.310 | |
| XDP_CPUPCH_TRST_L | Default | v | 0.00 | |
| XDP_CPU_TDI | Default | d | 0.331 | |
| XDP_CPU_TDO | Default | d | 0.181 | |
| XDP_CPU_TDO | Default | v | 1.00 | |
| XDP_JTAG_CPU_ISOL_L | Default | d | 0.564 | |
| XDP_JTAG_CPU_ISOL_L | Default | v | 4.90 | |
| XDP_LPCPLUS_GPIO | Default | d | 0.5134 | |
| XDP_PCH_TDI | Default | d | 0.300 | |
| XDP_PCH_TDO | Default | d | 0.300 | |
| XDP_PCH_TDO | Default | v | 1.00 | |
| XDP_PCH_TMS | Default | d | 0.297 | |
| XDP_SSD_PCIE1_SEL_L | Default | d | 0.505 | |
| XDP_SSD_PCIE2_SEL_L | Default | d | 0.507 | |
| XDP_TRST_L | Default | d | 0.655 | |
| XDP_TRST_L | Default | v | 0.00 | |
| XDP_USB_EXTB_OC_L | Default | d | 0.5147 | |
| PPVBAT_G3H_CONN | No Start | d | - | |
| SMBUS_SMC_5_G3_SCL | No Start | d | - | |
| SMBUS_SMC_5_G3_SDA | No Start | d | - | |
| SYS_DETECT_L | No Start | d | - |
| Component | Type | Value |
|---|---|---|
| R7095 | v | 348K |
| R7096 | v | 200K |