<<< Back to list of boards

This data released under the ODbL licence.

laptops/apple/820-3476

Diagnostic solutions

Backlight

• Diagnosing
  

  Check your voltage on backlight output.  
  If below 1V probably a bad fuse or MOSFET.
  If 8.4V check EN signal on [p:U7701:3], if present, check [n:BKL_PWM], if > 1V then replace [p:U7701]
  

Overview

• Summary
  

Power Rails

• S5
  

  [n:PPBUS_G3H]
  [n:PPBUS_S5_HS_COMPUTING_ISNS]
  [n:PPBUS_S5_HS_OTHER_ISNS]
  [n:PPDCIN_G3H_ISOL]
  [n:PP3V42_G3H]
  [n:PPVRTC_G3H] [p:C1910:1]
  [n:PP5V_S5]
  [n:PP3V3_S5]
  

• S4/S3
  

  [n:PP5V_S4RS3]
  [n:PP3V3_S4SW_SNS]
  [n:PP3V3_S4]
  [n:PP3V3_S3]
  [n:PP1V8_S3]
  [n:PP1V2_S3]
  

• S0
  

  [n:PP1V05_SUS] ( needs  [n:PP3V3_S5] -> [n:PP3V3_SUS_FET_R] )
  [n:PP5V_S0]
  [n:PP3V3_S0]
  [n:PP3V3_S0SW_SSD]
  [n:PP1V5_S0]
  [n:PP0V6_S0_DDRVTT]
  [n:PP1V05_S0]
  [n:PP1V05_S0SW_PCH_HSIO]
  [n:PPVCC_S0_CPU]
  [n:PPHV_S0SW_LCDBKLT]
  

• Missing PM_SLP_S4_L
  

  Missing [n:PM_SLP_S4_L] can sometimes be diagnosed by going through and ensuring all the following signals are present;
  [n:PPVRTC_G3H]
  [n:RTC_RESET_L]
  [n:PCH_SRTCRST_L]
  [n:PCH_INTVRMEN]
  [n:PCH_DSWVRMEN]
  [n:PCH_CLK32K_RTCX1]
  [n:PP3V3_S5]
  [n:PM_DSW_PWRGD]
  [n:PP3V3_SUS]
  [n:PM_BATLOW_L]
  [n:PM_RSMRST_L]
  [n:PM_PWRBTN_L]
  

Network Diode/Volt/Res values

Netname	Condition	Type	Value	Comment
4V5_NR	Default	d	0.680
4V5_REG_EN	Default	d	0.746
4V5_REG_IN	Default	d	0.431
ADAPTER_SENSE	Default	d	0.597
ADAPTER_SENSE	Default	v	3.3
ALL_SYS_PWRGD	Default	d	0.430
ALL_SYS_PWRGD	Default	v	3.4
AP_PCIE_WAKE_L	Default	d	0.522
AP_S0IX_WAKE_L	Default	d	0.479
AP_S0IX_WAKE_SEL	Default	d	0.495
AUD_CH_HS_GND	Default	d	0.001
AUD_CONN_HP_LEFT	Default	d	1.088
AUD_CONN_TIPDET_2	Default	d	0.923
AUD_CONN_TYPEDET	Default	d	0.778
AUD_HP_PORT_L	Default	d	1.108
AUD_HP_PORT_R	Default	d	1.520
AUD_HP_PORT_REFCH	Default	d	0.002
AUD_HP_PORT_REFUS	Default	d	0.002
AUD_HSBIAS	Default	d	0.558
AUD_HSBIAS_FILT	Default	d	0.767
AUD_HSBIAS_IN	Default	d	0.500
AUD_HSBIAS_REF	Default	d	0.492
AUD_LO2_L_N	Default	d	0.694
AUD_LO2_L_P	Default	d	0.695
AUD_LO2_R_N	Default	d	0.694
AUD_LO2_R_P	Default	d	0.696
AUD_LO3_L_N	Default	d	0.679
AUD_LO3_L_P	Default	d	0.680
AUD_LO3_R_N	Default	d	0.678
AUD_LO3_R_P	Default	d	0.680
AUD_SPKRAMP_LIN_N	Default	d	0.694
AUD_SPKRAMP_LIN_P	Default	d	0.696
AUD_SPKRAMP_LSUBIN_N	Default	d	0.679
AUD_SPKRAMP_LSUBIN_P	Default	d	0.680
AUD_SPKRAMP_RIN_N	Default	d	0.695
AUD_SPKRAMP_RIN_P	Default	d	0.696
AUD_SPKRAMP_RSUBIN_N	Default	d	0.679
AUD_SPKRAMP_RSUBIN_P	Default	d	0.680
AUD_TIPDET_1	Default	d	OL
AUD_TIPDET_2	Default	d	1.081
AUD_TYPEDET	Default	d	0.777
AUD_US_HS_GND	Default	d	0.001
BKLT_EN_R	Default	d	0.53
BKLT_ISET_KEYB	Default	d	0.67
BKLT_KEYB1	Default	d	0.64
BKLT_KEYB2	Default	d	0.64
BKLT_PWM_KEYB	Default	d	0.53
BKLT_SCL	Default	d	0.53
BKLT_SD	Default	d	0.57
BKLT_SDA	Default	d	0.53
BKLT_SENSE_OUT	Default	d	0.73
CAM_SENSOR_WAKE_L_CONN	Default	d	0.00
CHGR_ACIN	Default	d	0.552
CHGR_ACIN	Default	v	3.9
CHGR_AGATE	Default	d	0.63
CHGR_AGATE	Default	v	na
CHGR_AGATE_DIV	Default	d	OL
CHGR_AMON	Default	d	0.70
CHGR_BGATE	Default	d	0.642
CHGR_BMON	Default	d	0.71
CHGR_BOOT	Default	d	0.554
CHGR_CELL	Default	d	0.69
CHGR_CSI_N	Default	d	0.567
CHGR_CSI_P	Default	d	0.561
CHGR_CSO_N	Default	d	0.137
CHGR_CSO_P	Default	d	0.139
CHGR_DCIN	Default	d	0.61
CHGR_DCIN	Default	r	na
CHGR_DCIN	Default	t	High Resistance between K and M
CHGR_DCIN	Default	v	16.23
CHGR_DCIN_D_R	Default	d	0.602
CHGR_DCIN_D_R	Default	v	16.480
CHGR_ICOMP	Default	d	0.72
CHGR_ICOMP	Default	v	0
CHGR_LGATE	Default	d	.447
CHGR_PHASE	Default	d	0.135
CHGR_RST_L	Default	d	0.49
CHGR_SGATE	Default	d	0.617
CHGR_UGATE	Default	d	0.57
CHGR_VCOMP	Default	d	0.71
CHGR_VFRQ	Default	d	0.47
CHGR_VFRQ	Default	v	0
CHGR_VNEG	Default	d	0.52
CODEC_FLYN	Default	d	OL
CODEC_FLYP	Default	d	0.447
CODEC_HS_MIC_N	Default	d	0.769
CODEC_HS_MIC_P	Default	d	0.769
CODEC_MICIN2	Default	d	0.718
CODEC_VCOM	Default	d	0.713
CODEC_VREF_ADC	Default	d	0.776
CPUVR_BOOT1	Default	d	0.60
CPUVR_BOOT1	Default	v	6.201
CPUVR_BOOT2	Default	d	0.594
CPUVR_BOOT2	Default	v	6.198
CPUVR_COMP	Default	d	0.57
CPUVR_COMP	Default	v	1.397
CPUVR_DRSEL	Default	d	0.00
CPUVR_DRSEL	Default	v	0.000
CPUVR_FB	Default	d	0.54
CPUVR_FB	Default	v	1.737
CPUVR_FB2	Default	d	0.55
CPUVR_FB2	Default	v	1.744
CPUVR_FCCM	Default	d	0.57
CPUVR_FCCM	Default	v	5.062
CPUVR_IMON	Default	d	0.57
CPUVR_IMON	Default	v	0.057
CPUVR_ISEN1	Default	d	0.58
CPUVR_ISEN2	Default	d	0.58
CPUVR_ISUMN_R	Default	d	0.36
CPUVR_ISUMN_R	Default	v	1.746
CPUVR_ISUMP	Default	d	0.48
CPUVR_ISUMP	Default	v	1.746
CPUVR_LGATE1	Default	d	0.43
CPUVR_LGATE1	Default	v	4.252
CPUVR_LGATE2	Default	d	0.429
CPUVR_LGATE2	Default	v	4.269
CPUVR_NTC	Default	d	0.58
CPUVR_NTC	Default	v	2.169
CPUVR_PGOOD_R	Default	d	0.70
CPUVR_PHASE1	Default	d	0.057
CPUVR_PHASE1	Default	v	1.739
CPUVR_PHASE2	Default	d	0.057
CPUVR_PHASE2	Default	v	1.740
CPUVR_PROG1	Default	d	0.58
CPUVR_PROG1	Default	v	0.000
CPUVR_PROG2	Default	d	0.57
CPUVR_PROG2	Default	v	0.000
CPUVR_PROG3	Default	d	0.58
CPUVR_PROG3	Default	v	0.000
CPUVR_PWM1	Default	d	0.57
CPUVR_PWM1	Default	v	0.785
CPUVR_PWM2	Default	d	0.57
CPUVR_PWM2	Default	v	0.779
CPUVR_SLOPE	Default	d	0.58
CPUVR_SLOPE	Default	v	0.290
CPUVR_UGATE1	Default	d	0.620
CPUVR_UGATE1	Default	v	2.293
CPUVR_UGATE2	Default	d	0.619
CPUVR_UGATE2	Default	v	2.280
CPU_PROCHOT_L	Default	d	0.20
CPU_PROCHOT_L	Default	v	0.056
CPU_RTN	Default	d	0.00
CPU_RTN	Default	v	0.000
CPU_VCCST_PWRGD	Default	d	0.740
CPU_VIDALERT_L	Default	d	0.21
CPU_VIDALERT_L	Default	v	1.057
CPU_VIDSCLK	Default	d	0.19
CPU_VIDSCLK	Default	v	1.031
CPU_VIDSOUT	Default	d	0.20
CPU_VIDSOUT	Default	v	1.049
CPU_VR_EN	Default	d	0.32
CPU_VR_EN	Default	v	1.064
CPU_VR_READY	Default	d	0.53
CPU_VR_READY	Default	v	1.058
CS4208_HDA_SDOUT0_R	Default	d	0.467
CS4208_SPDIF_IN	Default	d	0.001
CS4208_SPDIF_OUT	Default	d	0.703
DCINVSENS_EN_L	Default	d	0.470
DDRREG_1V8_VREF	Default	d	0.63
DDRREG_DRVH	Default	d	0.57
DDRREG_DRVL	Default	d	0.43
DDRREG_EN	Default	d	0.53
DDRREG_FB	Default	d	0.68
DDRREG_LL	Default	d	0.11
DDRREG_MODE	Default	d	0.52
DDRREG_PGOOD	Default	d	0.49
DDRREG_TRIP	Default	d	0.74
DDRREG_VBST	Default	d	0.60
DDRREG_VDDQSNS	Default	d	0.12
DDRREG_VTTSNS	Default	d	0.16
DFET_OPENCH	Default	d	0.477
DFET_OPENUS	Default	d	0.477
DMIC_CLK3	Default	d	0.834
DMIC_CLK3_R	Default	d	0.748
DMIC_SDA2	Default	d	0.001
DMIC_SDA3	Default	d	0.784
DP_A_LSX_ML_N<1>	Default	d	0.769
DP_A_LSX_ML_P<1>	Default	d	0.763
DP_B_LSX_ML_N<1>	Default	d	0.762
DP_B_LSX_ML_P<1>	Default	d	0.759
DP_TBTPA_AUXCH_N	Default	d	0.815
DP_TBTPA_AUXCH_P	Default	d	0.815
DP_TBTPA_DDC_CLK	Default	d	0.581
DP_TBTPA_DDC_DATA	Default	d	0.583
DP_TBTPA_HPD	Default	d	0.796
DP_TBTPA_ML_N<1>	Default	d	0.776
DP_TBTPA_ML_P<1>	Default	d	0.776
DP_TBTPB_AUXCH_N	Default	d	0.763
DP_TBTPB_AUXCH_P	Default	d	0.764
DP_TBTPB_DDC_CLK	Default	d	0.574
DP_TBTPB_DDC_DATA	Default	d	0.574
DP_TBTPB_HPD	Default	d	0.779
DP_TBTPB_ML_N<1>	Default	d	0.775
DP_TBTPB_ML_P<1>	Default	d	0.773
EDP_BKLT_EN	Default	d	0.68
EDP_BKLT_PSR_EN	Default	d	0.53
EDP_PANEL_PWR	Default	d	0.68
EDP_PANEL_PWR_OR_PSR_EN	Default	d	0.67
FAN_RT_PWM	Default	d	0.90
FAN_RT_TACH	Default	d	OL
GND_AUDIO_CODEC	Default	d	0.000
GPIO0_SPKR_SHUTDOWN	Default	d	0.534
HDA_BIT_CLK	Default	d	0.501
HDA_RST_L	Default	d	0.500
HDA_SDIN0	Default	d	0.441
HDA_SYNC	Default	d	0.501
I2C_CAM_SCK	Default	d	0.76
I2C_CAM_SDA	Default	d	0.76
ISNS_1V05_S0_N	Default	d	0.130
ISNS_1V05_S0_P	Default	d	0.130
ISNS_LCDBKLT_N	Default	d	0.14
ISNS_LCDBKLT_P	Default	d	0.14
ISNS_S0_SSD_IOUT	Default	d	0.710
ISNS_SSD_N	Default	d	0.569
ISNS_SSD_P	Default	d	0.569
ISNS_TBT_N	Default	d	OL
ISNS_TBT_P	Default	d	OL
LCDBKLT_EN_L	Default	d	0.00
LCDBKLT_FB	Default	d	0.72
LCDBKLT_FET_DRV	Default	d	0.49
LCDBKLT_SW	Default	d	0.42
LCD_PSR_EN	Default	d	0.58
LPCPLUS_RESET_L	Default	d	0.57
LPC_AD<0>	Default	d	0.56
LPC_AD<1>	Default	d	0.56
LPC_AD<2>	Default	d	0.56
LPC_AD<3>	Default	d	0.56
LPC_CLK24M_LPCPLUS	Default	d	0.49
LPC_FRAME_L	Default	d	0.56
LPC_PWRDWN_L	Default	d	0.660
LPC_SERIRQ	Default	d	0.56
MEMVTT_PWR_EN	Default	d	0.53
MIPI_CLK_CONN_N	Default	d	0.40
MIPI_CLK_CONN_P	Default	d	0.40
MIPI_DATA_CONN_N	Default	d	0.40
MIPI_DATA_CONN_P	Default	d	0.40
P1V05S0_DRVH	Default	d	0.59
P1V05S0_DRVH_R	Default	d	0.59
P1V05S0_DRVL	Default	d	0.46
P1V05S0_EN	Default	d	0.43
P1V05S0_FB	Default	d	0.68
P1V05S0_LL	Default	d	0.13
P1V05S0_MODE	Default	d	0.52
P1V05S0_PGOOD	Default	d	0.48
P1V05S0_TRIP	Default	d	0.74
P1V05S0_VBST	Default	d	0.60
P1V05S0_VDDQSNS	Default	d	0.14
P1V05S0_VTT	Default	d	0.55
P1V05S0_VTTREF	Default	d	0.48
P1V05S3_EN	Default	d	0.49
P1V05_S0_VREF	Default	d	0.62
P1V2_CAM_SRVLXC_PHASE	Default	d	0.338
P1V35_CAM_SRVLXD_PHASE	Default	d	0.281
P1V5S0SW_AUDIO_EN	Default	d	OL
P1V5S0_EN	Default	d	0.73
P1V5S0_PGOOD	Default	d	0.55
P1V5_S0_FB	Default	d	0.77
P1V5_S0_SW	Default	d	0.343
P1V5_S0_SW	Default	v	1.050
P3V3S0SW_SSD_FET_RAMP	Default	d	0.635
P3V3S0_EN_D	Default	d	0.568
P3V3S5_COMP2	Default	d	0.73
P3V3S5_CSN2	Default	d	0.14
P3V3S5_CSN2	Default	v	3.300
P3V3S5_CSP2	Default	d	1.29
P3V3S5_CSP2	Default	v	3.300
P3V3S5_CSP2_R	Default	v	3.300
P3V3S5_DRVH	Default	d	0.67
P3V3S5_DRVH	Default	v	3.300
P3V3S5_DRVL	Default	d	0.52
P3V3S5_LL	Default	d	0.14
P3V3S5_LL	Default	v	3.300
P3V3S5_RF	Default	d	0.58
P3V3S5_TG	Default	v	3.300
P3V3S5_VBST	Default	d	0.55
P3V3S5_VBST	Default	v	8.250
P3V3S5_VFB2	Default	d	0.57
P3V3SUS_EN	Default	d	0.614
P3V3SUS_EN	Default	v	3.300
P5VP3V3_SKIPSEL	Default	d	0.48
P5VP3V3_VREF2	Default	d	0.48
P5VP3V3_VREG3	Default	d	0.56
P5VP3V3_VREG3	Default	v	3.200
P5VS4RS3_EN	Default	d	0.49
P5VS4RS3_PGOOD	Default	d	0.49
P5VS4_COMP1	Default	d	0.73
P5VS4_CSN1	Default	d	0.40
P5VS4_CSP1	Default	d	1.30
P5VS4_DRVH	Default	d	0.94
P5VS4_DRVL	Default	d	0.52
P5VS4_LL	Default	d	0.40
P5VS4_VBST	Default	d	0.62
P5VS4_VFB1	Default	d	0.58
P5VS4_VSW	Default	d	0.400
PBUSVSENS_EN_L	Default	d	0.49
PBUSVSENS_EN_L	Default	v	12.260
PBUSVSENS_EN_L_DIV	Default	d	OL
PBUSVSENS_EN_L_DIV	Default	v	12.380
PBUS_S0_VSENSE	Default	d	OL
PBUS_S0_VSENSE_IN	Default	d	0.14
PBUS_S0_VSENSE_IN	Default	v	12.490
PCH_CLK32K_RTCX1	Default	d	0.46
PCH_DSWVRMEN	Default	v	3.200
PCIE_AP_R2D_C_N	Default	d	0.390
PCIE_AP_R2D_C_P	Default	d	0.387
PCIE_AP_R2D_N	Default	d	OL
PCIE_AP_R2D_P	Default	d	OL
PCIE_WAKE_L	Default	d	0.512
PD_CS4208_GPIO1	Default	d	0.750
PICKB_L	Default	d	0.69
PLT_RESET_L	Default	d	0.551
PLT_RST_BUF_L	Default	d	0.560
PM_CLKRUN_L	Default	d	0.59
PM_PWRBTN_L	Default	d	0.565
PM_PWRBTN_L	Default	v	3.400
PM_RSMRST_L	Default	d	OL
PM_RSMRST_L	Default	v	3.200
PM_S0_PGOOD	Default	d	0.66
PM_SLP_S3_BUF_L	Default	d	0.43
PM_SLP_S3_L	Default	d	0.654
PM_SLP_S3_L	Default	v	3.300
PM_SLP_S3_R_L	Default	d	0.67
PM_SLP_S4_L	Default	d	0.501
PM_SLP_S4_L	Default	v	3.300
PM_SLP_S5_L	Default	d	0.452
PM_SLP_S5_L	Default	v	3.300
PM_SLP_SUS_L	Default	d	0.616
PM_SLP_SUS_L	Default	v	3.300
PP0V675_S0_DDRVTT	Default	d	0.120
PP0V675_S0_DDRVTT	Default	v	0.600
PP15V_TBT	Default	d	0.566
PP1V05_S0	Default	d	0.125
PP1V05_S0	Default	v	1.050
PP1V05_S0SW_PCH_HSIO	Default	d	0.211
PP1V05_S0SW_PCH_HSIO	Default	v	1.050
PP1V05_S0SW_PCH_VCCSATA3PLL	Default	d	0.208
PP1V05_S0SW_PCH_VCCUSB3PLL	Default	d	0.209
PP1V05_S0SW_PCH_VCCUSB3PLL	Default	v	1.050
PP1V05_S0_PCH_VCCACLKPLL	Default	d	0.126
PP1V05_S0_PCH_VCCAPLL_OPI	Default	d	0.126
PP1V05_S0_PCH_VCC_ICC	Default	d	0.126
PP1V05_S0_PCH_VCC_ICC_R	Default	d	0.126
PP1V05_S0_REG_R	Default	d	0.130
PP1V05_SUS	Default	d	0.425
PP1V05_SUS	Default	v	1.050
PP1V2_CAM	Default	d	0.338
PP1V2_CAM_PCIE_PVDD_FLT	Default	d	0.356
PP1V2_CAM_PCIE_VDD_FLT	Default	d	0.356
PP1V2_CAM_XTALPCIEVDD	Default	d	0.356
PP1V2_S5_SMC_VDDC	Default	v	1.200
PP1V35_CAM	Default	d	0.280
PP1V35_DDR_CLK	Default	d	0.280
PP1V35_S3	Default	d	0.124
PP1V35_S3	Default	v	1.350
PP1V35_S3_CPUDDR	Default	d	0.124
PP1V35_S3_CPUDDR	Default	v	1.350
PP1V5_S0	Default	d	0.343
PP1V5_S0	Default	v	1.050
PP1V5_S0SW_AUDIO_HDA	Default	d	0.342
PP1V5_S0_AUDIO_DIG	Default	d	0.379
PP1V8_CAM	Default	d	0.504
PP3V3_S0	Default	d	0.359
PP3V3_S0	Default	v	3.300
PP3V3_S0SW_SSD	Default	d	0.569
PP3V3_S0SW_SSD	Default	v	3.300
PP3V3_S0SW_SSD_FET	Default	d	0.569
PP3V3_S0SW_SSD_FET	Default	v	3.300
PP3V3_S0SW_SSD_FLT	Default	d	0.569
PP3V3_S0SW_SSD_FLT	Default	v	3.300
PP3V3_S0_AUDIO_ANALOG	Default	d	0.343
PP3V3_S0_FET	Default	d	0.359
PP3V3_S0_FET	Default	v	3.000
PP3V3_S3	Default	d	0.500
PP3V3_S3	Default	v	3.300
PP3V3_S3RS0_CAMERA	Default	d	0.359
PP3V3_S4	Default	d	0.424
PP3V3_S4	Default	v	3.300
PP3V3_S4SW_SNS	Default	d	0.499
PP3V3_S4SW_SNS	Default	v	3.300
PP3V3_S4_TBT	Default	d	0.424
PP3V3_S4_TBT	Default	v	3.300
PP3V3_S4_TBTAPWR	Default	d	0.490
PP3V3_S4_TBTBPWR	Default	d	0.384
PP3V3_S5	Default	d	0.150
PP3V3_S5	Default	v	3.300
PP3V3_S5RS3RS0_SYSCLKGEN	Default	d	0.140
PP3V3_S5RS3RS0_SYSCLKGEN	Default	v	3.300
PP3V3_S5_AVREF_SMC	Default	d	0.59
PP3V3_S5_AVREF_SMC	Default	v	3.200
PP3V3_S5_SMC_VDDA	Default	d	0.305
PP3V3_SUS	Default	d	0.425
PP3V3_SUS	Default	v	3.300
PP3V3_TBTLC	Default	d	0.416
PP3V3_TBTLC	Default	v	3.300
PP3V3_TPAD_CONN	Default	d	0.43
PP3V42_G3H	Default	d	0.310
PP3V42_G3H	Default	v	3.400
PP3V42_G3H_SMC_SPVSR	Default	d	0.31
PP3V42_G3H_SMC_SPVSR	Default	v	3.400
PP4V5_AUDIO_ANALOG	Default	d	0.435
PP5V1_CHGR_VDD	Default	d	0.313
PP5V1_CHGR_VDDP	Default	d	0.31
PP5VR3V3_SW_LCD	Default	d	0.52
PP5VR3V3_SW_LCD_UF	Default	d	0.52
PP5V_S0	Default	d	0.437
PP5V_S0	Default	v	5.099
PP5V_S0_BKLT_A	Default	d	0.40
PP5V_S0_BKLT_D	Default	d	0.40
PP5V_S0_CPUVR_VDD	Default	d	0.40
PP5V_S0_CPUVR_VDD	Default	v	5.095
PP5V_S0_FET	Default	d	0.437
PP5V_S0_FET	Default	v	5.000
PP5V_S0_KBDBKLT_SW	Default	d	0.40
PP5V_S3RS0_ALSCAM_F	Default	d	0.436
PP5V_S3_LTUSB_A_ILIM	Default	d	0.51
PP5V_S4	Default	d	0.400
PP5V_S4	Default	v	3.300
PP5V_S4_CUMULUS	Default	d	0.57
PP5V_S5	Default	d	0.479
PP5V_S5	Default	v	5.000
PPBUS_G3H	Default	d	0.161
PPBUS_G3H	Default	v	12.500
PPBUS_S5_HS_COMPUTING	Default	d	0.162
PPBUS_S5_HS_COMPUTING	Default	v	12.500
PPBUS_S5_HS_OTHER3V3	Default	d	0.162
PPBUS_S5_HS_OTHER3V3	Default	v	12.500
PPBUS_S5_HS_OTHER5V	Default	d	0.162
PPBUS_S5_HS_OTHER5V	Default	v	12.500
PPDCIN_G3H	Default	d	0.688
PPDCIN_G3H	Default	v	16.720
PPDCIN_G3H_ISOL	Default	d	OL
PPDCIN_G3H_ISOL	Default	v	16.720
PPDDR_S3_REG_R	Default	d	0.110
PPVBAT_G3H_CHGR_REG	Default	d	0.161
PPVBAT_G3H_CHGR_REG	Default	v	12.500
PPVCC_S0_CPU	Default	d	0.057
PPVCC_S0_CPU	Default	v	1.800
PPVCC_S0_CPU_PH1	Default	d	0.057
PPVCC_S0_CPU_PH2	Default	d	0.057
PPVIN_S0SW_LCDBKLT	Default	d	0.87
PPVIN_S0SW_LCDBKLT_R	Default	d	0.14
PPVIN_S0_CPUVR_VIN	Default	d	0.15
PPVIN_S0_CPUVR_VIN	Default	v	12.580
PPVIN_SW_LCDBKLT_SW	Default	d	0.870
PPVIN_SW_TBTBST	Default	d	0.525
PPVOUT_BKLT_FB2	Default	d	0.60
PPVOUT_S5_PCH_DCPSUSBYP	Default	d	0.278
PPVOUT_S5_PCH_DCPSUSBYP	Default	v	1.075
PPVRTC_G3H	Default	d	0.453
PPVRTC_G3H	Default	v	3.300
PPVTTDDR_S3	Default	d	0.496
PPVTTDDR_S3	Default	v	0.600
PSOC_F_CS_L	Default	d	0.72
PSOC_MISO	Default	d	0.72
PSOC_MOSI	Default	d	0.72
PSOC_SCLK	Default	d	0.72
S5_PWRGD	Default	d	0.57
S5_PWRGD	Default	v	3.300
S5_PWR_EN	Default	d	0.53
S5_PWR_EN	Default	v	3.400
SMBUS_SMC_1_S0_SCL	Default	d	0.58
SMBUS_SMC_1_S0_SDA	Default	d	0.58
SMBUS_SMC_2_S3_SCL	Default	d	0.75
SMBUS_SMC_2_S3_SDA	Default	d	0.75
SMBUS_SMC_5_G3_SCL	Default	d	0.51
SMBUS_SMC_5_G3_SCL	Default	v	3.300
SMBUS_SMC_5_G3_SDA	Default	d	0.51
SMBUS_SMC_5_G3_SDA	Default	v	3.300
SMC_ADAPTER_EN	Default	d	0.610
SMC_ADAPTER_EN	Default	v	3.300
SMC_BC_ACOK	Default	d	0.52
SMC_BC_ACOK	Default	v	3.300
SMC_DELAYED_PWRGD	Default	d	0.69
SMC_MANUAL_RST_L	Default	d	0.66
SMC_MANUAL_RST_L	Default	v	2.700
SMC_ONOFF_L	Default	d	0.65
SMC_ONOFF_L	Default	v	3.400
SMC_PM_G2_EN	Default	d	0.554
SMC_PM_G2_EN	Default	v	3.400
SMC_PROCHOT	Default	d	0.74
SMC_RESET_L	Default	d	0.510
SMC_RESET_L	Default	v	3.300
SMC_ROMBOOT	Default	d	1.40
SMC_RX_L	Default	d	0.74
SMC_S4_WAKESRC_EN	Default	d	0.744
SMC_SENSOR_PWR_EN	Default	d	0.67
SMC_TCK	Default	d	0.74
SMC_TDI	Default	d	0.74
SMC_TDO	Default	d	0.74
SMC_TMS	Default	d	0.74
SMC_TPAD_RST_L	Default	d	0.46
SMC_TX_L	Default	d	0.74
SMS_INT_L	Default	v	3.400
SPDIF_OUT_JACK	Default	d	0.687
SPIROM_HOLD_L	Default	d	0.490
SPIROM_HOLD_L	Default	v	3.200
SPIROM_USE_MLB	Default	d	0.49
SPIROM_WP_L	Default	d	0.64
SPIROM_WP_L	Default	v	3.300
SPI_ALT_CLK	Default	d	0.58
SPI_ALT_CS_L	Default	d	0.56
SPI_ALT_MISO	Default	d	0.50
SPI_ALT_MOSI	Default	d	0.51
SPI_DESCRIPTOR_OVERRIDE_L	Default	d	0.745
SPI_MLB_CLK	Default	d	0.580
SPI_MLB_CLK	Default	v	3.300
SPI_MLB_CS_L	Default	d	0.56
SPI_MLB_CS_L	Default	v	3.300
SPI_MLB_MISO	Default	d	0.50
SPI_MLB_MISO	Default	v	3.300
SPI_MLB_MOSI	Default	d	0.510
SPI_MLB_MOSI	Default	v	3.300
SPKRCONN_L_ID	Default	d	0.751
SPKRCONN_R_ID	Default	d	0.73
SPKRCONN_R_OUT_N	Default	d	0.50
SPKRCONN_R_OUT_P	Default	d	0.50
SPKRCONN_SR_OUT_N	Default	d	0.62
SPKRCONN_SR_OUT_P	Default	d	0.62
SPKR_SHUTDOWN	Default	d	0.533
SSD_PWR_EN	Default	d	0.148
SUS_PGOOD_CT	Default	d	0.63
SYSCLK_CLK25M_CAMERA	Default	d	0.45
SYSCLK_CLK25M_TBT	Default	d	0.44
SYSCLK_CLK25M_X1	Default	d	0.45
SYSCLK_CLK25M_X2_R	Default	d	0.45
SYS_PWROK_R	Default	d	0.68
TBTBST_EN_UVLO	Default	d	0.615
TBTDP_AUXIO_EN	Default	d	0.780
TBT_A_CIO_SEL	Default	d	0.796
TBT_A_CONFIG1_BUF	Default	d	0.797
TBT_A_CONFIG1_RC	Default	d	0.838
TBT_A_D2R1_AUXDDC_N	Default	d	0.760
TBT_A_D2R1_AUXDDC_P	Default	d	0.760
TBT_A_D2R_C_N<1>	Default	d	0.777
TBT_A_D2R_C_P<1>	Default	d	0.777
TBT_A_DP_PWRDN	Default	d	0.795
TBT_A_HPD	Default	d	0.818
TBT_A_LSRX	Default	d	0.784
TBT_A_LSTX	Default	d	0.773
TBT_B_CIO_SEL	Default	d	0.801
TBT_B_CONFIG1_BUF	Default	d	0.780
TBT_B_CONFIG1_RC	Default	d	0.845
TBT_B_D2R1_AUXDDC_N	Default	d	0.760
TBT_B_D2R1_AUXDDC_P	Default	d	0.760
TBT_B_D2R_C_N<1>	Default	d	0.773
TBT_B_D2R_C_P<1>	Default	d	0.773
TBT_B_DP_PWRDN	Default	d	0.803
TBT_B_HPD	Default	d	0.845
TBT_B_LSRX	Default	d	0.791
TBT_B_LSTX	Default	d	0.767
TP_SUS_PGOOD_MR_L	Default	d	0.69
UNCONNECTED_50	Default	d	0.45
UNCONNECTED_99	Default	d	OL
USB_ILIM	Default	d	0.54
USB_PWR_EN	Default	d	0.49
VHP_FILTN	Default	d	0.907
VREF_DAC	Default	d	0.740
XDP_CPU_PWRBTN_L	Default	d	0.565
XDP_CPU_PWRBTN_L	Default	v	3.400
XDP_LPCPLUS_GPIO	Default	d	0.54
XDP_USB_EXTA_OC_L	Default	d	0.49
Z2_CLKIN	Default	d	0.73
Z2_CS_L	Default	d	0.72
Z2_HOST_INTN	Default	d	0.72
Z2_KEY_ACT_L	Default	d	0.72
Z2_MISO	Default	d	0.72
Z2_MOSI	Default	d	0.72
Z2_SCLK	Default	d	0.72
PCIE_WAKE_L	mes donn˙˙es	d	-

Component values

• v = value (1uF, 410R)
• r = rating (25V)
• c = Manufacturer code
• p = Package (SOT23-5)
• m = misc
• s = status ('-' = no stuff )

Component	Type	Value

---