Netname | Condition | Type | Value | Comment |
---|---|---|---|---|
4V5_NR | Default | d | 0.659 | |
4V5_REG_EN | Default | d | 0.733 | |
4V5_REG_IN | Default | d | 0.443 | |
ADAPTER_SENSE | Default | d | 0.642 | |
ALL_SYS_PWRGD | Default | d | 0.469 | |
ALL_SYS_PWRGD_R | Default | d | OL | |
AP_CLKREQ_L | Default | d | 0.445 | |
AP_CLKREQ_Q_L | Default | d | 0v46 | |
AP_RESET_CONN_L | Default | d | 0v46 | |
AP_RESET_L | Default | d | 0.425 | |
AUD_CONN_HP_LEFT | Default | d | 0.660 | |
AUD_CONN_SLEEVE_XW | Default | d | 0.001 | |
AUD_HP_PORT_L | Default | d | 0.660 | |
AUD_HP_PORT_R | Default | d | 0.661 | |
AUD_HS_MIC_N | Default | d | 0.002 | |
AUD_HS_MIC_P | Default | d | 0.001 | |
AUD_I2C_INT_L | Default | d | 0.655 | |
AUD_IP_PERIPHERAL_DET | Default | d | 0.660 | |
AUD_LO2_L_N | Default | d | 0.673 | |
AUD_LO2_L_P | Default | d | 0.673 | |
AUD_LO2_R_N | Default | d | 0.673 | |
AUD_LO2_R_P | Default | d | 0.673 | |
AUD_LO3_L_N | Default | d | 0.659 | |
AUD_LO3_L_P | Default | d | 0.661 | |
AUD_LO3_R_N | Default | d | 0.659 | |
AUD_LO3_R_P | Default | d | 0.660 | |
AUD_SPKRAMP_LIN_N | Default | d | 0.674 | |
AUD_SPKRAMP_LIN_P | Default | d | 0.675 | |
AUD_SPKRAMP_LSUBIN_N | Default | d | 0.660 | |
AUD_SPKRAMP_LSUBIN_P | Default | d | 0.663 | |
AUD_SPKRAMP_RIN_N | Default | d | 0.674 | |
AUD_SPKRAMP_RIN_P | Default | d | 0.675 | |
AUD_SPKRAMP_RSUBIN_N | Default | d | 0.660 | |
AUD_SPKRAMP_RSUBIN_P | Default | d | 0.660 | |
AUD_TYPEDET | Default | d | 0.772 | |
BKLT_EN_R | Default | d | 0v53 | |
BKLT_EN_R_JERRY | Default | d | 0v53 | |
BKLT_FLT | Default | d | 0v73 | |
BKLT_FLT_RC | Default | d | OL | |
BKLT_ISET_KEYB | Default | d | 0v66 | |
BKLT_ISET_LCD | Default | d | 0v74 | |
BKLT_KEYB1 | Default | d | 0v64 | |
BKLT_KEYB2 | Default | d | 0v64 | |
BKLT_PWM_KEYB | Default | d | 0v54 | |
BKLT_SCL | Default | d | 0v51 | |
BKLT_SCL_R | Default | d | 0v51 | |
BKLT_SD | Default | d | 6v58 | |
BKLT_SDA | Default | d | 0v51 | |
BKLT_SDA_R | Default | d | 0v51 | |
BKLT_SENSE_OUT | Default | d | 0v72 | |
BKLT_SYNC | Default | d | 0v41 | |
BKL_1_SCL | Default | d | 0v50 | |
BKL_1_SDA | Default | d | 0v50 | |
BKL_FB | Default | d | 0v72 | |
BKL_FET_CNTL | Default | d | 0v50 | |
BKL_FET_CNTL_R | Default | d | 0.548 | |
BKL_ISEN1 | Default | d | 0v65 | |
BKL_ISEN2 | Default | d | 0v65 | |
BKL_ISEN3 | Default | d | 0v65 | |
BKL_ISEN4 | Default | d | 0v65 | |
BKL_ISEN5 | Default | d | 0v65 | |
BKL_ISEN6 | Default | d | 0v65 | |
BKL_SW | Default | d | 0v44 | |
CAMERA_CLKREQ_L | Default | d | 0.507 | |
CAMERA_PWR_EN | Default | d | 0.544 | |
CAM_DEBUG_RESET_L | Default | d | 0.777 | |
CAM_GPIO3 | Default | d | 0.777 | |
CAM_PCIE_RESET_L | Default | d | 0.428 | |
CAM_PCIE_WAKE_L | Default | d | 0.532 | |
CAM_RAMCFG0 | Default | d | 0.777 | |
CAM_RAMCFG1 | Default | d | 0.777 | |
CAM_RAMCFG2 | Default | d | 0.777 | |
CAM_SENSOR_WAKE_L | Default | d | 0.825 | |
CAM_SENSOR_WAKE_L_CONN | Default | d | 0v00 | |
CAM_TEST_MODE | Default | d | 0.774 | |
CAM_TEST_OUT | Default | d | 0.829 | |
CAM_UARTRXD | Default | d | 0.777 | |
CAM_XTAL_SEL | Default | d | 0.778 | |
CHGR_ACIN | Default | d | 0v53 | |
CHGR_AGATE | Default | d | 0v65 | |
CHGR_AGATE_DIV | Default | d | OL | |
CHGR_AMON | Default | d | 0v72 | |
CHGR_BGATE | Default | d | 0v66 | |
CHGR_BMON | Default | d | 0v72 | |
CHGR_BOOT | Default | d | 0v59 | |
CHGR_CELL | Default | d | 0v71 | |
CHGR_CSI_N | Default | d | 0v59 | |
CHGR_CSI_N | Default | r | 21.900R | |
CHGR_CSI_P | Default | d | 0v62 | |
CHGR_CSI_P | Default | r | 21.900R | |
CHGR_CSI_R_N | Default | d | 0.649 | |
CHGR_CSI_R_P | Default | d | 0.648 | |
CHGR_CSO_N | Default | d | 0v45 | |
CHGR_CSO_N | Default | r | 3.500R | |
CHGR_CSO_P | Default | d | 0v45 | |
CHGR_CSO_P | Default | r | 3.500R | |
CHGR_CSO_R_N | Default | d | 0.450 | |
CHGR_CSO_R_P | Default | d | 0.450 | |
CHGR_DCIN | Default | d | 0v59 | |
CHGR_DCIN_D_R | Default | d | 0.607 | |
CHGR_ICOMP | Default | d | 0v72 | |
CHGR_ICOMP_RC | Default | d | 1.734 | |
CHGR_LGATE | Default | d | 0v45 | |
CHGR_PHASE | Default | d | 0v45 | |
CHGR_RST_L | Default | d | 0v51 | |
CHGR_SGATE | Default | d | 0v64 | |
CHGR_SGATE_DIV | Default | d | OL | |
CHGR_UGATE | Default | d | 0v89 | |
CHGR_VCOMP | Default | d | 0v72 | |
CHGR_VCOMP_R | Default | d | OL | |
CHGR_VFRQ | Default | d | 0v48 | |
CHGR_VNEG | Default | d | 0v53 | |
CLK25M_CAM_XTALN | Default | d | OL | |
CLK25M_CAM_XTALP | Default | d | OL | |
CLK25M_CAM_XTALP_R | Default | d | OL | |
CODEC_MICIN2 | Default | d | 0.713 | |
CPUTHMSNS_ALERT_L | Default | v | 3.30 | |
CPUTHMSNS_D2_N | Default | d | 0.764 | |
CPUTHMSNS_D2_N | Default | v | 0.70 | |
CPUTHMSNS_D2_P | Default | d | 0.763 | |
CPUTHMSNS_D2_P | Default | v | 0.80 | |
CPUTHMSNS_THM_L | Default | d | 0.761 | |
CPUTHMSNS_THM_L | Default | v | 3.30 | |
CPUVDDQ_EN | Default | d | 0.559 | |
CPUVDDQ_EN_L | Default | d | 0.598 | |
CPUVR_BOOT1 | Default | d | 0v57 | |
CPUVR_BOOT1_RC | Default | d | 0.611 | |
CPUVR_BOOT2 | Default | d | 0v56 | |
CPUVR_BOOT2_RC | Default | d | 0.611 | |
CPUVR_BOOT3 | Default | d | 0v57 | |
CPUVR_BOOT3_RC | Default | d | 0.611 | |
CPUVR_COMP | Default | d | 0.587 | |
CPUVR_COMP_RC | Default | d | OL | |
CPUVR_DRSEL | Default | d | 0.600 | |
CPUVR_FB2 | Default | d | 0.575 | |
CPUVR_FB_RC | Default | d | OL | |
CPUVR_FCCM | Default | d | 0v48 | |
CPUVR_IMON | Default | d | 0.589 | |
CPUVR_ISEN2 | Default | d | 0.585 | |
CPUVR_ISEN3 | Default | d | 0.584 | |
CPUVR_ISNS1_N | Default | d | 0.013 | |
CPUVR_ISNS1_P | Default | d | 0.013 | |
CPUVR_ISNS2_N | Default | d | 0.013 | |
CPUVR_ISNS2_P | Default | d | 0.013 | |
CPUVR_ISNS3_N | Default | d | 0.013 | |
CPUVR_ISNS3_P | Default | d | 0.013 | |
CPUVR_ISNS_N | Default | d | OL | |
CPUVR_ISNS_P | Default | d | OL | |
CPUVR_ISUMN | Default | d | 0.014 | |
CPUVR_ISUMP | Default | d | 0.348 | |
CPUVR_ISUM_IOUT | Default | d | 0.592 | |
CPUVR_ISUM_R_N | Default | d | OL | |
CPUVR_ISUM_R_P | Default | d | OL | |
CPUVR_NTC | Default | d | 0.598 | |
CPUVR_NTC_R | Default | d | OL | |
CPUVR_PGOOD | Default | d | 0.539 | |
CPUVR_PH1_SNUB | Default | d | OL | |
CPUVR_PH2_SNUB | Default | d | OL | |
CPUVR_PH3_SNUB | Default | d | OL | |
CPUVR_PHASE1 | Default | d | 0.013 | |
CPUVR_PHASE1 | Default | r | 18.400R | |
CPUVR_PHASE1_K | Default | d | 0v02 | |
CPUVR_PHASE2 | Default | d | 0.013 | |
CPUVR_PHASE2 | Default | r | 18.400R | |
CPUVR_PHASE2_K | Default | d | 0v02 | |
CPUVR_PHASE3 | Default | d | 0.013 | |
CPUVR_PHASE3 | Default | r | 18.400R | |
CPUVR_PHASE3_K | Default | d | 0v02 | |
CPUVR_PROG1 | Default | d | 0.590 | |
CPUVR_PROG2 | Default | d | 0.589 | |
CPUVR_PROG3 | Default | d | 0.600 | |
CPUVR_PWM1 | Default | d | 0v51 | |
CPUVR_PWM2 | Default | d | 0v52 | |
CPUVR_PWM3 | Default | d | 0v52 | |
CPUVR_SLOPE | Default | d | 0.589 | |
CPUVSENSE_IN | Default | d | OL | |
CPU_CATERR_L | Default | d | 0.273 | |
CPU_CFG<0> | Default | d | 0v25 | |
CPU_CFG<10> | Default | d | 0v25 | |
CPU_CFG<11> | Default | d | 0v25 | |
CPU_CFG<12> | Default | d | 0v25 | |
CPU_CFG<13> | Default | d | 0v25 | |
CPU_CFG<14> | Default | d | 0v25 | |
CPU_CFG<15> | Default | d | 0v25 | |
CPU_CFG<16> | Default | d | 0v25 | |
CPU_CFG<17> | Default | d | 0v26 | |
CPU_CFG<18> | Default | d | 0v25 | |
CPU_CFG<19> | Default | d | 0v25 | |
CPU_CFG<1> | Default | d | 0v25 | |
CPU_CFG<2> | Default | d | 0v25 | |
CPU_CFG<3> | Default | d | 0v25 | |
CPU_CFG<4> | Default | d | 0v24 | |
CPU_CFG<5> | Default | d | 0v25 | |
CPU_CFG<6> | Default | d | 0v25 | |
CPU_CFG<7> | Default | d | 0v25 | |
CPU_CFG<8> | Default | d | 0v25 | |
CPU_CFG<9> | Default | d | 0v25 | |
CPU_CFG_RCOMP | Default | d | 0.050 | |
CPU_CLK135M_DPLLREF_N | Default | d | 0.292 | |
CPU_CLK135M_DPLLREF_P | Default | d | 0.293 | |
CPU_CLK135M_DPLLSS_N | Default | d | 0.293 | |
CPU_CLK135M_DPLLSS_P | Default | d | 0.294 | |
CPU_DC_A4 | Default | d | OL | |
CPU_DC_A51 | Default | d | OL | |
CPU_DC_BC1 | Default | d | OL | |
CPU_DC_BC54 | Default | d | OL | |
CPU_DC_BF4 | Default | d | OL | |
CPU_DC_BF51 | Default | d | OL | |
CPU_DC_D1 | Default | d | OL | |
CPU_DC_D54 | Default | d | OL | |
CPU_DIMMA_VREFDQ | Default | d | 0.778 | |
CPU_DIMMB_VREFDQ | Default | d | 0.780 | |
CPU_DIMM_VREFCA | Default | d | 0.778 | |
CPU_EDP_RCOMP | Default | d | 0.065 | |
CPU_MEM_RESET_L | Default | d | 0.338 | |
CPU_MEM_VREFCA_A_ISOL | Default | d | 0.378 | |
CPU_MEM_VREFCA_B_ISOL | Default | d | 0.375 | |
CPU_MEM_VREFDQ_A_ISOL | Default | d | 0.378 | |
CPU_MEM_VREFDQ_B_ISOL | Default | d | 0.375 | |
CPU_PECI | Default | d | 0.375 | |
CPU_PECI_R | Default | d | 0.334 | |
CPU_PEG_RCOMP | Default | d | 0.063 | |
CPU_PROCHOT_L | Default | d | 0.081 | |
CPU_PROCHOT_R_L | Default | d | 0.135 | |
CPU_PWRGD | Default | d | 0.362 | |
CPU_PWR_DEBUG | Default | d | 0v21 | |
CPU_RESET_L | Default | d | 0.368 | |
CPU_SM_RCOMP<0> | Default | d | 0.104 | |
CPU_SM_RCOMP<1> | Default | v | 0.076 | |
CPU_SM_RCOMP<2> | Default | d | 0.104 | |
CPU_TESTLO_F20 | Default | d | 0.052 | |
CPU_TESTLO_F21 | Default | d | 0.052 | |
CPU_THRMTRIP_3V3 | Default | d | 0.749 | |
CPU_VCCSENSE_N | Default | d | 0.002 | |
CPU_VCCSENSE_P | Default | d | 0.014 | |
CPU_VCCSENSE_P_RC | Default | d | 1.565 | |
CPU_VIDALERT_L | Default | d | 0.094 | |
CPU_VIDALERT_R_L | Default | d | 0.136 | |
CPU_VIDSCLK | Default | d | 0.071 | |
CPU_VIDSCLK_R | Default | d | 0.075 | |
CPU_VIDSOUT | Default | d | 0.074 | |
CPU_VIDSOUT_R | Default | d | 0.073 | |
CS4208_HDA_SDOUT0_R | Default | d | 0.439 | |
CS4208_SPDIF_IN | Default | d | 0.000 | |
CS4208_SPDIF_OUT | Default | d | 0.692 | |
DBGLED_S0 | Default | d | OL | |
DBGLED_S0_D | Default | d | OL | |
DBGLED_S3 | Default | d | OL | |
DBGLED_S3_D | Default | d | OL | |
DBGLED_S4 | Default | d | OL | |
DBGLED_S4_D | Default | d | OL | |
DBGLED_S5 | Default | d | OL | |
DCINVSENS_EN_L | Default | d | 0.502 | |
DCIN_ISOL_GATE | Default | d | 0.783 | |
DCIN_ISOL_GATE_R | Default | d | OL | |
DCIN_S5_VSENSE | Default | d | OL | |
DDR3THMSNS_D1_N | Default | d | 0.777 | |
DDR3THMSNS_D1_N | Default | v | 0.500 | |
DDR3THMSNS_D1_P | Default | d | 0.780 | |
DDR3THMSNS_D1_P | Default | v | 0.800 | |
DDRREG_1V8_VREF | Default | d | 0.644 | |
DDRREG_DRVH | Default | d | 0.597 | |
DDRREG_DRVH_R | Default | d | 0.598 | |
DDRREG_DRVL | Default | d | 0.453 | |
DDRREG_EN | Default | d | 0.548 | |
DDRREG_FB | Default | d | 0.692 | |
DDRREG_LL | Default | d | 0.124 | |
DDRREG_VBST | Default | d | 0.622 | |
DDRREG_VDDQSNS | Default | d | 0.124 | |
DDRREG_VSW | Default | d | 0.130 | |
DDRREG_VTTSNS | Default | d | 0.097 | |
DELAY_1V5S0_PGD | Default | d | 0.464 | |
DFET_CPO1 | Default | d | 0.589 | |
DFET_CPO2 | Default | d | 0.587 | |
DFET_OPENCH | Default | d | 0.463 | |
DFET_OPENUS | Default | d | 0.463 | |
DMIC_CLK3 | Default | d | 0v77 | |
DMIC_SDA2 | Default | d | 0v00 | |
DMIC_SDA3 | Default | d | 0v76 | |
DMI_CLK100M_CPU_N | Default | d | 0.295 | |
DMI_CLK100M_CPU_P | Default | d | 0.296 | |
DMI_S2N_N<0> | Default | d | 0.291 | |
DMI_S2N_P<0> | Default | d | 0.292 | |
DP_A_LSX_ML_N<1> | Default | d | 0.756 | |
DP_IG_A_HPD_L | Default | d | 0.440 | |
DP_INT_AUXCH_C_N | Default | d | 0.302 | |
DP_INT_AUXCH_C_P | Default | d | 0.300 | |
DP_INT_AUX_N | Default | d | OL | |
DP_INT_AUX_P | Default | d | OL | |
DP_INT_ML_C_N<0> | Default | d | 0.308 | |
DP_INT_ML_C_N<1> | Default | d | 0.306 | |
DP_INT_ML_C_N<2> | Default | d | 0.307 | |
DP_INT_ML_C_P<0> | Default | d | 0.307 | |
DP_INT_ML_C_P<1> | Default | d | 0.308 | |
DP_INT_ML_C_P<2> | Default | d | 0.308 | |
DP_INT_ML_N<0> | Default | d | OL | |
DP_INT_ML_N<1> | Default | d | OL | |
DP_INT_ML_N<2> | Default | d | OL | |
DP_INT_ML_N<3> | Default | d | OL | |
DP_INT_ML_P<0> | Default | d | OL | |
DP_INT_ML_P<1> | Default | d | OL | |
DP_INT_ML_P<2> | Default | d | OL | |
DP_INT_ML_P<3> | Default | d | OL | |
DP_TBTPA_AUXCH_C_N | Default | d | 0.567 | |
DP_TBTPA_AUXCH_C_P | Default | d | 0.616 | |
DP_TBTPA_DDC_CLK | Default | d | 0v55 | |
DP_TBTPA_DDC_DATA | Default | d | 0v55 | |
DP_TBTPA_HPD | Default | d | 0.774 | |
DP_TBTPA_ML_C_N<1> | Default | d | 0.316 | |
DP_TBTPA_ML_C_P<1> | Default | d | 0.314 | |
DP_TBTPA_ML_N<1> | Default | d | 0.768 | |
DP_TBTPA_ML_P<1> | Default | d | 0.767 | |
DP_TBTPB_AUXCH_N | Default | d | 0.753 | |
DP_TBTPB_AUXCH_P | Default | d | 0.753 | |
DP_TBTPB_DDC_CLK | Default | d | 0v55 | |
DP_TBTPB_DDC_DATA | Default | d | 0v55 | |
DP_TBTSNK0_AUXCH_C_N | Default | d | 0.408 | |
DP_TBTSNK0_AUXCH_C_P | Default | d | 0.410 | |
DP_TBTSNK0_DDC_CLK | Default | d | 0v56 | |
DP_TBTSNK0_DDC_DATA | Default | d | 0v56 | |
DP_TBTSNK0_HPD | Default | d | 0.568 | |
DP_TBTSNK1_AUXCH_C_N | Default | d | 0.406 | |
DP_TBTSNK1_AUXCH_C_P | Default | d | 0.408 | |
DP_TBTSNK1_DDC_CLK | Default | d | 0v56 | |
DP_TBTSNK1_DDC_DATA | Default | d | 0v56 | |
DP_TBTSNK1_HPD | Default | d | 0.570 | |
DP_TBT_SEL | Default | d | 0.542 | |
EDP_IG_BKL_ON | Default | d | 0.548 | |
EDP_IG_BKL_PWM | Default | d | 0.541 | |
EDP_IG_PANEL_PWR | Default | d | 0.654 | |
ENET_MEDIA_SENSE_RDIV | Default | d | 0.412 | |
FAN_LT_PWM | Default | v | 0.70 | |
FAN_LT_TACH | Default | v | 1.10 | |
FAN_RT_PWM | Default | v | 4.00 | |
FAN_RT_TACH | Default | v | 1.68 | |
FDI_CSYNC | Default | d | 0.378 | |
FDI_INT | Default | d | 0.377 | |
FINTHMSNS_D_N | Default | d | 0.780 | |
FINTHMSNS_D_P | Default | d | 0.787 | |
FW_PME_L | Default | d | 0.700 | |
G3_POWERON_L | Default | d | 0.750 | |
GND | Default | v | 0.00 | |
GND_5V3V3_AGND | Default | d | 0v00 | |
GND_BKLT_SGND | Default | d | 0v00 | |
GND_CHGR_AGND | Default | d | 0v00 | |
GND_LCDBKLT_SGND | Default | d | 0v00 | |
GND_TBTBST_SGND | Default | d | 0v00 | |
GPIO0_SPKR_SHUTDOWN | Default | d | 0.529 | |
HDA_BIT_CLK | Default | d | 0.463 | |
HDA_BIT_CLK_R | Default | d | 0.424 | |
HDA_RST_L | Default | d | 0.457 | |
HDA_RST_R_L | Default | d | 0.424 | |
HDA_SDIN0 | Default | d | 0.416 | |
HDA_SDOUT | Default | d | 0.465 | |
HDA_SDOUT_R | Default | d | 0.427 | |
HDA_SYNC | Default | d | 0.465 | |
HDMITBTMUX_SEL_TBT | Default | d | 0.610 | |
HDMI_CLK_N | Default | d | 0.305 | |
HDMI_CLK_P | Default | d | 0.305 | |
HDMI_DATA_N<0> | Default | d | 0.304 | |
HDMI_DATA_N<1> | Default | d | 0.306 | |
HDMI_DATA_N<2> | Default | d | 0.308 | |
HDMI_DATA_P<0> | Default | d | 0.305 | |
HDMI_DATA_P<1> | Default | d | 0.305 | |
HDMI_DATA_P<2> | Default | d | 0.307 | |
HDMI_DDC_CLK | Default | d | 0v60 | |
HDMI_DDC_DATA | Default | d | 0v60 | |
HDMI_HPD | Default | d | 0v78 | |
HS_COMPUTING_IOUT | Default | d | 0.713 | |
HS_MIC_N | Default | d | 2.091 | |
HS_MIC_P | Default | d | 2.060 | |
HS_OTHER3V3_IOUT | Default | d | 0.712 | |
HS_OTHER5V_IOUT | Default | d | 0.711 | |
I2C_CAM_SCK | Default | d | 0v75 | |
I2C_CAM_SDA | Default | d | 0v75 | |
I2C_CAM_SMBDBG_CLK | Default | d | 0.789 | |
I2C_CAM_SMBDBG_DAT | Default | d | 0.789 | |
ISENSE_P1V35MEM_IOUT | Default | d | 0.655 | |
ISNS_1V35_MEM_N | Default | d | 0.125 | |
ISNS_1V35_MEM_P | Default | d | 0.125 | |
ISNS_1V35_MEM_R_N | Default | d | 0.795 | |
ISNS_1V35_MEM_R_P | Default | d | 0.800 | |
ISNS_AIRPORT_IOUT | Default | d | OL | |
ISNS_AIRPORT_R_N | Default | d | OL | |
ISNS_AIRPORT_R_P | Default | d | OL | |
ISNS_CPUDDR_N | Default | d | OL | |
ISNS_CPUDDR_P | Default | d | OL | |
ISNS_CPU_DDR_IOUT | Default | d | OL | |
ISNS_HS_COMPUTING_N | Default | d | 0.450 | |
ISNS_HS_COMPUTING_P | Default | d | 0.450 | |
ISNS_HS_OTHER3V3_N | Default | d | 0.450 | |
ISNS_HS_OTHER3V3_P | Default | d | 0.450 | |
ISNS_HS_OTHER5V_N | Default | d | 0.450 | |
ISNS_HS_OTHER5V_P | Default | d | 0.450 | |
ISNS_LCDBKLT_N | Default | d | 0v45 | |
ISNS_LCDBKLT_P | Default | d | 0v46 | |
ISNS_S2_OUT | Default | d | OL | |
ISNS_S2_R_N | Default | d | OL | |
ISNS_S2_R_P | Default | d | OL | |
ISNS_SSD_IOUT | Default | d | 0.652 | |
ISNS_SSD_N | Default | d | 0.658 | |
ISNS_SSD_P | Default | d | 0.658 | |
ISNS_SSD_R_N | Default | d | 0.799 | |
ISNS_SSD_R_P | Default | d | 0.797 | |
ISNS_TBT_IOUT | Default | d | 0.645 | |
ISNS_TBT_R_N | Default | d | 0.794 | |
ISOLATE_CPU_MEM_L | Default | d | 0.586 | |
JTAG_ISP_TCK | Default | d | 0.500 | |
JTAG_ISP_TDI | Default | d | 0.463 | |
JTAG_ISP_TDO | Default | d | 0.462 | |
JTAG_TBT_TCK | Default | d | 0.565 | |
JTAG_TBT_TDI | Default | d | 0.533 | |
JTAG_TBT_TDO | Default | d | 0.552 | |
JTAG_TBT_TMS | Default | d | 0.532 | |
JTAG_TBT_TMS_PCH | Default | d | 0.470 | |
KBDBKLT_RETURN1 | Default | d | 0v65 | |
KBDBKLT_RETURN2 | Default | d | 0v64 | |
KBDBKLT_SW | Default | d | 0v41 | |
LCDBKLT_EN_L | Default | d | OL | |
LCDBKLT_IOUT | Default | d | OL | |
LCD_BKLT_PWM_R | Default | d | 0v53 | |
LCD_FSS | Default | d | OL | |
LCD_HPD | Default | d | OL | |
LCD_HPD_CONN | Default | d | OL | |
LCD_PANEL_IOUT | Default | d | OL | |
LED_RETURN_1 | Default | d | 0v64 | |
LED_RETURN_2 | Default | d | 0v64 | |
LED_RETURN_2 | Default | t | 485 | |
LED_RETURN_3 | Default | d | 0v64 | |
LED_RETURN_3 | Default | t | 499 | |
LED_RETURN_4 | Default | d | 0v64 | |
LED_RETURN_4 | Default | t | 468 | |
LED_RETURN_5 | Default | d | 0v64 | |
LED_RETURN_5 | Default | t | 462 | |
LED_RETURN_6 | Default | d | 0v65 | |
LED_RETURN_6 | Default | t | 548 | |
LPCPLUS_GPIO | Default | d | 0v62 | |
LPCPLUS_RESET_L | Default | d | 0v57 | |
LPC_AD<0> | Default | d | 0v54 | |
LPC_AD<1> | Default | d | 0v54 | |
LPC_AD<2> | Default | d | 0v54 | |
LPC_AD<3> | Default | d | 0v54 | |
LPC_CLK33M_LPCPLUS | Default | d | 0v60 | |
LPC_CLK33M_LPCPLUS_R | Default | d | 0.611 | |
LPC_CLK33M_SMC | Default | d | 0.627 | |
LPC_CLK33M_SMC_R | Default | d | 0.604 | |
LPC_FRAME_L | Default | d | 0v54 | |
LPC_FRAME_R_L | Default | d | 0.531 | |
LPC_PWRDWN_L | Default | d | 0v62 | |
LPC_SERIRQ | Default | d | 0v62 | |
LSUBIN_N | Default | d | 0.596 | |
LSUBIN_P | Default | d | 0.596 | |
MEMPWR_DIV | Default | d | OL | |
MEMRESET_ISOL_LS5V_L | Default | d | 1.010 | |
MEMVTT_EN | Default | d | 0.547 | |
MEMVTT_EN_L | Default | d | 0.603 | |
MEM_A_A<0> | Default | d | 0.131 | |
MEM_A_A<10> | Default | d | 0.131 | |
MEM_A_A<11> | Default | d | 0.129 | |
MEM_A_A<12> | Default | d | 0.132 | |
MEM_A_A<14> | Default | d | 0.132 | |
MEM_A_A<1> | Default | d | 0.131 | |
MEM_A_A<2> | Default | d | 0.131 | |
MEM_A_A<4> | Default | d | 0.131 | |
MEM_A_A<5> | Default | d | 0.131 | |
MEM_A_A<7> | Default | d | 0.131 | |
MEM_A_A<8> | Default | d | 0.131 | |
MEM_A_BA<0> | Default | d | 0.129 | |
MEM_A_BA<1> | Default | d | 0.130 | |
MEM_A_BA<2> | Default | d | 0.131 | |
MEM_A_CAS_L | Default | d | 0.130 | |
MEM_A_CKE<0> | Default | d | 0.130 | |
MEM_A_CKE<1> | Default | d | 0.130 | |
MEM_A_CS_L<0> | Default | d | 0.130 | |
MEM_A_CS_L<1> | Default | d | 0.131 | |
MEM_A_DQ<13> | Default | d | 0.268 | |
MEM_A_DQ<18> | Default | d | 0.270 | |
MEM_A_DQ<21> | Default | d | 0.270 | |
MEM_A_DQ<38> | Default | d | 0.262 | |
MEM_A_DQ<54> | Default | d | 0.267 | |
MEM_A_DQ<55> | Default | d | 0.267 | |
MEM_A_ODT<0> | Default | d | 0.130 | |
MEM_A_ODT<1> | Default | d | 0.130 | |
MEM_B_A<0> | Default | d | 0v13 | |
MEM_B_A<10> | Default | d | 0v13 | |
MEM_B_A<11> | Default | d | 0v13 | |
MEM_B_A<12> | Default | d | 0v13 | |
MEM_B_A<13> | Default | d | 0v13 | |
MEM_B_A<14> | Default | d | 0v13 | |
MEM_B_A<15> | Default | d | 0v13 | |
MEM_B_A<1> | Default | d | 0v13 | |
MEM_B_A<2> | Default | d | 0v13 | |
MEM_B_A<3> | Default | d | 0v13 | |
MEM_B_A<4> | Default | d | 0v13 | |
MEM_B_A<5> | Default | d | 0v13 | |
MEM_B_A<6> | Default | d | 0v13 | |
MEM_B_A<7> | Default | d | 0v13 | |
MEM_B_A<8> | Default | d | 0v13 | |
MEM_B_A<9> | Default | d | 0v13 | |
MEM_B_BA<0> | Default | d | 0v13 | |
MEM_B_BA<1> | Default | d | 0v13 | |
MEM_B_BA<2> | Default | d | 0v13 | |
MEM_B_CAS_L | Default | d | 0v13 | |
MEM_B_CKE<0> | Default | d | 0.131 | |
MEM_B_CKE<1> | Default | d | 0v13 | |
MEM_B_CLK1_TERM_R | Default | d | 0.255 | |
MEM_B_CLK_N<0> | Default | d | 0.246 | |
MEM_B_CLK_N<1> | Default | d | 0v25 | |
MEM_B_CLK_P<0> | Default | d | 0.246 | |
MEM_B_CLK_P<1> | Default | d | 0v25 | |
MEM_B_CS_L<1> | Default | d | 0v13 | |
MEM_B_DQ<0> | Default | d | 0v27 | |
MEM_B_DQ<10> | Default | d | 0v27 | |
MEM_B_DQ<11> | Default | d | 0v27 | |
MEM_B_DQ<12> | Default | d | 0v27 | |
MEM_B_DQ<13> | Default | d | 0v27 | |
MEM_B_DQ<14> | Default | d | 0v27 | |
MEM_B_DQ<15> | Default | d | 0v27 | |
MEM_B_DQ<1> | Default | d | 0v27 | |
MEM_B_DQ<2> | Default | d | 0v27 | |
MEM_B_DQ<3> | Default | d | 0v27 | |
MEM_B_DQ<4> | Default | d | 0v27 | |
MEM_B_DQ<5> | Default | d | 0v27 | |
MEM_B_DQ<60> | Default | d | 0.269 | |
MEM_B_DQ<6> | Default | d | 0v27 | |
MEM_B_DQ<7> | Default | d | 0v27 | |
MEM_B_DQ<8> | Default | d | 0v27 | |
MEM_B_DQ<9> | Default | d | 0v27 | |
MEM_B_DQS_N<0> | Default | d | 0v27 | |
MEM_B_DQS_N<1> | Default | d | 0v27 | |
MEM_B_DQS_P<0> | Default | d | 0v27 | |
MEM_B_DQS_P<1> | Default | d | 0v27 | |
MEM_B_ODT<1> | Default | d | 0v13 | |
MEM_B_RAS_L | Default | d | 0v13 | |
MEM_B_WE_L | Default | d | 0v13 | |
MEM_B_ZQ<8> | Default | d | 0v25 | |
MEM_B_ZQ<9> | Default | d | 0v25 | |
MEM_CAM_A<14> | Default | d | 0.468 | |
MEM_CAM_CKE | Default | d | 0.473 | |
MEM_CAM_CKE_R | Default | d | OL | |
MEM_CAM_ODT | Default | d | 0.707 | |
MEM_CAM_RESET_L | Default | d | 0.475 | |
MEM_CAM_WE_L | Default | d | 0.470 | |
MEM_RESET_L | Default | d | 0v41 | |
MEM_VREFCA_A_RC | Default | d | 0.026 | |
MEM_VREFCA_B_RC | Default | d | 0.025 | |
MEM_VREFDQ_A_RC | Default | d | 0.026 | |
MIPI_CLK_CONN_N | Default | d | 0v41 | |
MIPI_CLK_CONN_P | Default | d | 0v41 | |
MIPI_DATA_CONN_N | Default | d | 0v41 | |
MIPI_DATA_CONN_P | Default | d | 0v41 | |
MLB_RAMCFG0 | Default | d | 0.526 | |
MLB_RAMCFG2 | Default | d | 0.527 | |
MLB_RAMCFG3 | Default | d | 0.701 | |
NC | Default | d | OL | |
P1V05S0_AGND | Default | d | 0.000 | |
P1V05S0_BOOT_RC | Default | d | 0.587 | |
P1V05S0_CS_N | Default | d | 0.127 | |
P1V05S0_CS_P | Default | d | 0.127 | |
P1V05S0_DRVH | Default | d | 0v53 | |
P1V05S0_DRVL | Default | d | 0v45 | |
P1V05S0_EN | Default | d | 0.545 | |
P1V05S0_FB | Default | d | 0.521 | |
P1V05S0_FSEL | Default | d | 0.544 | |
P1V05S0_LL | Default | d | 0.127 | |
P1V05S0_OCSET | Default | d | 0.523 | |
P1V05S0_PGOOD | Default | d | 0.506 | |
P1V05S0_RTN | Default | d | 0.523 | |
P1V05S0_SENSE_N | Default | d | 0.001 | |
P1V05S0_SENSE_P | Default | d | 0.124 | |
P1V05S0_SREF | Default | d | 0.543 | |
P1V05S0_VBST | Default | d | 0.586 | |
P1V05S0_VO | Default | d | 0.522 | |
P1V05_EN_D | Default | d | 0.858 | |
P1V05_VID_VMON | Default | d | OL | |
P1V2_CAM_SRVLXC_PHASE | Default | d | 0.321 | |
P1V35CPU_SLEW_CTL | Default | d | 0.727 | |
P1V35_CAM_SRVLXD_PHASE | Default | d | 0.258 | |
P1V5S0_FB | Default | d | 0.780 | |
P1V5S0_PGOOD | Default | d | 0.565 | |
P1V5S0_SW | Default | d | 0v30 | |
P1V5_DIV_VMON | Default | d | OL | |
P3V3S0_P1V5_S0_EN | Default | d | 0.650 | |
P3V3S3_EN | Default | d | 0.502 | |
P3V3S3_EN_L | Default | d | 0.510 | |
P3V3S3_S4 | Default | d | OL | |
P3V3S3_SS | Default | d | OL | |
P3V3S4_EN_L | Default | d | 0.626 | |
P3V3S5_COMP2 | Default | d | 0v72 | |
P3V3S5_COMP2_R | Default | d | OL | |
P3V3S5_CSN2 | Default | d | 0v14 | |
P3V3S5_CSP2 | Default | d | 0v76 | |
P3V3S5_CSP2_R | Default | d | 0.147 | |
P3V3S5_DRVH | Default | d | 0v68 | |
P3V3S5_DRVL | Default | d | 0v53 | |
P3V3S5_EN | Default | d | 0v53 | |
P3V3S5_LL | Default | d | 0v14 | |
P3V3S5_RF | Default | d | 0v58 | |
P3V3S5_SNUBR | Default | d | OL | |
P3V3S5_TG | Default | d | 0.694 | |
P3V3S5_VBST | Default | d | 0v55 | |
P3V3S5_VFB2 | Default | d | 0v57 | |
P3V3S5_VFB2_R | Default | d | 0.147 | |
P3V3SSD_VMON | Default | d | 0.471 | |
P3V3SUS_EN_L | Default | d | 0.621 | |
P3V3SUS_SS | Default | d | OL | |
P3V3WLAN_VMON | Default | d | 0.469 | |
P3V3_SSD_EN_L | Default | d | 0.506 | |
P3V3_SSD_SS | Default | d | OL | |
P3V42G3H_BOOST | Default | d | 0.629 | |
P3V42G3H_FB | Default | d | 0.722 | |
P3V42G3H_SHDN_L | Default | d | 0.609 | |
P3V42G3H_SW | Default | d | 0.321 | |
P5V0S0_EN_L | Default | d | 0.635 | |
P5V0S0_SS | Default | d | OL | |
P5V1_BIAS | Default | d | 0v32 | |
P5V1_BOOST | Default | d | 0v62 | |
P5V1_FB | Default | d | 0v71 | |
P5V1_SW | Default | d | 0v32 | |
P5V1_VIN | Default | d | 0v59 | |
P5VP3V3_SKIPSEL | Default | d | 0v48 | |
P5VP3V3_VREF2 | Default | d | 0v48 | |
P5VP3V3_VREG3 | Default | d | 0v55 | |
P5VS0_EN | Default | d | 0.631 | |
P5VS3_EN | Default | d | 0.499 | |
P5VS3_EN_L | Default | d | 0.617 | |
P5VS3_SS | Default | d | OL | |
P5VS4_COMP1 | Default | d | 0v72 | |
P5VS4_COMP1_R | Default | d | OL | |
P5VS4_CSN1 | Default | d | 0v43 | |
P5VS4_CSP1 | Default | d | 1v27 | |
P5VS4_CSP1_R | Default | d | 0.440 | |
P5VS4_DRVH | Default | d | 0v95 | |
P5VS4_DRVL | Default | d | 0v53 | |
P5VS4_EN | Default | d | 0v57 | |
P5VS4_EN_D | Default | d | 0.677 | |
P5VS4_LL | Default | d | 0v43 | |
P5VS4_PGOOD | Default | d | 0v57 | |
P5VS4_TG | Default | d | 0.985 | |
P5VS4_VBST | Default | d | 0v62 | |
P5VS4_VFB1 | Default | d | 0v57 | |
P5VS4_VFB1_R | Default | d | 0.440 | |
P5VS4_VSW | Default | d | 0v43 | |
P5V_DIV_VMON | Default | d | OL | |
PBUSVSENS_EN_L | Default | d | 0.488 | |
PBUSVSENS_EN_L_DIV | Default | d | OL | |
PBUS_S0_VSENSE | Default | d | OL | |
PCA9557D_RESET_L | Default | d | 0.585 | |
PCH_CLK100M_SATA_N | Default | d | 0.796 | |
PCH_CLK100M_SATA_P | Default | d | 0.796 | |
PCH_CLK14P3M_REFCLK | Default | d | 0.423 | |
PCH_CLK33M_PCIIN | Default | d | 0.632 | |
PCH_CLK33M_PCIOUT | Default | d | 0.609 | |
PCH_CLK96M_DOT_N | Default | d | 0.793 | |
PCH_CLK96M_DOT_P | Default | d | 0.794 | |
PCH_CLKIN_GNDN | Default | d | 0.793 | |
PCH_CLKIN_GNDP | Default | d | 0.793 | |
PCH_CLKRQ5_L_GPIO44 | Default | d | 0.608 | |
PCH_CLKRQ7_L_GPIO46 | Default | d | 0.607 | |
PCH_DMI_RCOMP | Default | d | 0.780 | |
PCH_DSWVRMEN | Default | d | 0.799 | |
PCH_FDI_RCOMP | Default | d | 0.781 | |
PCH_INTVRMEN_L | Default | d | 0.800 | |
PCH_PCIE_RCOMP | Default | d | 0.785 | |
PCH_PECI | Default | d | 0.578 | |
PCH_PEGCLKRQB_L_GPIO56 | Default | d | 0.599 | |
PCH_PROCPWRGD | Default | d | 0.362 | |
PCH_RI_L | Default | d | 0.663 | |
PCH_SATALED_L | Default | d | 0.652 | |
PCH_SATA_RCOMP | Default | d | 0.781 | |
PCH_SMBALERT_L | Default | d | 0.672 | |
PCH_SML1ALERT_L | Default | d | 0.667 | |
PCH_SPKR | Default | d | 0.548 | |
PCH_SRTCRST_L | Default | d | 0.797 | |
PCH_STRP_TOPBLK_SWP_L | Default | d | 0.467 | |
PCH_SUSACK_L | Default | d | 0.546 | |
PCH_SUSWARN_L | Default | d | 0.546 | |
PCH_TD_IREF | Default | d | 0.792 | |
PCH_USB_RBIAS | Default | d | 0.023 | |
PCIE_AP_D2R_PI_N | Default | d | 0v38 | |
PCIE_AP_D2R_PI_P | Default | d | 0v38 | |
PCIE_AP_R2D_N | Default | d | OL | |
PCIE_AP_R2D_P | Default | d | OL | |
PCIE_CAMERA_D2R_N | Default | d | 0.380 | |
PCIE_CAMERA_D2R_P | Default | d | 0.380 | |
PCIE_CLK100M_AP_CONN_N | Default | d | 0v30 | |
PCIE_CLK100M_AP_CONN_P | Default | d | 0v30 | |
PCIE_CLK100M_AP_N | Default | d | 0.289 | |
PCIE_CLK100M_AP_P | Default | d | 0.290 | |
PCIE_CLK100M_CAMERA_N | Default | d | 0.293 | |
PCIE_CLK100M_CAMERA_P | Default | d | 0.293 | |
PCIE_CLK100M_PCH_N | Default | d | 0.793 | |
PCIE_CLK100M_PCH_P | Default | d | 0.794 | |
PCIE_CLK100M_SSD_N | Default | d | 0v29 | |
PCIE_CLK100M_SSD_P | Default | d | 0v29 | |
PCIE_CLK100M_TBT_N | Default | d | 0.298 | |
PCIE_CLK100M_TBT_P | Default | d | 0.300 | |
PCIE_SSD_D2R_N<0> | Default | d | 0v37 | |
PCIE_SSD_D2R_N<1> | Default | d | 0v38 | |
PCIE_SSD_D2R_N<2> | Default | d | 0v38 | |
PCIE_SSD_D2R_N<3> | Default | d | 0v38 | |
PCIE_SSD_D2R_P<0> | Default | d | 0v38 | |
PCIE_SSD_D2R_P<1> | Default | d | 0v38 | |
PCIE_SSD_D2R_P<2> | Default | d | 0v38 | |
PCIE_SSD_D2R_P<3> | Default | d | 0v38 | |
PCIE_SSD_R2D_N<0> | Default | d | OL | |
PCIE_SSD_R2D_N<1> | Default | d | OL | |
PCIE_SSD_R2D_N<2> | Default | d | OL | |
PCIE_SSD_R2D_N<3> | Default | d | OL | |
PCIE_SSD_R2D_P<0> | Default | d | OL | |
PCIE_SSD_R2D_P<1> | Default | d | OL | |
PCIE_SSD_R2D_P<2> | Default | d | OL | |
PCIE_SSD_R2D_P<3> | Default | d | OL | |
PCIE_TBT_D2R_N<2> | Default | d | 0.317 | |
PCIE_TBT_D2R_N<3> | Default | d | 0.313 | |
PCIE_TBT_D2R_P<2> | Default | d | 0.318 | |
PCIE_TBT_D2R_P<3> | Default | d | 0.312 | |
PCIE_TBT_R2D_C_N<0> | Default | d | 0.308 | |
PCIE_TBT_R2D_C_N<1> | Default | d | 0.308 | |
PCIE_TBT_R2D_C_P<1> | Default | d | 0.309 | |
PCIE_WAKE_L | Default | d | 0v54 | |
PCI_INTA_L | Default | d | 0.715 | |
PCI_INTB_L | Default | d | 0.712 | |
PCI_INTC_L | Default | d | 0.723 | |
PDCINVSENS_EN_L_DIV | Default | d | OL | |
PD_CS4208_GPIO1 | Default | d | 0.742 | |
PICKB_L | Default | d | 0v67 | |
PLT_RESET_L | Default | d | 0.585 | |
PLT_RST_BUF_L | Default | d | 0.425 | |
PM_1V5_PGD_L | Default | d | OL | |
PM_1V5_PGD_L_R | Default | d | OL | |
PM_BATLOW_L | Default | d | 0.523 | |
PM_CLK32K_SUSCLK_R | Default | d | 0.713 | |
PM_CLKRUN_L | Default | d | 0v53 | |
PM_DSW_PWRGD | Default | d | 0.745 | |
PM_MEM_PWRGD | Default | d | 0.450 | |
PM_MEM_PWRGD_L | Default | d | OL | |
PM_P1V5_PGD_DIV | Default | d | OL | |
PM_PCH_PWROK | Default | d | 0.676 | |
PM_PCH_SYS_PWROK | Default | d | 0.740 | |
PM_PWRBTN_L | Default | d | 0.611 | |
PM_RSMRST_L | Default | d | 0.633 | |
PM_S0_PGOOD | Default | d | 0.676 | |
PM_SLP_S3_BUF_L | Default | d | 0v62 | |
PM_SLP_S3_L | Default | d | 0.516 | |
PM_SLP_S3_R_L | Default | d | 0.449 | |
PM_SLP_S4_L | Default | d | 0.500 | |
PM_SLP_S5_L | Default | d | 0.628 | |
PM_SLP_SUS_L | Default | d | 0.682 | |
PM_SYNC | Default | d | 0.376 | |
PM_SYSRST_L | Default | d | 0.637 | |
PM_THRMTRIP_B_L | Default | d | OL | |
PM_THRMTRIP_L | Default | d | 0.268 | |
PM_THRMTRIP_L_R | Default | d | 0.570 | |
PM_WLAN_EN | Default | d | 0.438 | |
PP0V675_CAM_VREF | Default | d | 0.673 | |
PP0V675_MEM_CAM_VREFCA | Default | d | 0.520 | |
PP0V675_MEM_CAM_VREFDQ | Default | d | 0.673 | |
PP0V75_S3_MEM_VREFCA_A | Default | d | 0.376 | |
PP0V75_S3_MEM_VREFCA_B | Default | d | 0v38 | |
PP0V75_S3_MEM_VREFDQ_A | Default | d | 0.376 | |
PP0V75_S3_MEM_VREFDQ_B | Default | d | 0v38 | |
PP15V_TBT | Default | d | 0v56 | |
PP1V05_S0 | Default | d | 0.127 | |
PP1V05_S0_PCH_VCC_CLK_F | Default | d | 0.125 | |
PP1V05_S0_PCH_VCC_CLK_R | Default | d | 0.124 | |
PP1V05_S0_REG_R | Default | d | 0.127 | |
PP1V05_SUS | Default | d | 0.350 | |
PP1V05_TBT | Default | d | 0.169 | |
PP1V05_TBTCIO | Default | d | 0.115 | |
PP1V05_TBTRDV | Default | d | 0.129 | |
PP1V2_CAM | Default | d | 0.322 | |
PP1V2_CAM_PCIE_PVDD_FLT | Default | d | 0.353 | |
PP1V2_CAM_PCIE_VDD_FLT | Default | d | 0.353 | |
PP1V2_CAM_XTALPCIEVDD | Default | d | 0.353 | |
PP1V2_S5_SMC_VDDC | Default | d | 0.524 | |
PP1V35_CAM | Default | d | 0.255 | |
PP1V35_DDR_CLK | Default | d | 0.255 | |
PP1V35_S3 | Default | d | 0.125 | |
PP1V35_S3RS0_CPUDDR | Default | d | 0.136 | |
PP1V35_S3RS0_FET | Default | d | 0.137 | |
PP1V35_S3_MEM | Default | d | 0.125 | |
PP1V5R1V35_S0_RIO | Default | d | 0.345 | |
PP1V5_S0 | Default | d | 0v30 | |
PP1V5_S0_AUDIO_DIG | Default | d | 0.346 | |
PP1V8_CAM | Default | d | 0.511 | |
PP20V_DCIN_CONN_R | Default | d | OL | |
PP20V_DCIN_FUSE | Default | d | OL | |
PP3V3RHV_S4_TBTAPWR | Default | d | 0.559 | |
PP3V3RHV_S4_TBTAPWR_F | Default | d | 0.559 | |
PP3V3RHV_S4_TBTBPWR | Default | d | 0.561 | |
PP3V3RHV_S4_TBTBPWR_F | Default | d | 0.560 | |
PP3V3_S0 | Default | d | 0v34 | |
PP3V3_S0 | Default | v | 3.30 | |
PP3V3_S0SW_SSD | Default | d | 0.657 | |
PP3V3_S0SW_SSD_FLT | Default | d | 0v64 | |
PP3V3_S0SW_SSD_R | Default | d | 0.657 | |
PP3V3_S0_AUDIO_ANALOG | Default | d | 0.358 | |
PP3V3_S0_CPUTHMSNS_R | Default | d | 0.405 | |
PP3V3_S0_CPUTHMSNS_R | Default | v | 3.30 | |
PP3V3_S0_FINTHMSNS_R | Default | d | 0.403 | |
PP3V3_S0_VMON_P2 | Default | d | OL | |
PP3V3_S0_VMON_P7 | Default | d | OL | |
PP3V3_S3 | Default | d | 0v45 | |
PP3V3_S3RS0_CAMERA | Default | d | 0.357 | |
PP3V3_S3RS0_CAMERA_R | Default | d | 0.357 | |
PP3V3_S3RS4_BT_F | Default | d | 0v41 | |
PP3V3_S3_FAN_CTL | Default | v | 3.30 | |
PP3V3_S3_PSOC | Default | d | 0v40 | |
PP3V3_S3_VREFMRGN | Default | d | 0.509 | |
PP3V3_S4 | Default | d | 0v40 | |
PP3V3_S4_TBT | Default | d | 0.413 | |
PP3V3_S4_TBTAPWR | Default | d | 0.375 | |
PP3V3_S4_TBTBPWR | Default | d | 0.372 | |
PP3V3_S4_TBT_F | Default | d | 0.412 | |
PP3V3_S5 | Default | d | 0v14 | |
PP3V3_S5_AVREF_SMC | Default | d | 0.609 | |
PP3V3_S5_DBGLED | Default | d | OL | |
PP3V3_S5_SMC_VDDA | Default | d | 0.320 | |
PP3V3_SUS | Default | d | 0v33 | |
PP3V3_TBTLC | Default | d | 0.419 | |
PP3V3_TBTRDV | Default | d | 0.549 | |
PP3V3_TPAD_CONN | Default | d | 0v39 | |
PP3V3_WLAN | Default | d | 0.544 | |
PP3V3_WLAN_F | Default | d | 0.544 | |
PP3V3_WLAN_R | Default | d | 0.544 | |
PP3V42_G3H | Default | d | 0v32 | |
PP3V42_G3H_SMC_SPVSR | Default | d | 0.318 | |
PP4V5_AUDIO_ANALOG | Default | d | 0.421 | |
PP5V1_CHGR_VDD | Default | d | 0v32 | |
PP5V1_CHGR_VDDP | Default | d | 0v32 | |
PP5VR3V3_SW_LCD | Default | d | 0.650 | |
PP5VR3V3_SW_LCD_ISNS | Default | d | 0.617 | |
PP5VR3V3_SW_LCD_UF | Default | d | 0.650 | |
PP5V_S0 | Default | d | 0v41 | |
PP5V_S0 | Default | v | 5.00 | |
PP5V_S0_AUDIO_AMP_L | Default | d | 0v41 | |
PP5V_S0_AUDIO_AMP_R | Default | d | 0.410 | |
PP5V_S0_BKLT_VDDA | Default | d | 0v41 | |
PP5V_S0_BKLT_VDDD | Default | d | 0v41 | |
PP5V_S0_CPUVR_VDD | Default | d | 0.407 | |
PP5V_S0_KBDLED_R | Default | d | 0v41 | |
PP5V_S0_P1V05S0_VCC | Default | d | 0.410 | |
PP5V_S3 | Default | d | 0.493 | |
PP5V_S3RS0_ALSCAM_F | Default | d | 0v41 | |
PP5V_S3_LTUSB_A_F | Default | d | 0.525 | |
PP5V_S3_LTUSB_A_ILIM | Default | d | 0.524 | |
PP5V_S4 | Default | d | 0v43 | |
PP5V_S4_AUDIO_XW | Default | d | 0.430 | |
PP5V_S5 | Default | d | 0v46 | |
PP5V_S5_CUMULUS | Default | d | 0v46 | |
PPBUS_G3H | Default | d | 0v45 | |
PPBUS_G3H_R | Default | d | 0.471 | |
PPBUS_S0_LCDBKLT_FUSED | Default | d | 0v46 | |
PPBUS_S0_LCDBKLT_PWR_SW | Default | d | 0v88 | |
PPBUS_SW_BKL | Default | d | 0v88 | |
PPBUS_SW_LCDBKLT_PWR | Default | d | 0v46 | |
PPDCIN_G3H | Default | d | 0v68 | |
PPDCIN_G3H_CHGR | Default | d | 0v63 | |
PPDCIN_G3H_INRUSH | Default | d | 0v63 | |
PPDCIN_G3H_ISOL | Default | d | OL | |
PPVBAT_G3H_CHGR_R | Default | d | 0.450 | |
PPVBAT_G3H_CHGR_REG | Default | d | 0v45 | |
PPVBAT_G3H_CONN | Default | d | OL | |
PPVCCIO_S0_CPU | Default | d | 0v02 | |
PPVCC_S0_CPU | Default | d | 0.013 | |
PPVCC_S0_CPU_PH1 | Default | d | 0.013 | |
PPVCC_S0_CPU_PH1 | Default | r | 18.400R | |
PPVCC_S0_CPU_PH2 | Default | d | 0.013 | |
PPVCC_S0_CPU_PH2 | Default | r | 18.400R | |
PPVCC_S0_CPU_PH3 | Default | d | 0.013 | |
PPVCC_S0_CPU_PH3 | Default | r | 18.400R | |
PPVCOMP_S0_CPU | Default | d | 0.038 | |
PPVIN_G3H_P3V42G3H | Default | d | 0.609 | |
PPVIN_S0_CPUVR_VIN | Default | d | 0.466 | |
PPVIN_S5_HS_COMPUTING_ISNS | Default | d | 0.450 | |
PPVIN_S5_HS_OTHER3V3_ISNS | Default | d | 0v45 | |
PPVIN_S5_HS_OTHER5V_ISNS | Default | d | 0v45 | |
PPVIN_SW_TBTBST | Default | d | 0v51 | |
PPVOUT_BKLT_FB2 | Default | d | 0v61 | |
PPVOUT_S0_KBDBKLT | Default | d | 0v61 | |
PPVOUT_S0_LCDBKLT | Default | d | 1v20 | |
PPVOUT_S0_PCH_DCPRTC | Default | d | 0.714 | |
PPVOUT_S0_PCH_DCPSST | Default | d | 0.484 | |
PPVOUT_S5_PCH_DCPSUSBYP_R | Default | d | 0.393 | |
PPVRTC_G3H | Default | d | 0.446 | |
PPVTTDDR_S3 | Default | d | 0.489 | |
PPVTT_S0_DDR | Default | d | 0.096 | |
PSOC_F_CS_L | Default | d | 0v70 | |
PSOC_MISO | Default | d | 0v70 | |
PSOC_MOSI | Default | d | 0v70 | |
PSOC_SCLK | Default | d | 0v70 | |
RIO_SDCONN_STATE_CHANGE_L | Default | d | 0v70 | |
RSUBIN_N | Default | d | 0.593 | |
RSUBIN_P | Default | d | 0.593 | |
RSUB_GAIN | Default | d | 0.589 | |
RTC_RESET_L | Default | d | 0.796 | |
S0PGD_BJT_GND_R | Default | d | 0.101 | |
S0PGD_C | Default | d | OL | |
S4_PWR_EN | Default | d | 0.454 | |
S5_PWRGD | Default | d | 0v57 | |
SDCONN_STATE_CHANGE_L | Default | d | 0.505 | |
SD_PWR_EN | Default | d | 0v52 | |
SD_SEL_PCIE_L_USB_H | Default | d | 0.704 | |
SMBUS_PCH_CLK | Default | d | 0v49 | |
SMBUS_PCH_DATA | Default | d | 0v49 | |
SMBUS_SMC_0_S0_SCL | Default | d | 0v71 | |
SMBUS_SMC_0_S0_SDA | Default | d | 0v71 | |
SMBUS_SMC_1_S0_SCL | Default | v | 3.30 | |
SMBUS_SMC_1_S0_SDA | Default | v | 3.30 | |
SMBUS_SMC_2_S3_SCL | Default | d | 0v72 | |
SMBUS_SMC_2_S3_SDA | Default | d | 0v72 | |
SMBUS_SMC_5_G3_SCL | Default | d | 0v52 | |
SMBUS_SMC_5_G3_SDA | Default | d | 0v52 | |
SMC_ADAPTER_EN | Default | d | 0.613 | |
SMC_BC_ACOK | Default | d | 0v53 | |
SMC_BC_ACOK_VCC | Default | d | 0.597 | |
SMC_BIL_BUTTON_L | Default | d | 0.750 | |
SMC_CHGR_BMON_ISENSE | Default | d | 0.748 | |
SMC_CLK32K | Default | d | 0.718 | |
SMC_CPUPKG_ISENSE | Default | d | 0.592 | |
SMC_CPUPKG_VSENSE | Default | d | 0.741 | |
SMC_CPU_HI_ISENSE | Default | d | 0.748 | |
SMC_DCIN_ISENSE | Default | d | 0.747 | |
SMC_DCIN_VSENSE | Default | d | 0.739 | |
SMC_DEBUGPRT_EN_L | Default | d | 0.587 | |
SMC_DEBUGPRT_RX_L | Default | d | 0.690 | |
SMC_DEBUGPRT_TX_L | Default | d | 0.690 | |
SMC_DELAYED_PWRGD | Default | d | 0.709 | |
SMC_DP_HPD_L | Default | d | 0.752 | |
SMC_EXTAL | Default | d | 0.780 | |
SMC_FAN_0_CTL | Default | v | 0.85 | |
SMC_FAN_1_CTL | Default | v | 2.31 | |
SMC_FAN_1_TACH | Default | d | 0.751 | |
SMC_LCDBKLT_ISENSE | Default | d | 0.747 | |
SMC_LCDPANEL_ISENSE | Default | d | 0.749 | |
SMC_LID | Default | d | 0.507 | |
SMC_LID_R | Default | d | 0.501 | |
SMC_LRESET_L | Default | d | 0.611 | |
SMC_MANUAL_RST_L | Default | d | 0.678 | |
SMC_ONOFF_L | Default | d | 0.670 | |
SMC_OOB1_D2R_CONN_L | Default | d | 0v70 | |
SMC_OOB1_D2R_L | Default | d | 0.690 | |
SMC_OOB1_R2D_CONN_L | Default | d | 0v68 | |
SMC_OOB1_R2D_L | Default | d | 0.689 | |
SMC_OTHER3V3_HI_ISENSE | Default | d | 0.748 | |
SMC_P1V35MEM_ISENSE | Default | d | 0.749 | |
SMC_PBUS_VSENSE | Default | d | 0.745 | |
SMC_PECI_L | Default | d | 0.744 | |
SMC_PECI_L_R | Default | d | 0.744 | |
SMC_PME_S4_DARK_L | Default | d | 0.637 | |
SMC_PME_S4_WAKE_L | Default | d | 0.493 | |
SMC_PME_SDCONN | Default | d | 0.628 | |
SMC_PM_G2_EN | Default | d | 0v53 | |
SMC_PROCHOT | Default | d | 0.751 | |
SMC_PWRFAIL_WARN_L | Default | d | 0v68 | |
SMC_RESET_L | Default | d | 0v51 | |
SMC_ROMBOOT | Default | d | 1v30 | |
SMC_RUNTIME_SCI_L | Default | d | 0.665 | |
SMC_RX_L | Default | d | 0v74 | |
SMC_S4_WAKESRC_EN | Default | d | 0.703 | |
SMC_S5_PWRGD_VIN | Default | d | 0.754 | |
SMC_SSD_ISENSE | Default | d | 0.744 | |
SMC_SYS_KBDLED | Default | d | 0.563 | |
SMC_TBT_ISENSE | Default | d | 0.740 | |
SMC_TCK | Default | d | 0v74 | |
SMC_TDI | Default | d | 0v74 | |
SMC_TDO | Default | d | 0v74 | |
SMC_THRMTRIP | Default | d | 0.751 | |
SMC_TMS | Default | d | 0v74 | |
SMC_TOPBLK_SWP_L | Default | d | 0.736 | |
SMC_TX_L | Default | d | 0v74 | |
SMC_VCCIO_CPU_DIV2 | Default | d | 0.740 | |
SMC_WAKE_L | Default | d | 0.751 | |
SMC_WAKE_SCI_L | Default | d | 0.521 | |
SMC_X29_ISENSE | Default | d | 0.751 | |
SMC_XTAL | Default | d | 0.767 | |
SMC_XTAL_R | Default | d | OL | |
SML_PCH_1_CLK | Default | d | 0.560 | |
SML_PCH_1_DATA | Default | d | 0.560 | |
SMS_INT_L | Default | d | 0.753 | |
SPDIF_OUT_JACK | Default | d | 0.678 | |
SPIROM_HOLD_L | Default | d | 0v51 | |
SPIROM_USE_MLB | Default | d | 0v48 | |
SPIROM_WP_L | Default | d | 0v63 | |
SPI_ALT_CLK | Default | d | 0v60 | |
SPI_ALT_CS_L | Default | d | 0v54 | |
SPI_ALT_MISO | Default | d | 0v48 | |
SPI_ALT_MOSI | Default | d | 0v51 | |
SPI_CLK | Default | d | 0.609 | |
SPI_CS0_L | Default | d | 0.544 | |
SPI_DESCRIPTOR_OVERRIDE | Default | d | 1.340 | |
SPI_DESCRIPTOR_OVERRIDE_L | Default | d | 0.754 | |
SPI_DESCRIPTOR_OVERRIDE_LS5V | Default | d | 0.617 | |
SPI_IO<3> | Default | d | 0.548 | |
SPI_MISO | Default | d | 0.495 | |
SPI_MLB_CLK | Default | d | 0v61 | |
SPI_MLB_CS_L | Default | d | 0v54 | |
SPI_MLB_MISO | Default | d | 0v49 | |
SPI_MLB_MOSI | Default | d | 0v51 | |
SPI_MOSI | Default | d | 0.541 | |
SPI_SMC_CLK | Default | d | 0.609 | |
SPI_SMC_CS_L | Default | d | 0.538 | |
SPI_SMC_MISO | Default | d | 0.508 | |
SPI_SMC_MOSI | Default | d | 0.548 | |
SPKRAMP_LIN_N | Default | d | 0.620 | |
SPKRAMP_LIN_P | Default | d | 0.620 | |
SPKRAMP_RIN_N | Default | d | 0.620 | |
SPKRAMP_RIN_P | Default | d | 0.620 | |
SPKRCONN_L_ID | Default | d | 0v72 | |
SPKRCONN_L_OUT_N | Default | d | 0v53 | |
SPKRCONN_L_OUT_P | Default | d | 0v52 | |
SPKRCONN_R_ID | Default | d | 0v72 | |
SPKRCONN_R_OUT_N | Default | d | 0v53 | |
SPKRCONN_R_OUT_P | Default | d | 0v52 | |
SPKRCONN_SL_OUT_N | Default | d | 0v61 | |
SPKRCONN_SL_OUT_P | Default | d | 0v61 | |
SPKRCONN_SR_OUT_N | Default | d | 0v61 | |
SPKRCONN_SR_OUT_P | Default | d | 0v61 | |
SPKR_L_GAIN | Default | d | 0.622 | |
SPKR_R_GAIN | Default | d | 0.623 | |
SPKR_SHUTDOWN | Default | d | 0.528 | |
SSD_CLKREQ_CONN_L | Default | d | 0v46 | |
SSD_CLKREQ_L | Default | d | 0.440 | |
SSD_DEVSLP | Default | d | 2v14 | |
SSD_PCIE_SEL_L | Default | d | 0v49 | |
SSD_PWR_EN | Default | d | 0.455 | |
SSD_PWR_FET_EN | Default | d | 0v44 | |
SSD_RESET_CONN_L | Default | d | 0v46 | |
SSD_RESET_L | Default | d | 0.425 | |
SUS_PGOOD_CT | Default | d | 0.640 | |
SYSCLK_CLK25M_CAMERA | Default | d | 0.452 | |
SYSCLK_CLK25M_SB | Default | d | 0.430 | |
SYSCLK_CLK25M_SB_R | Default | d | 0.561 | |
SYSCLK_CLK25M_TBT | Default | d | 0.443 | |
SYSCLK_CLK25M_TBT_R | Default | d | 0.671 | |
SYSCLK_CLK25M_X1 | Default | d | 0.445 | |
SYSCLK_CLK25M_X2 | Default | d | 0.448 | |
SYSCLK_CLK25M_X2_R | Default | d | 0.448 | |
SYSCLK_CLK32K_RTC | Default | d | 0.455 | |
SYS_DETECT_L | Default | d | 2v14 | |
SYS_ONEWIRE | Default | d | 0.685 | |
SYS_PWROK_R | Default | d | 0.687 | |
TBTACONN_1_C | Default | d | OL | |
TBTACONN_20_RC | Default | d | 0.573 | |
TBTACONN_7_C | Default | d | OL | |
TBTAPWRSW_ISET_S0 | Default | d | 0.479 | |
TBTAPWRSW_ISET_S0_R | Default | d | OL | |
TBTAPWRSW_ISET_S3 | Default | d | 0.478 | |
TBTAPWRSW_ISET_V3P3 | Default | d | 0.479 | |
TBTBCONN_1_C | Default | d | OL | |
TBTBCONN_20_RC | Default | d | 0.572 | |
TBTBCONN_7_C | Default | d | OL | |
TBTBPWRSW_ISET_S0 | Default | d | 0.477 | |
TBTBPWRSW_ISET_S3 | Default | d | 0.477 | |
TBTBPWRSW_ISET_V3P3 | Default | d | 0.477 | |
TBTBST_BOOST | Default | d | 0v51 | |
TBTBST_EN_UVLO | Default | d | 0v61 | |
TBTBST_FBX | Default | d | 2v27 | |
TBTBST_INTVCC | Default | d | 0v57 | |
TBTBST_PWREN_DIV_L | Default | d | OL | |
TBTBST_PWREN_L | Default | d | 0v49 | |
TBTBST_RT | Default | d | 0v67 | |
TBTBST_SHDN_DIV | Default | d | 0.626 | |
TBTBST_SNS1 | Default | d | 0v00 | |
TBTBST_SNS2 | Default | d | 0v00 | |
TBTBST_SS | Default | d | 0v67 | |
TBTBST_VC | Default | d | 0v68 | |
TBTBST_VC_RC | Default | d | OL | |
TBTBST_VSNS | Default | d | 0.569 | |
TBTDP_AUXIO_EN | Default | d | 0.788 | |
TBTPOCRST_CT | Default | d | 0.736 | |
TBTPOCRST_SENSE | Default | d | 1.414 | |
TBT_A_CIO_SEL | Default | d | 0.802 | |
TBT_A_CONFIG1_BUF | Default | d | 0.776 | |
TBT_A_CONFIG1_RC | Default | d | 0.843 | |
TBT_A_CONFIG2_RC | Default | d | 0.814 | |
TBT_A_D2R_N<1> | Default | d | 0.390 | |
TBT_A_D2R_P<1> | Default | d | 0.391 | |
TBT_A_DP_PWRDN | Default | d | 0.797 | |
TBT_A_HPD | Default | d | 0.841 | |
TBT_A_HV_EN | Default | d | 0.481 | |
TBT_A_LSTX | Default | d | 0.762 | |
TBT_A_R2D_C_P<1> | Default | d | 0.227 | |
TBT_BATLOW_L | Default | d | 0.801 | |
TBT_B_CONFIG1_RC | Default | d | 0.843 | |
TBT_B_CONFIG2_RC | Default | d | 0.807 | |
TBT_B_DP_PWRDN | Default | d | 0.798 | |
TBT_B_HPD | Default | d | 0.842 | |
TBT_B_HV_EN | Default | d | 0v48 | |
TBT_CIO_PLUG_EVENT_L | Default | d | 0.500 | |
TBT_CLKREQ_L | Default | d | 0.491 | |
TBT_DDC_XBAR_EN | Default | d | 0v49 | |
TBT_DDC_XBAR_EN_L | Default | d | 0v80 | |
TBT_EN_CIO_PWR_L | Default | d | 0.567 | |
TBT_MONOBSN | Default | d | 0.187 | |
TBT_MONOBSP | Default | d | 0.187 | |
TBT_PCIE_RESET_L | Default | d | 0.431 | |
TBT_POC_RESET_L | Default | d | 0.660 | |
TBT_PWR_EN | Default | d | 0.673 | |
TBT_PWR_EN_PCH | Default | d | 0.647 | |
TBT_PWR_ON_POC_RST_L | Default | d | 0.737 | |
TBT_PWR_REQ_L | Default | d | 0.712 | |
TBT_RBIAS | Default | d | 0.795 | |
TPAD_VBUS_EN | Default | d | 0v69 | |
TP_CAM_JTAG_TCK | Default | d | 0.778 | |
TP_CAM_JTAG_TDI | Default | d | 0.779 | |
TP_CAM_JTAG_TDO | Default | d | 0.778 | |
TP_CAM_JTAG_TMS | Default | d | 0.779 | |
TP_CAM_JTAG_TRST_L | Default | d | 0.779 | |
TP_CAM_LV_JTAG_TCK | Default | d | 0.777 | |
TP_CAM_LV_JTAG_TDI | Default | d | 0.777 | |
TP_CAM_LV_JTAG_TDO | Default | d | 0.778 | |
TP_CAM_LV_JTAG_TMS | Default | d | 0.777 | |
TP_CAM_LV_JTAG_TRSTN | Default | d | 0.778 | |
TP_CAM_TEST_MODE1 | Default | d | 0.777 | |
TP_CAM_TEST_MODE2 | Default | d | 0.778 | |
TP_CPU_FC_VCCST_PWRGD | Default | d | OL | |
TP_CPU_IVR_ERROR | Default | d | 0.272 | |
TP_CPU_RSVD_TP78 | Default | d | 0.270 | |
TP_EDP_DISP_UTIL | Default | d | 0.378 | |
TP_ISSP_SCLK_P1_1 | Default | d | 0v70 | |
TP_ISSP_SDATA_P1_0 | Default | d | 0v70 | |
TP_P7_7 | Default | d | 0v70 | |
TP_PEG_D2RN<10> | Default | d | 0.311 | |
TP_PEG_D2RN<11> | Default | d | 0.311 | |
TP_PEG_D2RN<4> | Default | d | 0.311 | |
TP_PEG_D2RN<5> | Default | d | 0.312 | |
TP_PEG_D2RN<6> | Default | d | 0.311 | |
TP_PEG_D2RN<7> | Default | d | 0.310 | |
TP_PEG_D2RN<8> | Default | d | 0.311 | |
TP_PEG_D2RN<9> | Default | d | 0.310 | |
TP_PEG_D2RP<10> | Default | d | 0.312 | |
TP_PEG_D2RP<11> | Default | d | 0.309 | |
TP_PEG_D2RP<4> | Default | d | 0.312 | |
TP_PEG_D2RP<5> | Default | d | 0.312 | |
TP_PEG_D2RP<6> | Default | d | 0.311 | |
TP_PEG_D2RP<7> | Default | d | 0.312 | |
TP_PEG_D2RP<8> | Default | d | 0.311 | |
TP_PEG_D2RP<9> | Default | d | 0.312 | |
TP_PSOC_P1_3 | Default | d | 0v70 | |
TP_PSOC_SCL | Default | d | 0v70 | |
TP_PSOC_SDA | Default | d | 0v70 | |
TP_SMC_MD1 | Default | d | OL | |
TP_SMC_MPM5_LED_CHG | Default | d | 0.751 | |
TP_SMC_TRST_L | Default | d | OL | |
TP_SUS_PGOOD_MR_L | Default | d | 0.700 | |
TP_TDM_ONEWIRE_MPM | Default | d | OL | |
UNCONNECTED_10 | Default | d | OL | |
UNCONNECTED_11 | Default | d | OL | |
UNCONNECTED_12 | Default | d | OL | |
UNCONNECTED_13 | Default | d | 0v70 | |
UNCONNECTED_14 | Default | d | 0v70 | |
UNCONNECTED_15 | Default | d | 0v70 | |
UNCONNECTED_177 | Default | d | 0v62 | |
UNCONNECTED_178 | Default | d | 0v43 | |
UNCONNECTED_179 | Default | d | 0v61 | |
UNCONNECTED_180 | Default | d | 0v00 | |
UNCONNECTED_181 | Default | d | 0v62 | |
UNCONNECTED_182 | Default | d | 0v45 | |
UNCONNECTED_183 | Default | d | 0v61 | |
UNCONNECTED_184 | Default | d | 0v02 | |
UNCONNECTED_185 | Default | d | 0v62 | |
UNCONNECTED_186 | Default | d | 0v44 | |
UNCONNECTED_187 | Default | d | 0v62 | |
UNCONNECTED_188 | Default | d | 0v02 | |
UNCONNECTED_202 | Default | d | OL | |
UNCONNECTED_203 | Default | d | OL | |
UNCONNECTED_27 | Default | d | OL | |
UNCONNECTED_28 | Default | d | OL | |
UNCONNECTED_445 | Default | d | OL | |
UNCONNECTED_447 | Default | d | OL | |
UNCONNECTED_448 | Default | d | OL | |
UNCONNECTED_449 | Default | d | OL | |
UNCONNECTED_450 | Default | d | OL | |
UNCONNECTED_451 | Default | d | OL | |
UNCONNECTED_452 | Default | d | OL | |
UNCONNECTED_453 | Default | d | OL | |
UNCONNECTED_454 | Default | d | OL | |
UNCONNECTED_455 | Default | d | OL | |
UNCONNECTED_456 | Default | d | OL | |
UNCONNECTED_457 | Default | d | OL | |
UNCONNECTED_458 | Default | d | OL | |
UNCONNECTED_459 | Default | d | OL | |
UNCONNECTED_460 | Default | d | OL | |
UNCONNECTED_461 | Default | d | OL | |
UNCONNECTED_462 | Default | d | OL | |
UNCONNECTED_463 | Default | d | OL | |
UNCONNECTED_464 | Default | d | OL | |
UNCONNECTED_465 | Default | d | OL | |
UNCONNECTED_466 | Default | d | OL | |
UNCONNECTED_473 | Default | d | OL | |
UNCONNECTED_532 | Default | d | OL | |
UNCONNECTED_537 | Default | d | 0v52 | |
UNCONNECTED_538 | Default | d | 0v52 | |
UNCONNECTED_541 | Default | v | 0.00 | |
UNCONNECTED_544 | Default | v | 0.00 | |
UNCONNECTED_553 | Default | d | OL | |
UNCONNECTED_6 | Default | d | OL | |
UNCONNECTED_7 | Default | d | OL | |
UNCONNECTED_8 | Default | d | OL | |
UNCONNECTED_9 | Default | d | OL | |
USB3_EXTA_D2R_N | Default | d | 0.378 | |
USB3_EXTA_D2R_P | Default | d | 0.380 | |
USB3_EXTB_D2R_N | Default | d | 0.395 | |
USB3_EXTB_D2R_P | Default | d | 0.396 | |
USB3_EXTB_R2D_C_N | Default | d | 0.372 | |
USB3_EXTB_R2D_C_P | Default | d | 0.371 | |
USB3_EXTB_R2D_N | Default | d | OL | |
USB3_EXTB_R2D_P | Default | d | OL | |
USB3_SD_D2R_N | Default | d | 0.376 | |
USB3_SD_D2R_P | Default | d | 0.377 | |
USB3_SD_R2D_C_N | Default | d | 0.372 | |
USB3_SD_R2D_C_P | Default | d | 0.370 | |
USB_BT_CONN_N | Default | d | 0v65 | |
USB_BT_CONN_P | Default | d | 0v64 | |
USB_BT_N | Default | d | 0.476 | |
USB_BT_P | Default | d | 0.478 | |
USB_BT_WAKEN | Default | d | 0.691 | |
USB_EXTA_MUXED_N | Default | d | 0.672 | |
USB_EXTA_MUXED_P | Default | d | 0.669 | |
USB_EXTA_N | Default | d | 0.465 | |
USB_EXTA_OC_L | Default | d | 0.503 | |
USB_EXTA_P | Default | d | 0.468 | |
USB_EXTB_N | Default | d | 0.465 | |
USB_EXTB_OC_L | Default | d | 0v52 | |
USB_EXTB_P | Default | d | 0.464 | |
USB_ILIM | Default | d | 0.552 | |
USB_LT1_N | Default | d | 0.675 | |
USB_LT1_P | Default | d | 0.672 | |
USB_PWR_EN | Default | d | 0.498 | |
USB_TPAD_N | Default | d | 0.446 | |
USB_TPAD_P | Default | d | 0.458 | |
USB_TPAD_R_N | Default | d | 0v46 | |
USB_TPAD_R_P | Default | d | 0v46 | |
VMON_3V3_DIV | Default | d | OL | |
VMON_5V_DIV | Default | d | OL | |
VMON_MR | Default | d | OL | |
VMON_Q2_BASE | Default | d | OL | |
VMON_Q3_BASE | Default | d | 1.152 | |
VMON_Q4_BASE | Default | d | OL | |
VREFMRGN_CA_AB | Default | d | OL | |
VREFMRGN_CA_A_EN | Default | d | OL | |
VREFMRGN_CA_A_EN_RC | Default | d | OL | |
VREFMRGN_CA_A_RDIV | Default | d | OL | |
VREFMRGN_CA_B_EN | Default | d | OL | |
VREFMRGN_CA_B_EN_RC | Default | d | OL | |
VREFMRGN_CA_B_RDIV | Default | d | OL | |
VREFMRGN_DQ_A_EN | Default | d | OL | |
VREFMRGN_DQ_A_EN_RC | Default | d | OL | |
VREFMRGN_DQ_A_RDIV | Default | d | OL | |
VREFMRGN_DQ_B_EN | Default | d | OL | |
VREFMRGN_DQ_B_EN_RC | Default | d | OL | |
VREFMRGN_DQ_B_RDIV | Default | d | OL | |
VREFMRGN_FRAMEBUF_BUF | Default | d | OL | |
VREFMRGN_FRAMEBUF_EN | Default | d | OL | |
VREFMRGN_MEMVREG_BUF | Default | d | OL | |
VREFMRGN_MEMVREG_EN | Default | d | OL | |
VREFMRGN_MEMVREG_FBVREF | Default | d | OL | |
VTTCLAMP_EN | Default | d | 0.620 | |
VTTCLAMP_L | Default | d | 0.106 | |
WIFI_EVENT_L | Default | d | 0v73 | |
WOL_EN | Default | d | 0.576 | |
WS_CONTROL_KBD | Default | d | 0v47 | |
WS_CONTROL_KEY | Default | d | 0v47 | |
WS_KBD1 | Default | d | 0v70 | |
WS_KBD10 | Default | d | 0v70 | |
WS_KBD11 | Default | d | 0v70 | |
WS_KBD12 | Default | d | 0v70 | |
WS_KBD13 | Default | d | 0v70 | |
WS_KBD14 | Default | d | 0v70 | |
WS_KBD15_C | Default | d | 0v70 | |
WS_KBD15_CAP | Default | d | 0v78 | |
WS_KBD16N | Default | d | 0v70 | |
WS_KBD16_NUM | Default | d | 0v68 | |
WS_KBD17 | Default | d | 0v67 | |
WS_KBD18 | Default | d | 0v67 | |
WS_KBD19 | Default | d | 0v66 | |
WS_KBD2 | Default | d | 0v70 | |
WS_KBD20 | Default | d | 0v70 | |
WS_KBD21 | Default | d | 0v70 | |
WS_KBD22 | Default | d | 0v70 | |
WS_KBD23 | Default | d | 0v70 | |
WS_KBD3 | Default | d | 0v70 | |
WS_KBD4 | Default | d | 0v70 | |
WS_KBD5 | Default | d | 0v70 | |
WS_KBD6 | Default | d | 0v70 | |
WS_KBD7 | Default | d | 0v70 | |
WS_KBD8 | Default | d | 0v70 | |
WS_KBD9 | Default | d | 0v70 | |
WS_KBD_ONOFF_L | Default | d | 1v22 | |
WS_LEFT_OPTION_KBD | Default | d | 0v47 | |
WS_LEFT_OPTION_KEY | Default | d | 0.475 | |
WS_LEFT_SHIFT_KBD | Default | d | 0v47 | |
WS_LEFT_SHIFT_KEY | Default | d | 0.475 | |
X29THMSNS_A0 | Default | d | 0.677 | |
XDP_BPM_L<0> | Default | d | 0v25 | |
XDP_BPM_L<1> | Default | d | 0v25 | |
XDP_BPM_L<2> | Default | d | 0.271 | |
XDP_BPM_L<3> | Default | d | 0.270 | |
XDP_BPM_L<4> | Default | d | 0.269 | |
XDP_BPM_L<5> | Default | d | 0.270 | |
XDP_BPM_L<6> | Default | d | 0.272 | |
XDP_BPM_L<7> | Default | d | 0.272 | |
XDP_CPUPCH_TRST_L | Default | d | 0.052 | |
XDP_CPURST_L | Default | d | 1v15 | |
XDP_CPU_PRDY_L | Default | d | 0v26 | |
XDP_CPU_PREQ_L | Default | d | 0v26 | |
XDP_CPU_PRESENT_L | Default | d | 0v95 | |
XDP_CPU_PWRBTN_L | Default | d | 0v58 | |
XDP_CPU_TCK | Default | d | 0v06 | |
XDP_CPU_TDI | Default | d | 0.266 | |
XDP_CPU_TMS | Default | d | 0.265 | |
XDP_CPU_VCCST_PWRGD | Default | d | 1v02 | |
XDP_DA1_USB_EXTC_OC_L | Default | d | 0.547 | |
XDP_DA2_SSD_PWR_EN | Default | d | 0.456 | |
XDP_DA3_CAMERA_PWR_EN | Default | d | 0.545 | |
XDP_DB0_USB_EXTB_OC_L | Default | d | 0.553 | |
XDP_DB1_USB_EXTD_OC_L | Default | d | 0.552 | |
XDP_DB2_SD_PWR_EN | Default | d | 0.549 | |
XDP_DB3_SDCONN_STATE_CHANGE_L | Default | d | 0.504 | |
XDP_DBRESET_L | Default | d | 0v61 | |
XDP_DC0_DP_AUXCH_ISOL_L | Default | d | 0.511 | |
XDP_DC2_ODD_PWR_EN_L | Default | d | 0.535 | |
XDP_DC3_JTAG_ISP_TCK | Default | d | 0.502 | |
XDP_DD1_MLB_RAMCFG1 | Default | d | 0.456 | |
XDP_DD2_ENETSD_CLKREQ_L | Default | d | 0.539 | |
XDP_FC0_HDD_PWR_EN | Default | d | 0.518 | |
XDP_FC1_GPU_GOOD | Default | d | 0.537 | |
XDP_JTAG_CPU_ISOL_L | Default | d | 0.609 | |
XDP_PCH_TCK | Default | d | 0v06 | |
XDP_PCH_TDI | Default | d | 0v37 | |
XDP_PCH_TDO | Default | d | 0v37 | |
XDP_PCH_TMS | Default | d | 0v37 | |
XDP_SYS_PWROK | Default | d | 0v73 | |
XDP_TRST_L | Default | d | 0v61 | |
Z2_CLKIN | Default | d | 0v70 | |
Z2_CS_L | Default | d | 0v70 | |
Z2_HOST_INTN | Default | d | 0v69 | |
Z2_KEY_ACT_L | Default | d | 0v70 | |
Z2_MISO | Default | d | 0v69 | |
Z2_MOSI | Default | d | 0v70 | |
Z2_SCLK | Default | d | 0v69 |
Component | Type | Value |
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