Netname | Condition | Type | Value | Comment |
50_0_ANT | Default | d | 0.000 | |
50_1_ANT | Default | d | 0.000 | |
50_2_ANT | Default | d | 0.000 | |
5VG3S_VFB1_RR | Default | d | 0.600 | |
ACT_GND | Default | d | 0.544 | |
ADC1_REFCOMP | Default | d | OL | |
ADC2_REFCOMP | Default | d | OL | |
AGND_P2V5S3 | Default | d | 0.000 | |
AGND_PVDD075GPU | Default | d | 0.000 | |
AGND_PVDD18GPU | Default | d | 0.000 | |
ALL_SYS_PWRGD | Default | d | 0.516 | |
ANGLE_SENSOR_MGL | Default | d | 0.541 | |
ANGLE_SENSOR_ND | Default | d | 0.539 | |
AUD_CONN_HP_LEFT | Default | d | 0.703 | |
AUD_CONN_HP_RIGHT | Default | d | 0.707 | |
AUD_CONN_HP_SENSE_L | Default | d | 1.329 | |
AUD_CONN_HP_SENSE_R | Default | d | 1.328 | |
AUD_CONN_RING2 | Default | d | 0.000 | |
AUD_CONN_RING2_XW | Default | d | 0.632 | |
AUD_CONN_RING_SENSE | Default | d | OL | |
AUD_CONN_SLEEVE | Default | d | 0.000 | |
AUD_CONN_SLEEVE_XW | Default | d | 0.631 | |
AUD_CONN_TIP_SENSE | Default | d | OL | |
AUD_DMIC0_CLK_CONN | Default | d | 0.515 | |
AUD_DMIC0_DATA_CONN | Default | d | 0.554 | |
AUD_DMIC1_CLK_CONN | Default | d | 0.514 | |
AUD_DMIC1_DATA_CONN | Default | d | 0.546 | |
AUD_HP_PORT_CH_GND | Default | d | 0.000 | |
AUD_HP_PORT_L | Default | d | 0.703 | |
AUD_HP_PORT_R | Default | d | 0.707 | |
AUD_HP_PORT_US_GND | Default | d | 0.000 | |
AUD_HP_SENSE_L | Default | d | 1.329 | |
AUD_HP_SENSE_R | Default | d | 1.328 | |
AUD_HS_MIC_N | Default | d | 0.632 | |
AUD_HS_MIC_P | Default | d | 0.631 | |
AUD_RING_SENSE | Default | d | 0.644 | |
AUD_TIP_SENSE | Default | d | 1.420 | |
BKLT_EN_R | Default | d | 0.528 | |
BKLT_ISET_KEYB | Default | d | 0.680 | |
BKLT_KEYB1 | Default | d | 0.659 | |
BKLT_KEYB2 | Default | d | 0.653 | |
BKLT_PWM_KEYB_3V3 | Default | d | 0.546 | |
BKLT_PWM_MLB2TCON | Default | d | OL | |
BKLT_SCL | Default | d | 0.539 | |
BKLT_SD | Default | d | 0.597 | |
BKLT_SDA | Default | d | 0.539 | |
BKLT_SENSE_OUT | Default | d | 0.734 | |
BT_AUDIO_SYNC | Default | d | 0.637 | |
BT_AUDIO_SYNC_LS3V3 | Default | d | 0.620 | |
BT_SFLASH_CS_L | Default | d | 0.692 | |
BT_SFLASH_HOLD_L | Default | d | 0.665 | |
BT_SFLASH_WP_L | Default | d | 0.666 | |
BT_SPI2_CLK | Default | d | 0.681 | |
BT_SPI2_CSN | Default | d | 0.717 | |
BT_SPI2_MISO | Default | d | 0.640 | |
BT_SPI2_MOSI | Default | d | 0.645 | |
CAPSLOCK_LED_DRV | Default | d | 0.755 | |
CAPSLOCK_LED_EN | Default | d | 0.509 | |
CHGR_AMON | Default | d | 0.598 | |
CHGR_AUX_DET | Default | d | 0.634 | |
CHGR_BGATE | Default | d | 0.632 | |
CHGR_BMON | Default | d | 0.605 | |
CHGR_BOOT1 | Default | d | 0.692 | |
CHGR_BOOT1_RC | Default | d | 0.592 | |
CHGR_BOOT2 | Default | d | 0.588 | |
CHGR_BOOT2_RC | Default | d | 0.588 | |
CHGR_COMP | Default | d | 0.632 | |
CHGR_CSI_N | Default | d | 0.552 | |
CHGR_CSI_P | Default | d | 0.552 | |
CHGR_CSI_R_N | Default | d | 0.552 | |
CHGR_CSI_R_P | Default | d | 0.552 | |
CHGR_CSO_N | Default | d | 0.416 | |
CHGR_CSO_P | Default | d | 0.417 | |
CHGR_CSO_R_N | Default | d | 0.415 | |
CHGR_CSO_R_N | Default | r | 410.000 | |
CHGR_CSO_R_P | Default | d | 0.415 | |
CHGR_CSO_R_P | Default | r | 410.000 | |
CHGR_EN_MVR | Default | d | 0.609 | |
CHGR_EN_MVR_R | Default | d | 0.612 | |
CHGR_GATE_Q1 | Default | d | 0.730 | |
CHGR_GATE_Q2 | Default | d | 0.455 | |
CHGR_GATE_Q3 | Default | d | 0.462 | |
CHGR_GATE_Q4 | Default | d | 0.720 | |
CHGR_INT_L | Default | d | 0.590 | |
CHGR_LX1 | Default | d | 0.505 | |
CHGR_LX2 | Default | d | 0.506 | |
CHGR_PBUS_SENSE | Default | d | 0.415 | |
CHGR_PHASE1 | Default | d | 0.507 | |
CHGR_PHASE1 | Default | r | 305.700R | |
CHGR_PHASE2 | Default | d | 0.507 | |
CHGR_RST_IN | Default | d | 0.625 | |
CHGR_RST_IN_R | Default | d | 0.610 | |
CHGR_VBAT | Default | d | 0.636 | |
CHGR_VDDA | Default | d | 0.459 | |
CHGR_VDDA | Default | v | 5.000 | |
CHGR_VDDP | Default | d | 0.456 | |
CHGR_VDDP | Default | v | 5.000 | |
CODEC_INT_L | Default | d | 0.494 | |
CODEC_RESET_L | Default | d | 0.497 | |
CODEC_WAKE_L | Default | d | 0.492 | |
COMP_A_CPUCORE | Default | d | 0.626 | |
COMP_A_CPUCORE_L | Default | d | OL | |
COMP_B_CPUGT | Default | d | 0.627 | |
COMP_B_CPUGT_L | Default | d | OL | |
COMP_C_CPUSA | Default | d | 0.626 | |
COMP_C_CPUSA_L | Default | d | OL | |
CORE_ISUMN_R | Default | d | 1.015 | |
CPUCORE_ISEN1 | Default | d | 0.627 | |
CPUCORE_ISEN2 | Default | d | 0.627 | |
CPUCORE_ISEN3 | Default | d | 0.628 | |
CPUCORE_ISNS1_N | Default | d | 0.002 | |
CPUCORE_ISNS1_P | Default | d | 0.002 | |
CPUCORE_ISNS2_N | Default | d | 0.002 | |
CPUCORE_ISNS2_P | Default | d | 0.002 | |
CPUCORE_ISNS3_N | Default | d | 0.002 | |
CPUCORE_ISNS3_P | Default | d | 0.002 | |
CPUCORE_ISUMN | Default | d | 0.004 | |
CPUCORE_ISUMN | Default | r | 3.800R | |
CPUCORE_ISUMN_R | Default | d | 0.442 | |
CPUCORE_ISUMP | Default | d | 0.340 | |
CPUCORE_PROCHOT_R_L | Default | d | 0.522 | |
CPUCORE_PSYS | Default | d | 0.624 | |
CPUCORE_SW1 | Default | d | 0.002 | |
CPUCORE_SW1 | Default | r | 2.400R | |
CPUCORE_SW2 | Default | d | 0.002 | |
CPUCORE_SW2 | Default | r | 2.400R | |
CPUCORE_SW3 | Default | d | 0.002 | |
CPUCORE_VIDALERT_R_L | Default | d | 0.277 | |
CPUCORE_VIDSCLK_R | Default | d | 0.281 | |
CPUCORE_VIDSOUT_R | Default | d | 0.242 | |
CPUGT_ISEN1 | Default | d | 0.627 | |
CPUGT_ISEN2 | Default | d | 0.627 | |
CPUGT_ISNS1_N | Default | d | 0.010 | |
CPUGT_ISNS1_P | Default | d | 0.010 | |
CPUGT_ISNS2_N | Default | d | 0.010 | |
CPUGT_ISNS2_P | Default | d | 0.010 | |
CPUGT_ISNS_N | Default | d | OL | |
CPUGT_ISNS_P | Default | d | OL | |
CPUGT_ISNS_R_N | Default | d | OL | |
CPUGT_ISNS_R_P | Default | d | OL | |
CPUGT_ISUMN | Default | d | 0.007 | |
CPUGT_ISUMN | Default | r | 6.700R | |
CPUGT_ISUMN_R | Default | d | 0.341 | |
CPUGT_ISUMP | Default | d | 0.480 | |
CPUGT_ISUM_IOUT | Default | d | OL | |
CPUGT_SW1 | Default | d | 0.010 | |
CPUGT_SW1 | Default | r | 9.500R | |
CPUGT_SW2 | Default | d | 0.010 | |
CPUSA_ISNS_N | Default | d | 0.033 | |
CPUSA_ISNS_P | Default | d | 0.033 | |
CPUSA_ISUMN | Default | d | 0.022 | |
CPUSA_ISUMN | Default | r | 21.700R | |
CPUSA_ISUMN_R | Default | d | 0.490 | |
CPUSA_ISUMP | Default | d | 0.575 | |
CPUVR_ISNS_N | Default | d | OL | |
CPUVR_ISNS_P | Default | d | OL | |
CPUVR_ISNS_R_N | Default | d | OL | |
CPUVR_ISNS_R_P | Default | d | OL | |
CPUVR_ISUM_IOUT | Default | d | OL | |
CPUVR_PGOOD | Default | d | 0.575 | |
CPUVR_SWSA | Default | d | 0.033 | |
CPUVSENSE_IN | Default | d | 0.007 | |
CPUVSENSE_IN | Default | r | 5.100R | |
CPU_C10_GATE_L | Default | d | 0.484 | |
CPU_CATERR_L | Default | d | 0.232 | |
CPU_CFG<0> | Default | d | 0.284 | |
CPU_CFG<10> | Default | d | 0.285 | |
CPU_CFG<11> | Default | d | 0.287 | |
CPU_CFG<12> | Default | d | 0.284 | |
CPU_CFG<13> | Default | d | 0.284 | |
CPU_CFG<14> | Default | d | 0.285 | |
CPU_CFG<15> | Default | d | 0.287 | |
CPU_CFG<17> | Default | d | 0.288 | |
CPU_CFG<19> | Default | d | 0.285 | |
CPU_CFG<1> | Default | d | 0.285 | |
CPU_CFG<2> | Default | d | 0.285 | |
CPU_CFG<3> | Default | d | 0.284 | |
CPU_CFG<4> | Default | d | 0.271 | |
CPU_CFG<5> | Default | d | 0.270 | |
CPU_CFG<6> | Default | d | 0.271 | |
CPU_CFG<7> | Default | d | 0.284 | |
CPU_CFG<8> | Default | d | 0.284 | |
CPU_CFG<9> | Default | d | 0.285 | |
CPU_CFG_RCOMP | Default | d | 0.052 | |
CPU_CFG_RCOMP | Default | r | 50.400R | |
CPU_DC_B2_C1 | Default | d | OL | |
CPU_DC_B38_C38 | Default | d | OL | |
CPU_DC_BR1_BR2 | Default | d | 0.345 | |
CPU_DC_BR2_BR1 | Default | d | OL | |
CPU_DC_C1_B2 | Default | d | OL | |
CPU_DC_C38_B38 | Default | d | OL | |
CPU_EDP_RCOMP | Default | d | 0.095 | |
CPU_PCH_PM_DOWN | Default | d | 0.289 | |
CPU_PCH_PM_DOWN_R | Default | d | 0.277 | |
CPU_PECI | Default | d | 0.369 | |
CPU_PEG_RCOMP | Default | d | 0.093 | |
CPU_PROCHOT_L | Default | d | 0.464 | |
CPU_PROCHOT_OUT_L | Default | d | 0.466 | |
CPU_PROCHOT_R_L | Default | d | 0.280 | |
CPU_PWRGD | Default | d | 0.323 | |
CPU_SM_RCOMP<0> | Default | d | 0.122 | |
CPU_SM_RCOMP<1> | Default | d | 0.123 | |
CPU_SM_RCOMP<2> | Default | d | 0.102 | |
CPU_VCCGTSENSE_N | Default | d | 0.004 | |
CPU_VCCGTSENSE_N | Default | r | 2.700R | |
CPU_VCCGTSENSE_P | Default | d | 0.007 | |
CPU_VCCGTSENSE_P | Default | r | 7.700R | |
CPU_VCCIOSENSENEG_R | Default | d | 0.005 | |
CPU_VCCIOSENSENEG_R | Default | r | 5.100R | |
CPU_VCCIOSENSEPOS_R | Default | d | 0.135 | |
CPU_VCCIOSENSE_P | Default | d | 0.061 | |
CPU_VCCIOSENSE_P | Default | r | 60.000R | |
CPU_VCCSASENSE_N | Default | d | 0.005 | |
CPU_VCCSASENSE_N | Default | r | 3.200R | |
CPU_VCCSASENSE_P | Default | d | 0.024 | |
CPU_VCCSASENSE_P | Default | r | 23.200R | |
CPU_VCCSENSE_N | Default | d | 0.004 | |
CPU_VCCSENSE_N | Default | r | 3.100R | |
CPU_VCCSENSE_P | Default | d | 0.006 | |
CPU_VCCSENSE_P | Default | r | 5.500R | |
CPU_VCCST_PWRGD | Default | d | 0.532 | |
CPU_VIDALERT_L | Default | d | 0.650 | |
CPU_VIDALERT_R_L | Default | d | 0.870 | |
CPU_VIDSCLK | Default | d | 0.229 | |
CPU_VIDSCLK_R | Default | d | 0.230 | |
CPU_VIDSOUT | Default | d | 0.230 | |
CPU_VIDSOUT_R | Default | d | 0.230 | |
CPU_VR_EN_R | Default | d | 0.532 | |
DBGLED_C10 | Default | d | OL | |
DBGLED_GPU | Default | d | OL | |
DBGLED_GPU_D | Default | d | OL | |
DBGLED_MEM_OK_D | Default | d | OL | |
DBGLED_S0I3 | Default | d | OL | |
DBGLED_S0I3_D | Default | d | OL | |
DBGLED_S5 | Default | d | OL | |
DDR2V5_IOUT | Default | d | OL | |
DDRREG_VTTSNS | Default | d | 0.134 | |
DFR_DISP_INT | Default | d | 0.496 | |
DFR_DISP_RESET_L | Default | d | 0.495 | |
DFR_DISP_TE | Default | d | 0.496 | |
DFR_DISP_VSYNC | Default | d | OL | |
DFR_LID_OPEN_L | Default | d | OL | |
DFR_PWR_EN | Default | d | 0.494 | |
DFR_PWR_EN_R | Default | d | 0.564 | |
DFR_TOUCH_CLK32K_RESET_L | Default | d | 0.470 | |
DFR_TOUCH_INT_L | Default | d | 0.475 | |
DFR_TOUCH_RESET_L | Default | d | 0.470 | |
DISP_GCON_INT_L | Default | d | 0.482 | |
DISP_GCON_RESET_L | Default | d | 0.682 | |
DISP_GCON_RESET_L_R | Default | d | 0.681 | |
DP_INT_EG_HPD | Default | d | 0.384 | |
DP_INT_HPD | Default | d | 0.656 | |
DP_INT_HPD_R | Default | d | 0.606 | |
DP_TA_HPD | Default | d | 0.559 | |
DP_TB_HPD | Default | d | 0.561 | |
DP_T_SNK1_HPD | Default | d | 0.581 | |
DP_XA_HPD | Default | d | 0.605 | |
DP_XB_HPD | Default | d | 0.567 | |
DP_X_SNK0_HPD | Default | d | 0.555 | |
DP_X_SNK1_HPD | Default | d | 0.588 | |
EADC1_CPUSA_VSENSE | Default | d | OL | |
EADC1_TBT_X_ISENSE | Default | d | OL | |
EADC2_AD0 | Default | d | OL | |
EADC2_GPU_MEM_VDDCI_ISENSE | Default | d | OL | |
EADC2_GPU_MEM_VDDIO_ISENSE | Default | d | OL | |
EDP_BKLT_EN | Default | d | 0.530 | |
EDP_INT_AUX_N | Default | d | 0.461 | |
EDP_INT_AUX_P | Default | d | 0.694 | |
EDP_INT_ML_N<0> | Default | d | 0.412 | |
EDP_INT_ML_N<1> | Default | d | 0.413 | |
EDP_INT_ML_N<2> | Default | d | 0.416 | |
EDP_INT_ML_N<3> | Default | d | 0.413 | |
EDP_INT_ML_P<0> | Default | d | 0.411 | |
EDP_INT_ML_P<1> | Default | d | 0.411 | |
EDP_INT_ML_P<2> | Default | d | 0.413 | |
EDP_INT_ML_P<3> | Default | d | 0.412 | |
EDP_PANEL_PWR_BUF_EN | Default | d | 0.613 | |
EDP_PANEL_PWR_DLY_EN | Default | d | 0.706 | |
EDP_PANEL_PWR_EN | Default | d | 0.537 | |
EG_RESET_L_BUFF | Default | d | 0.615 | |
EG_VR0_EN | Default | d | 0.504 | |
EG_VR0_PGOOD | Default | d | 0.611 | |
EG_VR1_EN | Default | d | 0.603 | |
EG_VR1_PGOOD | Default | d | 0.596 | |
EG_VR2_EN | Default | d | 0.625 | |
EG_VR2_PGOOD | Default | d | 0.530 | |
EG_VR3_EN | Default | d | 0.572 | |
EG_VR3_PGOOD | Default | d | 0.604 | |
EG_VR4_EN | Default | d | 0.576 | |
EG_VR4_PGOOD | Default | d | 0.459 | |
FAN_LT_PWM | Default | d | 0.754 | |
FAN_LT_TACH | Default | d | OL | |
FAN_RT_PWM | Default | d | 0.770 | |
FAN_RT_TACH | Default | d | OL | |
FB_A_CORE_R | Default | d | 1.616 | |
FB_A_CPUCORE | Default | d | 0.614 | |
FB_A_CPUCORE_RC | Default | d | 1.177 | |
FB_B_CPUGT | Default | d | 0.595 | |
FB_B_CPUGT_RC | Default | d | 1.162 | |
FB_B_GT_R | Default | d | OL | |
FB_CORE_R | Default | d | 0.006 | |
FB_CORE_R | Default | r | 5.200R | |
FB_C_CPUSA | Default | d | 0.604 | |
FB_C_CPUSA_RC | Default | d | OL | |
FB_C_SA_R | Default | d | OL | |
FB_GT_R | Default | d | 0.009 | |
FB_GT_R | Default | r | 7.800R | |
FB_SA_R | Default | d | 0.024 | |
FB_SA_R | Default | r | 23.200R | |
GFXGPU_SUM_N | Default | d | 0.760 | |
GFXGPU_SUM_P | Default | d | 0.760 | |
GFXGPU_SUM_R_N | Default | d | 0.593 | |
GFXGPU_SUM_R_P | Default | d | 0.593 | |
GFX_THROTTLE_1V8_R_L | Default | d | 0.485 | |
GMUX_IOEXP_ADDR_SEL | Default | d | 0.000 | |
GND | Default | d | 0.000 | |
GND_5V3V3_AGND | Default | d | 0.000 | |
GND_BKLT_SGND | Default | d | 0.000 | |
GND_P3V3G3HRTC_AGND | Default | d | 0.000 | |
GPUCOREVSENSE_IN | Default | d | 0.007 | |
GPUCOREVSENSE_IN | Default | r | 3.500R | |
GPUSOCVSENSE_IN | Default | d | 0.011 | |
GPUSOCVSENSE_IN | Default | r | 9.500R | |
GPU_CLKREQ_L_R | Default | d | 0.492 | |
GPU_DBREQ_L | Default | d | 0.433 | |
GPU_GFX_OVERTEMP | Default | d | 0.404 | |
GPU_GFX_OVERTEMP_R | Default | d | 0.576 | |
GPU_GPIO_SVC0 | Default | d | 0.462 | |
GPU_GPIO_SVD0 | Default | d | 0.458 | |
GPU_GPIO_SVT0 | Default | d | 0.436 | |
GPU_GPIO_SVT0_R | Default | d | 0.456 | |
GPU_JTAG_TCK | Default | d | 0.398 | |
GPU_JTAG_TDI | Default | d | 0.437 | |
GPU_JTAG_TDO | Default | d | 0.436 | |
GPU_JTAG_TESTEN | Default | d | 0.344 | |
GPU_JTAG_TMS | Default | d | 0.436 | |
GPU_JTAG_TRST_L | Default | d | 0.468 | |
GPU_PCC_ALERT_L | Default | d | 0.491 | |
GPU_PCC_COMP_NEG | Default | d | 0.468 | |
GPU_PCC_COMP_POS | Default | d | 0.735 | |
GPU_PROCHOT_L | Default | d | 0.480 | |
GPU_RESET_L | Default | d | 0.551 | |
GPU_RESET_L_CONN | Default | d | OL | |
GPU_RESET_L_R | Default | d | 0.710 | |
GPU_RESET_R_L | Default | d | 0.553 | |
GPU_VDDCR_GFX_COMP | Default | d | 0.626 | |
GPU_VDDCR_GFX_FB | Default | d | 0.005 | |
GPU_VDDCR_GFX_FB | Default | r | 4.800R | |
GPU_VDDCR_GFX_FB_PIN | Default | d | 0.589 | |
GPU_VDDCR_GFX_FB_R | Default | d | 0.016 | |
GPU_VDDCR_GFX_FB_R | Default | r | 14.900R | |
GPU_VDDCR_GFX_FB_R_C | Default | d | 0.690 | |
GPU_VDDCR_GFX_FCCM | Default | d | 0.598 | |
GPU_VDDCR_GFX_IMON | Default | d | 0.627 | |
GPU_VDDCR_GFX_ISEN1 | Default | d | 0.628 | |
GPU_VDDCR_GFX_ISEN2 | Default | d | 0.628 | |
GPU_VDDCR_GFX_ISEN3 | Default | d | 0.628 | |
GPU_VDDCR_GFX_ISEN4 | Default | d | 0.628 | |
GPU_VDDCR_GFX_ISNS1_N | Default | d | 0.016 | |
GPU_VDDCR_GFX_ISNS1_P | Default | d | 0.016 | |
GPU_VDDCR_GFX_ISNS2_N | Default | d | 0.016 | |
GPU_VDDCR_GFX_ISNS2_P | Default | d | 0.016 | |
GPU_VDDCR_GFX_ISNS3_N | Default | d | 0.016 | |
GPU_VDDCR_GFX_ISNS3_P | Default | d | 0.016 | |
GPU_VDDCR_GFX_ISNS4_N | Default | d | 0.016 | |
GPU_VDDCR_GFX_ISNS4_P | Default | d | 0.016 | |
GPU_VDDCR_GFX_ISUM_N | Default | d | 0.003 | |
GPU_VDDCR_GFX_ISUM_N | Default | r | 2.600R | |
GPU_VDDCR_GFX_ISUM_N_C | Default | d | 1.462 | |
GPU_VDDCR_GFX_ISUM_N_R | Default | d | 0.459 | |
GPU_VDDCR_GFX_ISUM_P | Default | d | 0.256 | |
GPU_VDDCR_GFX_ISUM_RC | Default | d | OL | |
GPU_VDDCR_GFX_NTC | Default | d | 0.005 | |
GPU_VDDCR_GFX_NTC | Default | r | 5.200R | |
GPU_VDDCR_PROG1 | Default | d | 0.610 | |
GPU_VDDCR_PROG2 | Default | d | 0.613 | |
GPU_VDDCR_RTN | Default | d | 0.005 | |
GPU_VDDCR_RTN | Default | r | 4.000R | |
GPU_VDDCR_RTN_R | Default | d | 0.004 | |
GPU_VDDCR_RTN_R | Default | r | 3.800R | |
GPU_VDDCR_SOC_COMP | Default | d | 0.628 | |
GPU_VDDCR_SOC_FB | Default | d | 0.011 | |
GPU_VDDCR_SOC_FB | Default | r | 10.600R | |
GPU_VDDCR_SOC_FB_PIN | Default | d | 0.228 | |
GPU_VDDCR_SOC_FB_R | Default | d | 0.011 | |
GPU_VDDCR_SOC_FB_R | Default | r | 10.900R | |
GPU_VDDCR_SOC_FB_R_C | Default | d | 0.228 | |
GPU_VDDCR_SOC_IMON | Default | d | 0.628 | |
GPU_VDDCR_SOC_ISNS_N | Default | d | 0.007 | |
GPU_VDDCR_SOC_ISNS_P | Default | d | 0.007 | |
GPU_VDDCR_SOC_ISUM_N | Default | d | 0.012 | |
GPU_VDDCR_SOC_ISUM_N | Default | r | 11.400R | |
GPU_VDDCR_SOC_ISUM_N_C | Default | d | 1.518 | |
GPU_VDDCR_SOC_ISUM_N_R | Default | d | 0.515 | |
GPU_VDDCR_SOC_ISUM_P | Default | d | 0.576 | |
GPU_VDDCR_SOC_NTC | Default | d | 0.011 | |
GPU_VDDCR_SOC_NTC | Default | r | 11.000R | |
GPU_VDD_MEM_RTN | Default | d | 0.005 | |
GPU_VDD_MEM_RTN | Default | r | 3.400R | |
GPU_VRAM_D_RST_L | Default | d | 0.394 | |
GT_ISUMN_R | Default | d | 1.012 | |
HS_3V3_X_IOUT | Default | d | 0.712 | |
HS_OTHER5V_IOUT | Default | d | 0.711 | |
HS_P3V3_G3W_SSD0_OUT | Default | d | 0.723 | |
HS_P3V3_G3W_SSD1_OUT | Default | d | 0.720 | |
HS_PBUS_MAIN_SSD0_OUT | Default | d | 0.712 | |
HS_PBUS_MAIN_SSD1_OUT | Default | d | 0.712 | |
I2C_ALS_SCL | Default | d | 0.489 | |
I2C_ALS_SCL | Default | v | 1.800 | |
I2C_ALS_SDA | Default | d | 0.487 | |
I2C_ALS_SDA | Default | v | 1.800 | |
I2C_BKLT_SCL | Default | d | 0.542 | |
I2C_BKLT_SCL | Default | v | 5.000 | |
I2C_BKLT_SDA | Default | d | 0.542 | |
I2C_BKLT_SDA | Default | v | 5.000 | |
I2C_CAM_ISOL_SCL | Default | d | 0.522 | |
I2C_CAM_ISOL_SCL | Default | v | 1.800 | |
I2C_CAM_ISOL_SDA | Default | d | 0.522 | |
I2C_CAM_ISOL_SDA | Default | v | 1.800 | |
I2C_DFR_SCL_R | Default | d | 0.477 | |
I2C_DFR_SDA_R | Default | d | 0.470 | |
I2C_PWR_SCL | Default | d | 0.491 | |
I2C_PWR_SDA | Default | d | 0.490 | |
I2C_SEP_SCL | Default | d | 0.487 | |
I2C_SEP_SDA | Default | d | 0.483 | |
I2C_SNS0_S0_5V_SCL | Default | d | OL | |
I2C_SNS0_S0_5V_SDA | Default | d | OL | |
I2C_SNS0_S0_SCL | Default | d | 0.488 | |
I2C_SNS0_S0_SDA | Default | d | 0.488 | |
I2C_SNS1_S0_SCL | Default | d | 0.460 | |
I2C_SNS1_S0_SDA | Default | d | 0.459 | |
I2C_SNS_G3S_SCL | Default | d | 0.484 | |
I2C_SNS_G3S_SDA | Default | d | 0.483 | |
I2C_SSD0_SCL | Default | d | 0.502 | |
I2C_SSD0_SDA | Default | d | 0.503 | |
I2C_SSD1_SCL | Default | d | 0.501 | |
I2C_SSD_SCL | Default | d | 0.478 | |
I2C_SSD_SDA | Default | d | 0.480 | |
I2C_TBT_TA_INT_L | Default | d | 0.588 | |
I2C_TBT_TB_INT_L | Default | d | 0.560 | |
I2C_TBT_T_SCL | Default | d | 0.508 | |
I2C_TBT_T_SDA | Default | d | 0.508 | |
I2C_TBT_XA_INT_L | Default | d | 0.570 | |
I2C_TBT_XB_INT_L | Default | d | 0.570 | |
I2C_TBT_X_SCL | Default | d | 0.517 | |
I2C_TBT_X_SDA | Default | d | 0.517 | |
I2C_TCON_SCL | Default | d | 0.493 | |
I2C_TCON_SCL | Default | v | 3.300 | |
I2C_TCON_SDA | Default | d | 0.492 | |
I2C_TCON_SDA | Default | v | 3.300 | |
I2C_TPAD_CONN_SCL | Default | d | 0.515 | |
I2C_TPAD_CONN_SDA | Default | d | 0.514 | |
I2C_UPC_SCL | Default | d | 0.472 | |
I2C_UPC_SDA | Default | d | 0.474 | |
I2C_UPC_TA_DBG_CTL_SCL | Default | d | 0.560 | |
I2C_UPC_TA_DBG_CTL_SDA | Default | d | 0.563 | |
I2C_UPC_TB_DBG_CTL_SCL | Default | d | 0.563 | |
I2C_UPC_TB_DBG_CTL_SDA | Default | d | 0.563 | |
I2C_UPC_T_SCL2 | Default | d | 0.462 | |
I2C_UPC_T_SDA2 | Default | d | 0.466 | |
I2C_UPC_XA_DBG_CTL_SCL | Default | d | 0.598 | |
I2C_UPC_XA_DBG_CTL_SDA | Default | d | 0.598 | |
I2C_UPC_XB_DBG_CTL_SCL | Default | d | 0.565 | |
I2C_UPC_XB_DBG_CTL_SDA | Default | d | 0.564 | |
I2C_UPC_X_SCL2 | Default | d | 0.468 | |
I2C_UPC_X_SDA2 | Default | d | 0.457 | |
I2S_CODEC_D2R | Default | d | 0.484 | |
I2S_SPKRAMP_L_D2R | Default | d | 0.363 | |
I2S_SPKRAMP_L_D2R_R1 | Default | d | 0.376 | |
I2S_SPKRAMP_L_D2R_R2 | Default | d | 0.376 | |
I2S_SPKRAMP_L_D2R_R3 | Default | d | 0.376 | |
I2S_SPKRAMP_R_D2R | Default | d | 0.000 | |
I2S_SPKRAMP_R_D2R_R1 | Default | d | 0.375 | |
I2S_SPKRAMP_R_D2R_R2 | Default | d | 0.375 | |
I2S_SPKRAMP_R_D2R_R3 | Default | d | 0.376 | |
I2S_SPKRAMP_R_LRCLK | Default | d | 0.392 | |
I2S_SPKRAMP_R_LRCLK_R | Default | d | 0.374 | |
IAPC_OPA_OUT | Default | d | OL | |
IMON_A_CPUCORE | Default | d | 0.626 | |
IMON_B_CPUGT | Default | d | 0.631 | |
IMON_C_CPUSA | Default | d | 0.627 | |
IOXP1_INT_L | Default | d | 0.641 | |
IOXP1_RESET_L | Default | d | 0.748 | |
IOXP2_ADDR | Default | d | 0.723 | |
IOXP2_INT_L | Default | d | 0.641 | |
IOXP2_RESET_L | Default | d | 0.750 | |
IOXP_I2C_SCL | Default | d | 0.693 | |
IOXP_I2C_SDA | Default | d | 0.660 | |
IPD_LID_OPEN | Default | d | 0.638 | |
IPD_LID_OPEN_R | Default | d | OL | |
ISNS_1V0_N | Default | d | OL | |
ISNS_1V0_P | Default | d | OL | |
ISNS_2V5_S3_N | Default | d | OL | |
ISNS_2V5_S3_P | Default | d | OL | |
ISNS_CALPE_IOUT | Default | d | 0.714 | |
ISNS_CALPE_N | Default | d | 0.378 | |
ISNS_CALPE_P | Default | d | 0.378 | |
ISNS_CPUDDR_IOUT | Default | d | OL | |
ISNS_CPUDDR_N | Default | d | 0.223 | |
ISNS_CPUDDR_N | Default | r | 221.000 | |
ISNS_CPUDDR_P | Default | d | 0.223 | |
ISNS_CPUDDR_P | Default | r | 221.000 | |
ISNS_CPUVCCIO_NEG | Default | d | 0.496 | |
ISNS_CPUVCCIO_POS | Default | d | 0.495 | |
ISNS_CPUVDDQ_N | Default | d | OL | |
ISNS_CPUVDDQ_P | Default | d | OL | |
ISNS_DDR_IOUT | Default | d | 0.714 | |
ISNS_GPU1V8_IOUT | Default | d | OL | |
ISNS_GPUGFX_IOUT | Default | d | OL | |
ISNS_GPU_1V8_N | Default | d | OL | |
ISNS_GPU_1V8_P | Default | d | OL | |
ISNS_GPU_HS_IOUT | Default | d | 0.713 | |
ISNS_GPU_HS_N | Default | d | 0.415 | |
ISNS_GPU_HS_P | Default | d | 0.415 | |
ISNS_GPU_SOC_IOUT | Default | d | OL | |
ISNS_HS_3V3_T_N | Default | d | 0.415 | |
ISNS_HS_3V3_T_N | Default | r | 410.000 | |
ISNS_HS_3V3_T_N | Default | v | 12.600 | |
ISNS_HS_3V3_T_OUT | Default | d | 0.711 | |
ISNS_HS_3V3_T_P | Default | d | 0.415 | |
ISNS_HS_3V3_T_P | Default | r | 410.000 | |
ISNS_HS_3V3_T_P | Default | v | 12.600 | |
ISNS_HS_3V3_X_N | Default | d | 0.415 | |
ISNS_HS_3V3_X_N | Default | r | 410.000 | |
ISNS_HS_3V3_X_P | Default | d | 0.415 | |
ISNS_HS_3V3_X_P | Default | r | 410.000 | |
ISNS_HS_COMPUTING_N | Default | d | 0.415 | |
ISNS_HS_COMPUTING_N | Default | r | 410.000 | |
ISNS_HS_COMPUTING_N | Default | v | 12.600 | |
ISNS_HS_COMPUTING_OUT | Default | d | 0.714 | |
ISNS_HS_COMPUTING_P | Default | d | 0.415 | |
ISNS_HS_COMPUTING_P | Default | r | 410.000 | |
ISNS_HS_COMPUTING_P | Default | v | 12.600 | |
ISNS_HS_OTHER5V_N | Default | d | 0.415 | |
ISNS_HS_OTHER5V_N | Default | r | 0.200R | |
ISNS_HS_OTHER5V_N | Default | v | 12.600 | |
ISNS_HS_OTHER5V_P | Default | d | 0.415 | |
ISNS_HS_OTHER5V_P | Default | r | 0.000R | |
ISNS_HS_OTHER5V_P | Default | v | 12.600 | |
ISNS_KBDLED_IOUT | Default | d | OL | |
ISNS_KBDLED_N | Default | d | OL | |
ISNS_KBDLED_P | Default | d | OL | |
ISNS_LCDBKLT_IOUT | Default | d | OL | |
ISNS_LCDBKLT_N | Default | d | 0.415 | |
ISNS_LCDBKLT_P | Default | d | 0.415 | |
ISNS_LCDPANEL_IOUT | Default | d | OL | |
ISNS_LCDPANEL_N | Default | d | OL | |
ISNS_LCDPANEL_P | Default | d | OL | |
ISNS_P3V3S_WLAN_IOUT | Default | d | OL | |
ISNS_P3V3_G3W_SSD0_N | Default | d | 0.421 | |
ISNS_P3V3_G3W_SSD0_P | Default | d | 0.421 | |
ISNS_P3V3_G3W_SSD1_N | Default | d | 0.377 | |
ISNS_P3V3_G3W_SSD1_P | Default | d | 0.377 | |
ISNS_PPBUS_MAIN_SSD0_N | Default | d | 0.415 | |
ISNS_PPBUS_MAIN_SSD0_N | Default | r | 410.000 | |
ISNS_PPBUS_MAIN_SSD0_N | Default | v | 12.600 | |
ISNS_PPBUS_MAIN_SSD0_P | Default | d | 0.415 | |
ISNS_PPBUS_MAIN_SSD0_P | Default | r | 410.000 | |
ISNS_PPBUS_MAIN_SSD0_P | Default | v | 12.600 | |
ISNS_PPBUS_MAIN_SSD1_N | Default | d | 0.415 | |
ISNS_PPBUS_MAIN_SSD1_N | Default | r | 410.000 | |
ISNS_PPBUS_MAIN_SSD1_N | Default | v | 12.600 | |
ISNS_PPBUS_MAIN_SSD1_P | Default | d | 0.415 | |
ISNS_PPBUS_MAIN_SSD1_P | Default | r | 410.000 | |
ISNS_PPBUS_MAIN_SSD1_P | Default | v | 12.600 | |
ISNS_T139_N | Default | d | OL | |
ISNS_T139_P | Default | d | OL | |
ISNS_TBT_T_IOUT | Default | d | OL | |
ISNS_TBT_T_N | Default | d | OL | |
ISNS_TBT_T_P | Default | d | OL | |
ISNS_TBT_X_IOUT | Default | d | 0.363 | |
ISNS_TBT_X_N | Default | d | OL | |
ISNS_TBT_X_P | Default | d | OL | |
ISNS_VCCIO_IOUT | Default | d | OL | |
ISNS_WL1V8_IOUT | Default | d | OL | |
ISNS_WL1V8_N | Default | d | OL | |
ISNS_WL1V8_P | Default | d | OL | |
ISNS_WLAN_N | Default | d | OL | |
ISNS_WLAN_P | Default | d | OL | |
ISNS_WLAN_R_N | Default | d | OL | |
ISNS_WLAN_R_P | Default | d | OL | |
JTAG_ISP_TCK | Default | d | 0.570 | |
JTAG_ISP_TDI | Default | d | 0.569 | |
JTAG_ISP_TDO | Default | d | 0.570 | |
KBDBKLT_SW2 | Default | d | 0.403 | |
KBDBKLT_SW2 | Default | v | 5.100 | |
KBDLED_CATHODE1 | Default | d | 0.674 | |
KBDLED_CATHODE2 | Default | d | 0.668 | |
KBD_CAPSLOCK_LED | Default | d | 0.508 | |
KBD_CAP_CATHODE | Default | d | 0.529 | |
KBD_CONTROL_KEY | Default | d | 0.492 | |
KBD_CONTROL_L | Default | d | 0.461 | |
KBD_DRIVE_Y0 | Default | d | 0.515 | |
KBD_DRIVE_Y1 | Default | d | 0.525 | |
KBD_DRIVE_Y2 | Default | d | 0.525 | |
KBD_DRIVE_Y3 | Default | d | 0.527 | |
KBD_DRIVE_Y4 | Default | d | 0.515 | |
KBD_DRIVE_Y5 | Default | d | 0.514 | |
KBD_DRIVE_Y6 | Default | d | 0.500 | |
KBD_DRIVE_Y7 | Default | d | 0.500 | |
KBD_I2C_INT_L | Default | d | 0.676 | |
KBD_I2C_SCL | Default | d | 0.715 | |
KBD_I2C_SDA | Default | d | 0.683 | |
KBD_ID1 | Default | d | 0.800 | |
KBD_ID_DETECT1 | Default | d | 0.514 | |
KBD_ID_DETECT2 | Default | d | 0.469 | |
KBD_LEFT_OPTION_KEY | Default | d | 0.492 | |
KBD_LEFT_OPTION_L | Default | d | 0.460 | |
KBD_RIGHT_SHIFT_KEY | Default | d | 0.495 | |
KBD_RIGHT_SHIFT_L | Default | d | 0.461 | |
KBD_SENSE_X0 | Default | d | 0.532 | |
KBD_SENSE_X1 | Default | d | 0.536 | |
KBD_SENSE_X10 | Default | d | 0.538 | |
KBD_SENSE_X11 | Default | d | 0.535 | |
KBD_SENSE_X12 | Default | d | 0.535 | |
KBD_SENSE_X2 | Default | d | 0.536 | |
KBD_SENSE_X3 | Default | d | 0.544 | |
KBD_SENSE_X4 | Default | d | 0.556 | |
KBD_SENSE_X5 | Default | d | 0.529 | |
KBD_SENSE_X6 | Default | d | 0.513 | |
KBD_SENSE_X7 | Default | d | 0.511 | |
KBD_SENSE_X8 | Default | d | 0.510 | |
KBD_SENSE_X9 | Default | d | 0.510 | |
L83_FILT | Default | d | 0.801 | |
L83_FLYC | Default | d | 0.372 | |
L83_FLYN | Default | d | 0.450 | |
L83_FLYP | Default | d | 0.404 | |
L83_HSBIAS_FILT | Default | d | 0.716 | |
L83_HSBIAS_FILT_REF | Default | d | 0.628 | |
L83_SDOUT | Default | d | 0.498 | |
L83_VCP_FILTN | Default | d | 0.573 | |
L83_VCP_FILTP | Default | d | 0.387 | |
L83_VCP_FILT_GND | Default | d | 0.000 | |
LCDBKLT_EN_L | Default | d | OL | |
LCDBKLT_FB | Default | d | 0.732 | |
LCDBKLT_FET_DRV | Default | d | 0.508 | |
LCDBKLT_FET_DRV | Default | v | 1.100 | |
LCDBKLT_FET_DRV_R | Default | d | 0.520 | |
LCDBKLT_FET_DRV_R | Default | v | 1.100 | |
LCDBKLT_SW | Default | d | 0.439 | |
LCDBKLT_TB_XWR | Default | d | 1.181 | |
LCD_MUX_SEL | Default | d | 1.389 | |
LCD_PWR_SLEW | Default | d | 0.617 | |
LCD_PWR_SLEW_3V3 | Default | d | 0.632 | |
LDO_CORE | Default | d | 0.373 | |
LDO_RTC | Default | d | 0.373 | |
LID_CTRL_DMIC | Default | d | 0.700 | |
LID_OPEN_SMC_IN | Default | d | 0.491 | |
MEMVTT_EN | Default | d | 0.543 | |
MEMVTT_EN_R | Default | d | 0.543 | |
MEM_B_TEN_R | Default | d | 0.101 | |
MESA_BOOST_EN | Default | d | 0.553 | |
MESA_BOOST_EN_CONN | Default | d | 1.238 | |
MESA_INT | Default | d | 0.493 | |
MESA_INT_CONN | Default | d | 1.177 | |
MESA_PWR_EN | Default | d | 0.483 | |
MIPI_DFR_CLK_CONN_FILT_N | Default | d | 0.550 | |
MIPI_DFR_CLK_CONN_FILT_P | Default | d | 0.552 | |
MIPI_DFR_CLK_P | Default | d | 0.550 | |
MIPI_DFR_DATA_CONN_FILT_N | Default | d | 0.547 | |
MIPI_DFR_DATA_CONN_FILT_P | Default | d | 0.547 | |
MIPI_DFR_DATA_N | Default | d | 0.547 | |
MIPI_DFR_DATA_P | Default | d | 0.547 | |
MIPI_FTCAM_CLK_CONN_N | Default | d | 0.523 | |
MIPI_FTCAM_CLK_CONN_P | Default | d | 0.524 | |
MIPI_FTCAM_CLK_ISOL_N | Default | d | 0.523 | |
MIPI_FTCAM_CLK_ISOL_P | Default | d | 0.524 | |
MIPI_FTCAM_DATA_CONN_N<0> | Default | d | 0.524 | |
MIPI_FTCAM_DATA_CONN_P<0> | Default | d | 0.523 | |
MIPI_FTCAM_DATA_ISOL_N<0> | Default | d | 0.524 | |
MIPI_FTCAM_DATA_ISOL_P<0> | Default | d | 0.523 | |
MLBSNS_I2CLS_EN | Default | d | OL | |
MLB_RAMCFG1 | Default | d | 0.780 | |
NC | Default | d | - | |
NTC_A_CPUCORE | Default | d | 0.628 | |
NTC_A_CPUCORE_R | Default | d | OL | |
NTC_B_CPUGT | Default | d | 0.587 | |
NTC_B_CPUGT_R | Default | d | OL | |
OUT123_EN | Default | d | 0.302 | |
P0V8SLPDDR_FB | Default | d | 0.051 | |
P0V8SLPDDR_FB | Default | r | 50.100R | |
P0V8SLPDDR_FB_R | Default | d | 0.054 | |
P0V8SLPDDR_FB_R | Default | r | 53.100R | |
P0V8SLPDDR_SW0 | Default | d | 0.053 | |
P0V8SLPDDR_SW0 | Default | r | 52.800R | |
P0V8SLPDDR_SW1 | Default | d | 0.053 | |
P0V8SLPDDR_SW1 | Default | r | 52.800R | |
P0V9SLPDDR_SW0 | Default | d | 0.084 | |
P0V9SLPDDR_SW0 | Default | r | 85.100R | |
P0V9SLPDDR_SW1 | Default | d | 0.084 | |
P0V9SLPDDR_SW1 | Default | r | 85.100R | |
P0V9_LX0_SSD0 | Default | d | 0.401 | |
P0V9_LX0_SSD0 | Default | r | 398.000R | |
P0V9_LX0_SSD1 | Default | d | 0.468 | |
P0V9_LX0_SSD1 | Default | r | 462.000R | |
P0V9_LX1_SSD0 | Default | d | 0.401 | |
P0V9_LX1_SSD0 | Default | r | 398.000 | |
P0V9_LX1_SSD1 | Default | d | 0.468 | |
P0V9_LX1_SSD1 | Default | r | 462.000R | |
P0V9_SSD0_FB_DIS | Default | d | 0.392 | |
P0V9_SSD1_FB_DIS | Default | d | 0.483 | |
P0V9_TBT_T_SVR_AGND | Default | d | 0.000 | |
P0V9_TBT_X_SVR_AGND | Default | d | 0.000 | |
P1V1SLPDDR_RAMP | Default | d | 0.719 | |
P1V1SLPS2R_SW0 | Default | d | 0.287 | |
P1V1SLPS2R_SW0 | Default | r | 0.011R | |
P1V1SLPS2R_SW1 | Default | d | 0.287 | |
P1V1SLPS2R_SW1 | Default | r | 0.011R | |
P1V1_SLPDDR_SOCFET_EN | Default | d | 0.570 | |
P1V1_SLPDDR_SOCFET_EN_R | Default | d | OL | |
P1V2REG_AGND | Default | d | 0.000 | |
P1V2REG_MODE | Default | d | 0.545 | |
P1V2REG_TRIP | Default | d | 0.750 | |
P1V2REG_VREF | Default | d | 0.651 | |
P1V2REG_VREF_R | Default | d | OL | |
P1V2_BOOT_RC | Default | d | 0.630 | |
P1V2_DRVH | Default | d | 0.713 | |
P1V2_DRVH_R | Default | d | 0.714 | |
P1V2_DRVL | Default | d | 0.458 | |
P1V2_DRVL_R | Default | d | 0.458 | |
P1V2_LL_SNUB | Default | d | OL | |
P1V2_PHASE | Default | d | 0.223 | |
P1V2_SNS | Default | d | 0.235 | |
P1V2_SNS_R | Default | d | 0.225 | |
P1V2_SW | Default | d | 0.225 | |
P1V2_VBST | Default | d | 0.627 | |
P1V2_WLANBT_VLX | Default | d | 0.300 | |
P1V2_WLANBT_VLX | Default | r | 0.200R | |
P1V5_WLANBT_VLX | Default | d | 0.320 | |
P1V5_WLANBT_VLX | Default | r | 0.017R | |
P1V8G3S_EN | Default | v | 1.80 | |
P1V8GPU_EN | Default | d | 0.603 | |
P1V8GPU_FB | Default | d | 1.421 | |
P1V8GPU_FB_R | Default | d | 0.197 | |
P1V8GPU_PGOOD | Default | d | 0.595 | |
P1V8GPU_RA_R | Default | d | 0.197 | |
P1V8GPU_SSTR | Default | d | 0.544 | |
P1V8S5_VALID | Default | d | 0.542 | |
P1V8SLPS2R_SW0 | Default | d | 0.409 | |
P1V8SLPS2R_SW0 | Default | r | 0.003R | |
P1V8_G3S_EN_R | Default | d | OL | |
P1V8_LX0_SSD0 | Default | d | 0.379 | |
P1V8_LX0_SSD0 | Default | r | 0.090R | |
P1V8_LX0_SSD1 | Default | d | 0.425 | |
P1V8_LX0_SSD1 | Default | r | 0.128R | |
P1V8_SLPS2RSW_DFR_R | Default | d | 0.610 | |
P1V8_SSD0_FB_DIS | Default | d | 0.376 | |
P1V8_SSD1_FB_DIS | Default | d | 0.430 | |
P2V5S3_FSW | Default | d | 0.420 | |
P2V5S3_REG | Default | d | 0.420 | |
P2V5_SSD0_AGND | Default | d | 0.000 | |
P2V5_SSD1_AGND | Default | d | 0.000 | |
P2V5_SW1_TPS62180_SSD0 | Default | d | 0.408 | |
P2V5_SW1_TPS62180_SSD0 | Default | r | 0.150R | |
P2V5_SW1_TPS62180_SSD1 | Default | d | 0.429 | |
P2V5_SW1_TPS62180_SSD1 | Default | r | 0.175R | |
P2V5_SW2_TPS62180_SSD0 | Default | d | 0.408 | |
P2V5_SW2_TPS62180_SSD0 | Default | r | 0.150R | |
P2V5_SW2_TPS62180_SSD1 | Default | d | 0.429 | |
P2V5_SW2_TPS62180_SSD1 | Default | r | 0.175R | |
P2V5_VPP_PGOOD | Default | d | 0.497 | |
P3V3G3HRTC_FB | Default | d | 1.423 | |
P3V3G3HRTC_FB_R | Default | d | 0.430 | |
P3V3G3HRTC_PGOOD | Default | d | 0.697 | |
P3V3G3HRTC_PHASE1 | Default | d | 0.421 | |
P3V3G3HRTC_PHASE1 | Default | v | 3.300 | |
P3V3G3HRTC_PHASE2 | Default | d | 0.421 | |
P3V3G3HRTC_PHASE2 | Default | v | 3.300 | |
P3V3G3HRTC_RA_R | Default | d | 0.430 | |
P3V3G3HRTC_SS | Default | d | 0.542 | |
P3V3G3H_COMP2 | Default | d | 0.747 | |
P3V3G3H_CSN2 | Default | d | 0.377 | |
P3V3G3H_CSP2 | Default | d | 1.268 | |
P3V3G3H_DRVH | Default | d | 0.934 | |
P3V3G3H_DRVL | Default | d | 0.558 | |
P3V3G3H_EN | Default | d | 0.592 | |
P3V3G3H_RF | Default | d | 0.590 | |
P3V3G3H_SNUBR | Default | d | OL | |
P3V3G3H_SW | Default | d | 0.376 | |
P3V3G3H_TG | Default | d | 0.933 | |
P3V3G3H_VBST | Default | d | 0.628 | |
P3V3G3H_VBST_R | Default | d | 0.628 | |
P3V3G3H_VFB2 | Default | d | 0.593 | |
P3V3G3H_VFB2_R | Default | d | 0.377 | |
P3V3G3H_VFB2_RR | Default | d | 1.304 | |
P3V3G3H_VSW | Default | d | 0.377 | |
P3V3G3ST_SS | Default | d | 0.635 | |
P3V3G3SX_SS | Default | d | 0.639 | |
P3V3G3S_EN | Default | d | 0.539 | |
P3V3GPU_EN | Default | d | 0.504 | |
P3V3GPU_RAMP | Default | d | 0.716 | |
P3V3MAIN_PGOOD | Default | d | 0.585 | |
P3V3S5_COMP2_R | Default | d | OL | |
P3V3TBTT_CMP | Default | d | 0.499 | |
P3V3TBTT_RAMP | Default | d | 0.620 | |
P3V3TBTX_CMP | Default | d | 0.500 | |
P3V3TBTX_RAMP | Default | d | 0.616 | |
P3V3_G3H_RTC_DEBUG_LED_R | Default | d | OL | |
P3V3_S0GPU_PGOOD | Default | d | 0.610 | |
P5VG3S_COMP1 | Default | d | 0.748 | |
P5VG3S_CSN1 | Default | d | 0.401 | |
P5VG3S_CSP1 | Default | d | 0.990 | |
P5VG3S_CSP1_R | Default | d | 0.402 | |
P5VG3S_DRVH | Default | d | 0.960 | |
P5VG3S_EN | Default | d | 0.591 | |
P5VG3S_EN_R | Default | d | 0.591 | |
P5VG3S_EN_R | Default | v | 3.30 | |
P5VG3S_PGOOD | Default | v | 1.80 | |
P5VG3S_SNUBR | Default | d | OL | |
P5VG3S_SW | Default | d | 0.401 | |
P5VG3S_TG | Default | d | 0.961 | |
P5VG3S_VBST | Default | d | 0.630 | |
P5VG3S_VBST_R | Default | d | 0.630 | |
P5VG3S_VFB1 | Default | d | 0.582 | |
P5VG3S_VFB1_R | Default | d | 0.401 | |
P5VG3S_VSW | Default | d | 0.401 | |
P5VG3S_VSW | Default | v | 5.00 | |
P5VP3V3_SKIPSEL | Default | d | 0.470 | |
P5VP3V3_VREF2 | Default | d | 0.487 | |
P5VP3V3_VREG3 | Default | d | 0.517 | |
P5VS4_COMP1_R | Default | d | OL | |
P5VUSBCT_AGND | Default | d | 0.000 | |
P5VUSBCT_BOOT_RC | Default | d | 0.608 | |
P5VUSBCT_DRVH | Default | d | 0.665 | |
P5VUSBCT_DRVH_R | Default | d | 0.665 | |
P5VUSBCT_FSEL | Default | d | 0.566 | |
P5VUSBCT_LL | Default | d | 0.197 | |
P5VUSBCT_LL | Default | r | 0.001R | |
P5VUSBCT_N | Default | d | 0.193 | |
P5VUSBCT_OCSET | Default | d | 0.558 | |
P5VUSBCT_P | Default | d | 0.193 | |
P5VUSBCT_R | Default | d | 0.193 | |
P5VUSBCT_R | Default | r | 0.001R | |
P5VUSBCT_RTN_DIV | Default | d | 0.562 | |
P5VUSBCT_RTN_DIV_R | Default | d | 0.000 | |
P5VUSBCT_SENSE_DIV | Default | d | 0.560 | |
P5VUSBCT_SENSE_DIV_R | Default | d | 0.195 | |
P5VUSBCT_SET0 | Default | d | 0.565 | |
P5VUSBCT_SET1 | Default | d | 0.563 | |
P5VUSBCT_SET_R | Default | d | OL | |
P5VUSBCT_SREF | Default | d | 0.563 | |
P5VUSBCT_VBST | Default | d | 0.607 | |
P5VUSBCT_VO | Default | d | 0.558 | |
P5VUSBC_X_AGND | Default | d | 0.000 | |
P5VUSBC_X_BOOT_RC | Default | d | 0.605 | |
P5VUSBC_X_DRVH | Default | d | 0.683 | |
P5VUSBC_X_DRVH_R | Default | d | 0.683 | |
P5VUSBC_X_FSEL | Default | d | 0.565 | |
P5VUSBC_X_LL | Default | d | 0.485 | |
P5VUSBC_X_LL | Default | r | - | |
P5VUSBC_X_NEG | Default | d | 0.188 | |
P5VUSBC_X_OCSET | Default | d | 0.556 | |
P5VUSBC_X_PGOOD | Default | d | 0.563 | |
P5VUSBC_X_POS | Default | d | 0.188 | |
P5VUSBC_X_R | Default | d | 0.485 | |
P5VUSBC_X_R | Default | r | 186.000 | |
P5VUSBC_X_RTN_DIV | Default | d | 0.559 | |
P5VUSBC_X_RTN_DIV_XW | Default | d | 0.003 | |
P5VUSBC_X_RTN_DIV_XW | Default | r | 1.600R | |
P5VUSBC_X_SENSE_DIV | Default | d | 0.557 | |
P5VUSBC_X_SET0 | Default | d | 0.530 | |
P5VUSBC_X_SET1 | Default | d | 0.562 | |
P5VUSBC_X_SET_R | Default | d | OL | |
P5VUSBC_X_SREF | Default | d | 0.560 | |
P5VUSBC_X_VBST | Default | d | 0.607 | |
P5V_3V3G3H_EN | Default | d | 0.592 | |
PANEL_P3V3_EN | Default | d | 0.489 | |
PANEL_P3V3_EN_D | Default | d | 0.701 | |
PANEL_P5V_EN | Default | d | 0.569 | |
PANEL_P5V_EN_D | Default | d | 1.039 | |
PBUSVSENS_EN_L | Default | d | 0.488 | |
PBUSVSENS_EN_L_DIV | Default | d | OL | |
PBUS_DIVIDER | Default | d | 0.706 | |
PBUS_DIVIDER_OUT | Default | d | 0.655 | |
PBUS_DIVIDER_REF | Default | d | 0.660 | |
PBUS_S0_VSENSE | Default | d | OL | |
PBUS_S0_VSENSE_IN | Default | d | 0.415 | |
PCC_EVENT | Default | d | 0.494 | |
PCC_GFXGPU_SUM | Default | d | 0.468 | |
PCH_BT_ROM_BOOT_L | Default | d | 0.539 | |
PCH_CLK24M_XTALIN | Default | d | 0.838 | |
PCH_CLK24M_XTALOUT_R | Default | d | 0.835 | |
PCH_CLK32K_RTCX1 | Default | d | 0.862 | |
PCH_GPPJ_RCOMP_1P8 | Default | d | 0.204 | |
PCH_PCIE_CLK100M_WLAN_N | Default | d | 0.312 | |
PCH_PCIE_CLK100M_WLAN_P | Default | d | 0.311 | |
PCH_PCIE_RCOMPN | Default | d | 0.296 | |
PCH_PCIE_RCOMPP | Default | d | 0.296 | |
PCH_PMTHRMTRIP_L | Default | d | 0.555 | |
PCH_PMTHRMTRIP_L_R | Default | d | 0.553 | |
PCH_RTC_RESET_L | Default | d | 0.771 | |
PCH_RTC_RESET_L | Default | v | 3.00 | |
PCH_STRP_ESPI | Default | d | 0.808 | |
PCH_STRP_GPP_H15 | Default | d | 0.830 | |
PCH_UART_BT_CTS_L | Default | d | 0.499 | |
PCH_UART_BT_RTS_L | Default | d | 0.455 | |
PCH_UART_DEBUG_D2R | Default | d | 0.709 | |
PCH_UART_DEBUG_R2D | Default | d | 0.707 | |
PCH_WLANBT_PERST_L | Default | d | 0.826 | |
PCIE_SSD0_D2R_C_N<3> | Default | d | 0.360 | |
PCIE_SSD0_D2R_C_P<3> | Default | d | 0.325 | |
PCIE_SSD0_D2R_N<3> | Default | d | 0.435 | |
PCIE_SSD0_D2R_P<3> | Default | d | 0.433 | |
PCIE_SSD0_R2D_C_N<3> | Default | d | 0.373 | |
PCIE_SSD0_R2D_C_P<3> | Default | d | 0.373 | |
PCIE_SSD0_R2D_N<3> | Default | d | 0.442 | |
PCIE_SSD0_R2D_P<3> | Default | d | 0.440 | |
PDM_DMIC_DATA0 | Default | d | 0.403 | |
PDM_DMIC_DATA0_RR | Default | d | 0.494 | |
PDM_DMIC_DATA1 | Default | d | 0.477 | |
PDM_DMIC_DATA1_RR | Default | d | 0.487 | |
PLT3V3_RST_L | Default | d | 0.634 | |
PLT_RST_L | Default | d | 0.396 | |
PMU_3V3_T_HI_ISENSE | Default | d | 0.586 | |
PMU_3V3_X_HI_ISENSE | Default | d | 0.589 | |
PMU_ACTIVE_READY | Default | d | 0.469 | |
PMU_ACTIVE_READY_R | Default | d | OL | |
PMU_CLK32K_PCH | Default | d | 0.810 | |
PMU_CLK32K_SOC | Default | d | 0.496 | |
PMU_CLK32K_SOC_R | Default | d | 0.530 | |
PMU_CLK32K_WLANBT_R | Default | d | 0.485 | |
PMU_COLD_RESET_L | Default | d | 0.490 | |
PMU_CPUDDR_ISENSE | Default | d | 0.590 | |
PMU_CPU_ISENSE | Default | d | 0.591 | |
PMU_CPU_VSENSE | Default | d | 0.584 | |
PMU_DDR1V2_ISENSE | Default | d | 0.586 | |
PMU_DROOP_L | Default | d | 0.495 | |
PMU_FORCE_DFU | Default | d | 0.769 | |
PMU_GPU_GFX_ISENSE | Default | d | 0.590 | |
PMU_GPU_GFX_VSENSE | Default | d | 0.584 | |
PMU_GPU_SOC_ISENSE | Default | d | 0.589 | |
PMU_GPU_SOC_VSENSE | Default | d | 0.589 | |
PMU_IREF | Default | d | 0.761 | |
PMU_LDO3_OUT_R | Default | d | 0.601 | |
PMU_ONOFF_L | Default | d | 0.590 | |
PMU_ONOFF_R_L | Default | d | 0.585 | |
PMU_ONOFF_R_L_CONN | Default | d | 0.586 | |
PMU_OTHER5V_HI_ISENSE | Default | d | 0.588 | |
PMU_P1V8_WLAN_ISENSE | Default | d | 0.590 | |
PMU_P3V3_G3W_SSD0_ISENSE | Default | d | 0.557 | |
PMU_P3V3_G3W_SSD1_ISENSE | Default | d | 0.588 | |
PMU_PBUS_MAIN_SSD0_ISENSE | Default | d | 0.586 | |
PMU_PBUS_MAIN_SSD1_ISENSE | Default | d | 0.588 | |
PMU_PVDDMAIN_EN | Default | d | 0.773 | |
PMU_RSLOC_RST_L | Default | d | 0.522 | |
PMU_SYS_ALIVE | Default | d | 0.435 | |
PMU_VDD_HI | Default | d | 0.660 | |
PMU_VDD_MAX | Default | d | 0.560 | |
PMU_VPUMP | Default | d | 0.591 | |
PMU_VREF | Default | d | 0.002 | |
PMU_XTAL1 | Default | d | 0.796 | |
PMU_XTAL1_R | Default | d | 0.796 | |
PMU_XTAL2 | Default | d | 0.796 | |
PM_ALL_GPU_PGOOD | Default | d | 0.457 | |
PM_MEMVTT_EN | Default | d | 0.376 | |
PM_PCH_PWROK | Default | d | 0.497 | |
PM_PCH_SYS_PWROK | Default | d | 0.547 | |
PM_PWRBTN_L | Default | d | 0.762 | |
PM_RSMRST_L | Default | d | 0.528 | |
PM_SLP_S0_L | Default | d | 0.491 | |
PM_SLP_S0_R_L | Default | d | OL | |
PM_SLP_S3_L | Default | d | 0.564 | |
PM_SLP_S4_L | Default | d | 0.815 | |
PM_SLP_S5_L | Default | d | 0.815 | |
PM_SLP_TIEOFF | Default | d | 0.719 | |
PM_SYSRST_L | Default | d | 0.810 | |
PM_SYSRST_R_L | Default | d | 0.553 | |
PM_THRMTRIP_L | Default | d | 0.258 | |
PP0V6_S0_DDRVTT | Default | d | 0.132 | |
PP0V75_S0_GPU | Default | r | 49.300R | |
PP0V82_SLPDDR | Default | d | 0.053 | |
PP0V82_SLPDDR | Default | r | 52.800R | |
PP0V85_MEMCI_S0_GPU | Default | d | 0.089 | |
PP0V85_MEMCI_S0_GPU | Default | r | 88.400R | |
PP0V8_SLPS2R | Default | d | 0.253 | |
PP0V95_S0_CPUVCCIO_REG_R | Default | d | 0.076 | |
PP0V95_S0_CPUVCCIO_REG_R | Default | r | 83.200R | |
PP0V9_SLPDDR | Default | d | 0.084 | |
PP0V9_SLPDDR | Default | r | 85.100R | |
PP0V9_SLPDDR_SOC_PCIEREFBUF | Default | d | 0.085 | |
PP0V9_SLPDDR_SOC_PCIEREFBUF | Default | r | 83.400R | |
PP0V9_SSD0 | Default | d | 0.401 | |
PP0V9_SSD0 | Default | r | 398.000 | |
PP0V9_SSD1 | Default | d | 0.468 | |
PP0V9_SSD1 | Default | r | 462.000 | |
PP0V9_TBT_T_LC | Default | d | 0.347 | |
PP0V9_TBT_T_LVR | Default | d | 0.460 | |
PP0V9_TBT_T_PCIE | Default | d | 0.316 | |
PP0V9_TBT_T_SVR | Default | d | 0.288 | |
PP0V9_TBT_T_SVR | Default | r | 286.000 | |
PP0V9_TBT_X_LVR | Default | d | 0.478 | |
PP0V9_TBT_X_PCIE | Default | d | 0.324 | |
PP0V9_TBT_X_SVR | Default | d | 0.320 | |
PP0V9_TBT_X_SVR | Default | r | 312.000R | |
PP16V0_MESA | Default | d | 0.655 | |
PP16V0_MESA_FILT_CONN | Default | d | 0.656 | |
PP17V0_MOJAVE_LDOIN | Default | d | 0.596 | |
PP1V05_PRIM | Default | d | 0.096 | |
PP1V05_PRIM | Default | r | 94.000R | |
PP1V05_PRIM_PCH_VCCAPLL_F | Default | d | 0.096 | |
PP1V05_PRIM_PCH_VCCAXTAL_F | Default | d | 0.096 | |
PP1V05_PRIM_PCH_VCCAXTAL_F | Default | r | 94.800R | |
PP1V05_S0SW | Default | d | 0.208 | |
PP1V05_S3 | Default | d | 0.219 | |
PP1V1_SLPDDR | Default | d | 0.388 | |
PP1V1_SLPDDR_SOC_VDDIOPLLDDR_F | Default | d | 0.388 | |
PP1V1_SLPDDR_SOC_XTAL_F | Default | d | 0.388 | |
PP1V1_SLPS2R | Default | d | 0.287 | |
PP1V1_SLPS2R | Default | r | 0.011R | |
PP1V24_S5_PCH_VCCDPHY | Default | d | 0.428 | |
PP1V25_SLPS2R_SMC_AVREF | Default | d | 0.616 | |
PP1V2_AWAKE | Default | d | 0.525 | |
PP1V2_AWAKE_SOC_PCIEPLL_F | Default | d | 0.525 | |
PP1V2_AWAKE_SOC_PCIEREFBUF_F | Default | d | 0.000 | |
PP1V2_AWAKE_SOC_PLLCPU_F | Default | d | 0.522 | |
PP1V2_AWAKE_SOC_PLLSOC_F | Default | d | 0.523 | |
PP1V2_S0SW | Default | d | 0.303 | |
PP1V2_S3 | Default | d | 0.223 | |
PP1V2_S3 | Default | r | 221.000 | |
PP1V2_S3_CPUDDR | Default | d | 0.228 | |
PP1V2_S3_CPUDDR | Default | r | 226.000R | |
PP1V2_S3_REG_R | Default | d | 0.223 | |
PP1V2_S3_REG_R | Default | r | 221.000 | |
PP1V2_WLANBT | Default | d | 0.299 | |
PP1V2_WLANBT_C | Default | d | 0.300 | |
PP1V2_WLANBT_C | Default | r | 0.200R | |
PP1V35_MEMIO_S0_GPU | Default | d | 0.048 | |
PP1V35_MEMIO_S0_GPU | Default | r | 46.600R | |
PP1V5_UPC_TA_LDO_CORE | Default | d | 0.501 | |
PP1V5_UPC_TB_LDO_CORE | Default | d | 0.501 | |
PP1V5_UPC_XA_LDO_CORE | Default | d | 0.501 | |
PP1V5_UPC_XB_LDO_CORE | Default | d | 0.504 | |
PP1V5_WLANBT | Default | d | 0.327 | |
PP1V5_WLANBT_C | Default | d | 0.320 | |
PP1V5_WLANBT_C | Default | r | 0.017R | |
PP1V8_AUDIO | Default | d | 0.300 | |
PP1V8_AWAKE | Default | d | 0.422 | |
PP1V8_DMIC | Default | d | 0.305 | |
PP1V8_G3S | Default | d | 0.301 | |
PP1V8_G3S | Default | t | ok | |
PP1V8_G3S | Default | v | 1.80 | |
PP1V8_G3S_TPAD_CONN | Default | d | 0.544 | |
PP1V8_G3S_WLANBT | Default | d | 0.301 | |
PP1V8_L83_VA | Default | d | 0.300 | |
PP1V8_L83_VCP | Default | d | 0.300 | |
PP1V8_L83_VL | Default | d | 0.300 | |
PP1V8_MESA | Default | d | 0.521 | |
PP1V8_MESA_FILT_CONN | Default | d | 0.521 | |
PP1V8_PCH_VCCPHYLDO | Default | d | 0.658 | |
PP1V8_S0_GPU | Default | d | 0.190 | |
PP1V8_S0_GPU_CONN | Default | d | OL | |
PP1V8_S0_GPU_REG | Default | d | 0.200 | |
PP1V8_S0_GPU_REG | Default | r | 0.001R | |
PP1V8_S0_PCH_VCCHDA_F | Default | d | 0.363 | |
PP1V8_S0_PCH_VCCHDA_F | Default | r | 0.019R | |
PP1V8_S5 | Default | d | 0.363 | |
PP1V8_S5 | Default | r | 0.019R | |
PP1V8_S5_GPIOX_R | Default | d | 0.364 | |
PP1V8_S5_TBTTHMSNS_T_R | Default | d | 0.410 | |
PP1V8_S5_TBTTHMSNS_X_R | Default | d | 0.410 | |
PP1V8_SLPS2R | Default | d | 0.409 | |
PP1V8_SLPS2R | Default | r | 0.003R | |
PP1V8_SLPS2RSW_DFR | Default | d | 0.535 | |
PP1V8_SLPS2R_PMUVDDGPIO | Default | d | 0.739 | |
PP1V8_SLPS2R_SOC_LPADC_RC | Default | d | 0.453 | |
PP1V8_SLPS2R_SOC_LPOSC_RC | Default | d | 0.458 | |
PP1V8_SSD0 | Default | d | 0.379 | |
PP1V8_SSD0 | Default | r | 0.090R | |
PP1V8_SSD0_S4E1_AVDD18_PLL | Default | d | 0.375 | |
PP1V8_SSD0_S4E1_PCI_AVDD_H | Default | d | 0.375 | |
PP1V8_SSD1 | Default | d | 0.425 | |
PP1V8_SSD1 | Default | r | 0.128R | |
PP1V_PRIM_PCH_VCCAMPHYPLL_F | Default | d | 0.096 | |
PP1V_PRIM_PCH_VCCAMPHYPLL_F | Default | r | 94.000R | |
PP2V5_NAND_SSD0 | Default | d | 0.408 | |
PP2V5_NAND_SSD0 | Default | r | 0.150R | |
PP2V5_NAND_SSD1 | Default | d | 0.429 | |
PP2V5_NAND_SSD1 | Default | r | 0.175R | |
PP2V5_S3 | Default | d | 0.420 | |
PP3V0_G3H_RTC | Default | d | 0.461 | |
PP3V0_MESA | Default | d | 0.551 | |
PP3V0_MESA_FILT_CONN | Default | d | 0.551 | |
PP3V3_AWAKE | Default | d | 0.645 | |
PP3V3_G3HSW_DFR | Default | d | 0.568 | |
PP3V3_G3H_DFR | Default | d | 0.420 | |
PP3V3_G3H_MESA_SW | Default | d | 0.377 | |
PP3V3_G3H_PMU_VINRTC_R | Default | d | 0.421 | |
PP3V3_G3H_RSLOC | Default | d | 0.383 | |
PP3V3_G3H_RTC_REG_R | Default | d | 0.421 | |
PP3V3_G3H_RTC_REG_R | Default | v | 3.300 | |
PP3V3_G3H_RTC_X | Default | d | 0.421 | |
PP3V3_G3H_SOCPMU | Default | d | 0.378 | |
PP3V3_G3H_SOCPMU | Default | v | 3.300 | |
PP3V3_G3H_SSD0_SNS | Default | d | 0.421 | |
PP3V3_G3H_SSD1_SNS | Default | d | 0.377 | |
PP3V3_G3H_T | Default | d | 0.378 | |
PP3V3_G3SSW_SNS | Default | d | 0.494 | |
PP3V3_G3S_T | Default | d | 0.428 | |
PP3V3_G3S_WLAN | Default | d | 0.349 | |
PP3V3_G3S_X | Default | d | 0.349 | |
PP3V3_L83_VP | Default | d | 0.377 | |
PP3V3_S0SW_LCD | Default | d | 0.484 | |
PP3V3_S0SW_LCD | Default | v | 3.300 | |
PP3V3_S0SW_LCD_R | Default | d | 0.485 | |
PP3V3_S0SW_TBT_T | Default | d | 0.537 | |
PP3V3_S0SW_TBT_T_SNS | Default | d | 0.535 | |
PP3V3_S0SW_TBT_X | Default | d | 0.532 | |
PP3V3_S0SW_TBT_X_SNS | Default | d | 0.532 | |
PP3V3_S0_GPU | Default | d | 0.416 | |
PP3V3_S5 | Default | d | 0.335 | |
PP3V3_S5_GPIOX_R | Default | d | 0.335 | |
PP3V3_TBT_T_ANA | Default | d | 0.537 | |
PP3V3_TBT_T_ANA_PCIE | Default | d | 0.490 | |
PP3V3_TBT_T_F | Default | d | 0.506 | |
PP3V3_TBT_T_LC | Default | d | 0.554 | |
PP3V3_TBT_T_SX | Default | d | 0.481 | |
PP3V3_TBT_X_ANA | Default | d | 0.537 | |
PP3V3_TBT_X_ANA_PCIE | Default | d | 0.503 | |
PP3V3_TBT_X_ANA_USB2 | Default | d | 0.508 | |
PP3V3_TBT_X_F | Default | d | 0.517 | |
PP3V3_TBT_X_LC | Default | d | 0.559 | |
PP3V3_TBT_X_SX | Default | d | 0.486 | |
PP3V3_UPC_TA_LDO | Default | d | 0.475 | |
PP3V3_UPC_TB_LDO | Default | d | 0.490 | |
PP3V3_UPC_XA_LDO | Default | d | 0.493 | |
PP3V3_UPC_XB_LDO | Default | d | 0.483 | |
PP5V_COREVR_VCC | Default | d | 0.405 | |
PP5V_EADC1_AVDD | Default | d | OL | |
PP5V_EADC2_AVDD | Default | d | OL | |
PP5V_EDRAM_V5IN | Default | d | 0.403 | |
PP5V_G3S | Default | d | 0.405 | |
PP5V_G3S | Default | v | 5.000 | |
PP5V_G3S_BKLT_A | Default | d | 0.413 | |
PP5V_G3S_BKLT_A | Default | v | 5.100 | |
PP5V_G3S_BKLT_D | Default | d | 0.413 | |
PP5V_G3S_BKLT_D | Default | v | 5.100 | |
PP5V_G3S_DFR_FILT | Default | d | 0.405 | |
PP5V_G3S_GPU_COREREG_VDD | Default | d | 0.404 | |
PP5V_G3S_GPU_VDD075REG_R | Default | d | 0.405 | |
PP5V_G3S_ISNS_D | Default | d | OL | |
PP5V_G3S_KBDLED | Default | d | 0.403 | |
PP5V_G3S_KBDLED | Default | v | 5.100 | |
PP5V_G3S_TPAD_CONN | Default | d | 0.403 | |
PP5V_G3S_VCCIOVCC | Default | d | 0.403 | |
PP5V_S0SW_LCD | Default | d | 0.570 | |
PP5V_S0SW_LCD | Default | v | 5.000 | |
PP5V_S0_ALSCAM_F | Default | d | 0.404 | |
PP5V_S0_ALSCAM_F | Default | v | 5.000 | |
PP5V_S4_T_USBC | Default | d | 0.193 | |
PP5V_S4_X_USBC | Default | d | 0.188 | |
PP5V_S4_X_USBC | Default | r | 186.000 | |
PP5V_S5_LDO | Default | d | 0.485 | |
PP5V_USBCT_VCC | Default | d | 0.406 | |
PP5V_USBC_X_VCC | Default | d | 0.405 | |
PPBUS_G3H | Default | d | 0.415 | |
PPBUS_G3H | Default | r | 410.000 | |
PPBUS_G3H | Default | v | 12.600 | |
PPBUS_G3H_SPKRAMPL | Default | d | 0.414 | |
PPBUS_G3H_SSD0_SNS | Default | d | 0.415 | |
PPBUS_G3H_SSD0_SNS | Default | r | 410.000 | |
PPBUS_G3H_SSD0_SNS | Default | v | 12.600 | |
PPBUS_G3H_SSD1_SNS | Default | d | 0.415 | |
PPBUS_G3H_SSD1_SNS | Default | r | 410.000 | |
PPBUS_G3H_SSD1_SNS | Default | v | 12.600 | |
PPBUS_HS_3V3G3HRTC_X | Default | d | 0.415 | |
PPBUS_HS_3V3G3HRTC_X | Default | r | 410.000 | |
PPBUS_HS_3V3G3H_T | Default | d | 0.415 | |
PPBUS_HS_3V3G3H_T | Default | r | 410.000 | |
PPBUS_HS_3V3G3H_T | Default | v | 12.600 | |
PPBUS_HS_CPU | Default | d | 0.415 | |
PPBUS_HS_CPU | Default | r | 410.000 | |
PPBUS_HS_CPU | Default | v | 12.600 | |
PPBUS_HS_GPU | Default | d | 0.415 | |
PPBUS_HS_GPU | Default | r | 409.000R | |
PPBUS_HS_OTH5V | Default | d | 0.415 | |
PPBUS_HS_OTH5V | Default | r | 0.200R | |
PPBUS_HS_OTH5V | Default | v | 12.600 | |
PPDCIN_G3H | Default | d | 0.552 | |
PPDCIN_G3H_CHGR | Default | d | 0.552 | |
PPDCIN_TA_G3H_F | Default | d | 0.533 | |
PPDCIN_TB_G3H_F | Default | d | 0.533 | |
PPDCIN_XA_G3H_F | Default | d | 0.553 | |
PPDCIN_XB_G3H_F | Default | d | 0.533 | |
PPGFX_S0_GPU | Default | d | 0.016 | |
PPGFX_S0_GPU | Default | r | 14.800R | |
PPGFX_S0_GPU_R1 | Default | d | 0.016 | |
PPGFX_S0_GPU_R2 | Default | d | 0.016 | |
PPGFX_S0_GPU_R3 | Default | d | 0.016 | |
PPGFX_S0_GPU_R4 | Default | d | 0.016 | |
PPGFX_S0_GPU_SW1 | Default | d | 0.016 | |
PPGFX_S0_GPU_SW2 | Default | d | 0.016 | |
PPGFX_S0_GPU_SW3 | Default | d | 0.016 | |
PPGFX_S0_GPU_SW4 | Default | d | 0.016 | |
PPSOC_S0_GPU | Default | d | 0.007 | |
PPSOC_S0_GPU_R | Default | d | 0.007 | |
PPSOC_S0_GPU_R | Default | r | 7.400R | |
PPSOC_S0_GPU_SW | Default | d | 0.007 | |
PPVBAT_G3H_CHGR_R | Default | d | 0.415 | |
PPVBAT_G3H_CHGR_R | Default | r | 410.000 | |
PPVBAT_G3H_CHGR_REG | Default | d | 0.415 | |
PPVBAT_G3H_CHGR_REG | Default | r | 410.000 | |
PPVBAT_G3H_CHGR_REG | Default | v | 12.600 | |
PPVBAT_G3H_CONN | Default | d | 1.569 | |
PPVBAT_G3H_CONN | Default | t | Won't Boot without Battery, thereabout 20V 0.03A | |
PPVBUS_USBC_TA | Default | d | 0.141 | |
PPVBUS_USBC_TA | Default | t | Won't Boot without Battery, thereabout 20V 0.03A | |
PPVBUS_USBC_TB | Default | d | 0.141 | |
PPVBUS_USBC_TB | Default | t | Won't Boot without Battery, thereabout 20V 0.03A | |
PPVBUS_USBC_XA | Default | d | 0.144 | |
PPVBUS_USBC_XA | Default | t | Won't Boot without Battery, thereabout 20V 0.03A | |
PPVBUS_USBC_XB | Default | d | 0.144 | |
PPVBUS_USBC_XB | Default | t | Won't Boot without Battery, thereabout 20V 0.03A | |
PPVCCGT_CPU_PH1 | Default | d | 0.010 | |
PPVCCGT_CPU_PH2 | Default | d | 0.010 | |
PPVCCGT_S0_CPU | Default | d | 0.010 | |
PPVCCGT_S0_CPU | Default | r | 9.500R | |
PPVCCIO_S0_CPU | Default | d | 0.076 | |
PPVCCIO_S0_CPU | Default | r | 83.200R | |
PPVCCPRIMCORE_PRIM_REG | Default | d | 0.109 | |
PPVCCPRIMCORE_PRIM_REG | Default | r | 107.400R | |
PPVCCPRIM_FETIN | Default | d | 0.107 | |
PPVCCSA_CPU_R | Default | d | 0.033 | |
PPVCCSA_S0_CPU | Default | d | 0.033 | |
PPVCCSA_S0_CPU | Default | r | 21.400R | |
PPVCCSPI_PRIM_PCH | Default | d | 0.335 | |
PPVCC_CPU_PH1 | Default | d | 0.002 | |
PPVCC_CPU_PH2 | Default | d | 0.002 | |
PPVCC_CPU_PH3 | Default | d | 0.002 | |
PPVCC_S0_CPU | Default | d | 0.002 | |
PPVCC_S0_CPU | Default | r | 2.400R | |
PPVDD075_GPU_R | Default | d | 0.050 | |
PPVDD075_GPU_R | Default | r | 49.300R | |
PPVDDCIMEM_GPU_R | Default | d | 0.089 | |
PPVDDCPUSRAM_AWAKE | Default | d | 0.355 | |
PPVDDCPUSRAM_AWAKE | Default | r | 353.000 | |
PPVDDCPU_AWAKE | Default | d | 0.032 | |
PPVDDCPU_AWAKE | Default | r | 31.900R | |
PPVDDIOMEM_GPU_R1 | Default | d | 0.048 | |
PPVDDIOMEM_GPU_R2 | Default | d | 0.048 | |
PPVIN_G3H_P3V3G3HRTC_R | Default | d | 0.415 | |
PPVIN_GPU_COREREG_VIN | Default | d | 0.414 | |
PPVIN_RFLDO_WLANBT | Default | d | 0.498 | |
PPVIN_RFLDO_WLANBT_C | Default | d | 0.328 | |
PPVIN_RFLDO_WLANBT_C | Default | r | 0.100R | |
PPVIN_S0SW_LCDBKLT | Default | d | 0.833 | |
PPVIN_S0SW_LCDBKLT | Default | v | 11.880 | |
PPVIN_S0SW_LCDBKLT_FET | Default | d | 0.415 | |
PPVIN_S0SW_LCDBKLT_FET | Default | r | 410.000 | |
PPVIN_S0SW_LCDBKLT_FET | Default | v | 12.600 | |
PPVIN_S0SW_LCDBKLT_R | Default | d | 0.415 | |
PPVIN_S0_CPUVR_VIN | Default | d | 0.422 | |
PPVIN_S3_DDR2V5_RC | Default | d | 0.420 | |
PPVIN_SW_LCDBKLT_SW | Default | d | 0.833 | |
PPVIN_SW_LCDBKLT_SW | Default | r | 0.512R | |
PPVIN_SW_LCDBKLT_SW | Default | v | 11.900 | |
PPVOUT_S0_KBDLED | Default | d | 0.601 | |
PPVOUT_S0_KBDLED_R | Default | d | 0.608 | |
PPVOUT_S0_KBDLED_R | Default | v | 5.100 | |
PPVOUT_S0_LCDBKLT | Default | d | 1.148 | |
PPVOUT_S0_LCDBKLT | Default | v | 55.000 | |
PPVOUT_S0_LCDBKLT_F | Default | d | 1.181 | |
PPVOUT_S0_LCDBKLT_F | Default | r | 0.177R | |
PPVOUT_S0_LCDBKLT_F | Default | v | 48.800 | |
PPVTT_VTTREF | Default | d | 0.501 | |
PP_VDD_SE_VDDA | Default | d | 0.336 | |
PP_VDD_SE_VDDC | Default | d | 0.342 | |
PP_VDD_SE_VDDNV | Default | d | 0.367 | |
PP_VDD_SE_VDDPLL | Default | d | 0.365 | |
PP_VDD_SE_VHV | Default | d | 0.323 | |
PP_VDD_SE_VREF | Default | d | 0.696 | |
PROG1_CPUCOREVR | Default | d | 0.618 | |
PROG2_CPUCOREVR | Default | d | 0.619 | |
PROG3_CPUCOREVR | Default | d | 0.600 | |
PROG4_CPUCOREVR | Default | d | 0.627 | |
PROG5_CPUCOREVR | Default | d | 0.626 | |
PVCCEDRAM_REFIN | Default | d | 0.705 | |
PVCCIOS0_AGND | Default | d | 0.000 | |
PVCCIOS0_CS_N | Default | d | 0.076 | |
PVCCIOS0_CS_N | Default | r | 83.200R | |
PVCCIOS0_CS_P | Default | d | 0.076 | |
PVCCIOS0_CS_P | Default | r | 83.200R | |
PVCCIOS0_EN | Default | d | 0.772 | |
PVCCIOS0_EN_FILT | Default | d | 0.763 | |
PVCCIOS0_EN_FILT_BUF | Default | d | 0.553 | |
PVCCIOS0_EN_R | Default | d | 0.810 | |
PVCCIOS0_FB | Default | d | 0.537 | |
PVCCIOS0_FSEL | Default | d | 0.554 | |
PVCCIOS0_RTN | Default | d | 0.541 | |
PVCCIOS0_SREF | Default | d | 0.552 | |
PVCCIOS0_VO | Default | d | 0.547 | |
PVCCIO_BOOT_RC | Default | d | 0.567 | |
PVCCIO_DRVH | Default | d | 0.549 | |
PVCCIO_DRVH_R | Default | d | 0.548 | |
PVCCIO_DRVL | Default | d | 0.000 | |
PVCCIO_DRVL | Default | r | 0.264R | |
PVCCIO_DRVL_R | Default | d | 0.458 | |
PVCCIO_EN | Default | d | 0.553 | |
PVCCIO_LL | Default | d | 0.058 | |
PVCCIO_LL | Default | r | 58.100R | |
PVCCIO_LL_SNUB | Default | d | OL | |
PVCCIO_PGOOD | Default | d | 0.549 | |
PVCCIO_PHASE | Default | d | 0.076 | |
PVCCIO_VBST | Default | d | 0.060 | |
PVCCIO_VBST | Default | r | 0.300R | |
PVCCOIOS0_OCSET | Default | d | 0.547 | |
PVCCPRIMCORE_FB | Default | d | 0.108 | |
PVCCPRIMCORE_FB_R | Default | d | 0.108 | |
PVCCPRIMCORE_SW0 | Default | d | 0.109 | |
PVCCPRIMCORE_SW1 | Default | d | 0.109 | |
PVDD075GPU_BOOT | Default | d | 0.564 | |
PVDD075GPU_BOOT_RC | Default | d | 0.559 | |
PVDD075GPU_EN | Default | d | 0.625 | |
PVDD075GPU_EN_FILT | Default | d | 0.765 | |
PVDD075GPU_EN_FILT_BUF | Default | d | 0.551 | |
PVDD075GPU_EN_RC | Default | d | 0.811 | |
PVDD075GPU_ISNS_N | Default | r | 49.300R | |
PVDD075GPU_ISNS_P | Default | r | 49.300R | |
PVDD075GPU_OCSET | Default | d | 0.545 | |
PVDD075GPU_PGOOD | Default | d | 0.530 | |
PVDD075GPU_PHASE | Default | d | 0.050 | |
PVDD075GPU_UGATE | Default | d | 0.542 | |
PVDD075GPU_VO | Default | d | 0.545 | |
PVDD18GPU_SW1 | Default | d | 0.200 | |
PVDD18GPU_SW1 | Default | r | 0.001R | |
PVDD18GPU_SW2 | Default | d | 0.200 | |
PVDD18GPU_SW2 | Default | r | 0.001R | |
PVDDCIMEMGPU_BOOT_R | Default | d | 0.538 | |
PVDDCIMEMGPU_COMP | Default | d | 0.605 | |
PVDDCIMEMGPU_FB | Default | d | 0.308 | |
PVDDCIMEMGPU_FB_R | Default | d | OL | |
PVDDCIMEMGPU_IMON | Default | d | 0.633 | |
PVDDCIMEMGPU_ISEN1 | Default | d | 0.629 | |
PVDDCIMEMGPU_ISUMN | Default | d | 0.092 | |
PVDDCIMEMGPU_ISUMN | Default | r | 90.600R | |
PVDDCIMEMGPU_ISUMN_R | Default | d | 0.538 | |
PVDDCIMEMGPU_ISUMN_RES | Default | d | 0.089 | |
PVDDCIMEMGPU_ISUMP | Default | d | 0.584 | |
PVDDCIMEMGPU_ISUMP_RES | Default | d | 0.089 | |
PVDDCIMEMGPU_PGOOD | Default | d | 0.584 | |
PVDDCIMEMGPU_PHASE | Default | d | 0.089 | |
PVDDCIMEMGPU_VSEN | Default | d | 0.307 | |
PVDDCIMEMGPU_VSEN_C | Default | d | 0.308 | |
PVDDCOREGPU_EN | Default | d | 0.572 | |
PVDDCOREGPU_VRHOT_L | Default | d | 0.480 | |
PVDDCPUAWAKE_FB | Default | d | 0.000 | |
PVDDCPUAWAKE_FB_R | Default | d | 0.000 | |
PVDDCPUAWAKE_SW0 | Default | d | 0.032 | |
PVDDCPUAWAKE_SW0 | Default | r | 31.900R | |
PVDDCPUAWAKE_SW1 | Default | d | 0.032 | |
PVDDCPUAWAKE_SW1 | Default | r | 31.900R | |
PVDDCPUAWAKE_SW2 | Default | d | 0.032 | |
PVDDCPUAWAKE_SW2 | Default | r | 31.900R | |
PVDDCPUAWAKE_SW3 | Default | d | 0.032 | |
PVDDCPUAWAKE_SW3 | Default | r | 31.900R | |
PVDDCPUSRAMAWAKE_FB | Default | d | 0.000 | |
PVDDCPUSRAMAWAKE_SW0 | Default | d | 0.355 | |
PVDDCPUSRAMAWAKE_SW0 | Default | r | 353.000 | |
PVDDCRGFXGPU_IMON_FB | Default | d | OL | |
PVDDCRGFXGPU_IMON_R | Default | d | OL | |
PVDDCRGFXGPU_PGOOD | Default | d | 0.575 | |
PVDDCRSOCGPU_FB_R | Default | d | OL | |
PVDDCRSOCGPU_IMON_R | Default | d | OL | |
PVDDCRSOCGPU_PGOOD | Default | d | 0.575 | |
PVDDIOMEMGPU_ISNS1_N | Default | d | 0.048 | |
PVDDIOMEMGPU_ISNS1_P | Default | d | 0.048 | |
PVDDIOMEMGPU_ISNS2_N | Default | d | 0.048 | |
PVDDIOMEMGPU_ISNS2_P | Default | d | 0.048 | |
PVDDIOMEMGPU_LGATE1 | Default | d | 0.466 | |
PVDDIOMEMGPU_LGATE2 | Default | d | 0.467 | |
PVDDIOMEMGPU_PGOOD | Default | d | 0.584 | |
PVDDIOMEMGPU_PHASE1 | Default | d | 0.048 | |
PVDDIOMEMGPU_PHASE2 | Default | d | 0.048 | |
PVDDIOMEMGPU_UGATE1 | Default | d | 0.512 | |
PVDDIOMEMGPU_UGATE2 | Default | d | 0.513 | |
PVDDIOMEMGPU_UGATE2_R | Default | d | 0.513 | |
PVDDMEMGPU_EN | Default | d | 0.575 | |
PVDDMEMGPU_FCCM | Default | d | 0.624 | |
PVDDMEMGPU_RTN | Default | d | 0.007 | |
PVDDMEMGPU_RTN | Default | r | 3.300R | |
PVDDQ_EN | Default | d | 0.735 | |
PVDDQ_EN_LED | Default | d | OL | |
PVDDQ_EN_R | Default | d | 0.501 | |
PVDDQ_PGOOD | Default | d | 0.576 | |
PVDD_GPU_CORE_COMP_C | Default | d | 2.346 | |
PVIN_RFLDO_WLANBT_VLX | Default | d | 0.328 | |
PVIN_RFLDO_WLANBT_VLX | Default | r | 0.100R | |
PVPP_EN_R | Default | d | OL | |
PVTT_VTTSNS | Default | d | 0.134 | |
REG_FB_P2V5S3 | Default | d | 1.405 | |
REG_PHASE_2V5S3 | Default | d | 0.420 | |
REG_VOS_P2V5S3 | Default | d | 0.428 | |
RSLOC_RST_L | Default | d | 0.490 | |
SAVE_BAT_G | Default | d | 0.757 | |
SAVE_BAT_S | Default | d | 1.568 | |
SA_ISUMN_R | Default | d | 1.027 | |
SENSOR_PWR_EN | Default | d | 0.416 | |
SE_CTLR_FW_DWLD | Default | d | 0.479 | |
SE_DEV_WAKE | Default | d | 0.482 | |
SE_GPIO2_AO | Default | d | 0.756 | |
SE_GPIO3_AO | Default | d | 0.756 | |
SE_PWR_EN | Default | d | 0.765 | |
SE_RXN | Default | d | 0.496 | |
SE_RXP | Default | d | 0.496 | |
SE_XTAL1 | Default | d | 0.542 | |
SMCRST_TIEOFF | Default | d | 0.720 | |
SMC_BMON_ISENSE | Default | d | 0.791 | |
SMC_DCIN_ISENSE | Default | d | 0.808 | |
SMC_DCIN_VSENSE | Default | d | 0.807 | |
SMC_DEBUGPRT_RX | Default | d | 0.461 | |
SMC_DEBUGPRT_TX | Default | d | 0.479 | |
SMC_FAN_0_PWM | Default | d | 0.492 | |
SMC_FAN_0_TACH | Default | d | 0.457 | |
SMC_FAN_1_PWM | Default | d | 0.488 | |
SMC_FAN_1_TACH | Default | d | 0.461 | |
SMC_FIXTURE_MODE_L | Default | d | 0.490 | |
SMC_P3V3_CAPLE_ISENSE | Default | d | 0.806 | |
SMC_PBUS_VSENSE | Default | d | 0.806 | |
SMC_PCH_PWROK | Default | d | 0.461 | |
SMC_PCH_SYS_PWROK | Default | d | 0.461 | |
SMC_PECI_TX | Default | d | 0.476 | |
SMC_PECI_TX_R | Default | d | 0.450 | |
SMC_PROCHOT_L | Default | d | 0.469 | |
SMC_RSMRST_L | Default | d | 0.452 | |
SMC_SYSRST_L | Default | d | 0.461 | |
SOC_AMBER_R | Default | d | OL | |
SOC_BLUE_AWAKE | Default | d | OL | |
SOC_BLUE_R | Default | d | OL | |
SOC_COLD_RESET_L | Default | d | 0.494 | |
SOC_DEBUGPRT_RX | Default | d | 0.490 | |
SOC_DEBUGPRT_TX | Default | d | 0.489 | |
SOC_DFU_STATUS | Default | d | 0.534 | |
SOC_DOCK_CONNECT | Default | d | 0.461 | |
SOC_FORCE_DFU | Default | d | 0.490 | |
SOC_GREEN_DDR | Default | d | OL | |
SOC_GREEN_R | Default | d | OL | |
SOC_PCIE_UP_REXT | Default | d | 0.786 | |
SOC_PERST_L | Default | d | 0.485 | |
SOC_PM_THRMTRIP_L | Default | d | 0.771 | |
SOC_PM_THRMTRIP_L_R | Default | d | 0.713 | |
SOC_RED_R | Default | d | OL | |
SOC_RED_SLPS2R | Default | d | OL | |
SOC_SOCHOT_L | Default | d | 0.490 | |
SOC_SWD_MUX_SEL_PCH | Default | d | 0.576 | |
SOC_USB_VBUS | Default | d | 0.420 | |
SOC_VDDCPU_SENSE | Default | d | 0.478 | |
SOC_WDOG | Default | d | 0.492 | |
SPARE_UPC_TA_USB2_RN | Default | d | 0.704 | |
SPARE_UPC_TA_USB2_RP | Default | d | 0.701 | |
SPARE_UPC_TA_USB3_RN | Default | d | 0.704 | |
SPARE_UPC_TA_USB3_RP | Default | d | 0.701 | |
SPARE_UPC_TB_USB2_RN | Default | d | 0.701 | |
SPARE_UPC_TB_USB2_RP | Default | d | 0.701 | |
SPARE_UPC_TB_USB3_RN | Default | d | 0.701 | |
SPARE_UPC_TB_USB3_RP | Default | d | 0.701 | |
SPARE_UPC_XA_USB3_RN | Default | d | 0.735 | |
SPARE_UPC_XA_USB3_RP | Default | d | 0.733 | |
SPARE_UPC_XB_USB2_RN | Default | d | 0.705 | |
SPARE_UPC_XB_USB2_RP | Default | d | 0.704 | |
SPARE_UPC_XB_USB3_RN | Default | d | 0.706 | |
SPARE_UPC_XB_USB3_RP | Default | d | 0.704 | |
SPI_AOP_MA781_CLK | Default | d | 0.520 | |
SPI_AOP_MA781_CS_L | Default | d | 0.496 | |
SPI_AOP_MA781_MISO | Default | d | 0.518 | |
SPI_AOP_MA781_MOSI | Default | d | 0.520 | |
SPI_AOP_SENSOR_CLK_R | Default | d | 0.489 | |
SPI_AOP_SENSOR_MISO | Default | d | 0.495 | |
SPI_DFR_CLK | Default | d | 0.502 | |
SPI_DFR_CS_L | Default | d | 0.460 | |
SPI_DFR_MISO | Default | d | 0.495 | |
SPI_DFR_MISO_R | Default | d | 0.502 | |
SPI_DFR_MOSI | Default | d | 0.485 | |
SPI_IO2_STRAP_L | Default | d | 0.730 | |
SPI_IO<2> | Default | d | 0.800 | |
SPI_MESA_CLK | Default | d | - | |
SPI_MESA_CLK_CONN | Default | d | 0.569 | |
SPI_MESA_CLK_R | Default | d | - | |
SPI_MESA_MISO | Default | d | 0.492 | |
SPI_MESA_MISO_CONN | Default | d | 0.493 | |
SPI_MESA_MOSI | Default | d | 0.511 | |
SPI_MESA_MOSI_CONN | Default | d | 0.513 | |
SPI_MOSI_R | Default | d | 0.814 | |
SPI_MOSI_R_CONN | Default | d | 1.125 | |
SPI_SOCROM_CS_L | Default | d | 0.493 | |
SPI_SOCROM_MISO | Default | d | 0.433 | |
SPI_SOCROM_MISO_R | Default | d | 0.424 | |
SPI_SOCROM_WP_L | Default | d | 0.553 | |
SPI_TPAD3V3_CLK_R | Default | d | 0.680 | |
SPI_TPAD3V3_MOSI_R | Default | d | 0.678 | |
SPI_TPAD_CLK | Default | d | 0.504 | |
SPI_TPAD_CLK_CONN | Default | d | 0.703 | |
SPI_TPAD_CS_CONN_L | Default | d | 0.682 | |
SPI_TPAD_CS_L | Default | d | 0.477 | |
SPI_TPAD_EN_CONN | Default | d | 0.490 | |
SPI_TPAD_INT_CONN_L | Default | d | 0.495 | |
SPI_TPAD_MISO | Default | d | 0.487 | |
SPI_TPAD_MISO_CONN | Default | d | 0.684 | |
SPI_TPAD_MISO_R | Default | d | 0.506 | |
SPI_TPAD_MOSI | Default | d | 0.505 | |
SPI_TPAD_MOSI_CONN | Default | d | 0.702 | |
SPKRAMP_INT_L | Default | d | 0.356 | |
SPKRAMP_LT_AREG | Default | d | 0.587 | |
SPKRAMP_LT_BSTN | Default | d | 0.778 | |
SPKRAMP_LT_BSTP | Default | d | 0.778 | |
SPKRAMP_LT_DREG | Default | d | 0.524 | |
SPKRAMP_LT_MODE | Default | d | 0.473 | |
SPKRAMP_LT_OUTN | Default | d | 0.470 | |
SPKRAMP_LT_OUTN | Default | r | 0.281R | |
SPKRAMP_LT_OUTP | Default | d | 0.470 | |
SPKRAMP_LT_OUTP | Default | r | 0.283R | |
SPKRAMP_LW1_AREG | Default | d | 0.584 | |
SPKRAMP_LW1_BSTN | Default | d | 0.778 | |
SPKRAMP_LW1_BSTP | Default | d | 0.778 | |
SPKRAMP_LW1_DREG | Default | d | 0.523 | |
SPKRAMP_LW1_MODE | Default | d | 0.000 | |
SPKRAMP_LW1_OUTN | Default | d | 0.480 | |
SPKRAMP_LW1_OUTN | Default | r | 0.287R | |
SPKRAMP_LW1_OUTP | Default | d | 0.480 | |
SPKRAMP_LW1_OUTP | Default | r | 0.287R | |
SPKRAMP_LW2_AREG | Default | d | 0.587 | |
SPKRAMP_LW2_BSTN | Default | d | 0.778 | |
SPKRAMP_LW2_BSTP | Default | d | 0.778 | |
SPKRAMP_LW2_DREG | Default | d | 0.524 | |
SPKRAMP_LW2_MODE | Default | d | 0.407 | |
SPKRAMP_LW2_OUTN | Default | d | 0.480 | |
SPKRAMP_LW2_OUTN | Default | r | 0.295R | |
SPKRAMP_LW2_OUTP | Default | d | 0.480 | |
SPKRAMP_LW2_OUTP | Default | r | 0.293R | |
SPKRAMP_RESET_L | Default | d | 0.355 | |
SPKRAMP_RT_AREG | Default | d | 0.590 | |
SPKRAMP_RT_BSTN | Default | d | 0.775 | |
SPKRAMP_RT_BSTP | Default | d | 0.775 | |
SPKRAMP_RT_DREG | Default | d | 0.525 | |
SPKRAMP_RT_MODE | Default | d | 0.474 | |
SPKRAMP_RT_OUTN | Default | d | 0.485 | |
SPKRAMP_RT_OUTN | Default | r | 0.281R | |
SPKRAMP_RT_OUTP | Default | d | 0.484 | |
SPKRAMP_RT_OUTP | Default | r | 0.285R | |
SPKRAMP_RW1_AREG | Default | d | 0.583 | |
SPKRAMP_RW1_BSTN | Default | d | 0.775 | |
SPKRAMP_RW1_BSTP | Default | d | 0.775 | |
SPKRAMP_RW1_MODE | Default | d | 0.014 | |
SPKRAMP_RW1_MODE | Default | r | 13.000R | |
SPKRAMP_RW1_OUTN | Default | d | 0.484 | |
SPKRAMP_RW1_OUTN | Default | r | 0.290R | |
SPKRAMP_RW1_OUTP | Default | d | 0.485 | |
SPKRAMP_RW1_OUTP | Default | r | 0.291R | |
SPKRAMP_RW2_AREG | Default | d | 0.583 | |
SPKRAMP_RW2_BSTN | Default | d | 0.775 | |
SPKRAMP_RW2_BSTP | Default | d | 0.775 | |
SPKRAMP_RW2_DREG | Default | d | 0.523 | |
SPKRAMP_RW2_MODE | Default | d | 0.405 | |
SPKRAMP_RW2_OUTN | Default | d | 0.478 | |
SPKRAMP_RW2_OUTN | Default | r | 0.279R | |
SPKRAMP_RW2_OUTP | Default | d | 0.480 | |
SPKRAMP_RW2_OUTP | Default | r | 0.282R | |
SPKRCONN_LT_OUTN | Default | d | 0.470 | |
SPKRCONN_LT_OUTN | Default | r | 0.281R | |
SPKRCONN_LT_OUTP | Default | d | 0.470 | |
SPKRCONN_LT_OUTP | Default | r | 0.283R | |
SPKRCONN_LW1_OUTN | Default | d | 0.480 | |
SPKRCONN_LW1_OUTN | Default | r | 0.287R | |
SPKRCONN_LW1_OUTP | Default | d | 0.480 | |
SPKRCONN_LW1_OUTP | Default | r | 0.287R | |
SPKRCONN_LW2_OUTN | Default | d | 0.480 | |
SPKRCONN_LW2_OUTN | Default | r | 0.295R | |
SPKRCONN_LW2_OUTP | Default | d | 0.480 | |
SPKRCONN_LW2_OUTP | Default | r | 0.293R | |
SPKRCONN_RT_OUTN | Default | d | 0.485 | |
SPKRCONN_RT_OUTN | Default | r | 0.281R | |
SPKRCONN_RT_OUTP | Default | d | 0.484 | |
SPKRCONN_RT_OUTP | Default | r | 0.285R | |
SPKRCONN_RW1_OUTN | Default | d | 0.484 | |
SPKRCONN_RW1_OUTN | Default | r | 0.290R | |
SPKRCONN_RW1_OUTP | Default | d | 0.485 | |
SPKRCONN_RW1_OUTP | Default | r | 0.291R | |
SPKRCONN_RW2_OUTN | Default | d | 0.478 | |
SPKRCONN_RW2_OUTN | Default | r | 0.279R | |
SPKRCONN_RW2_OUTP | Default | d | 0.480 | |
SPKRCONN_RW2_OUTP | Default | r | 0.282R | |
SPMI_DATA | Default | d | 0.418 | |
SPMI_DATA_R | Default | d | 0.438 | |
SPROM_CLK | Default | d | 0.500 | |
SPROM_CS | Default | d | 0.496 | |
SPROM_CS_R | Default | d | 0.573 | |
SPROM_DIN | Default | d | 0.514 | |
SPROM_DOUT | Default | d | 0.501 | |
SSD0_CLK24M | Default | d | 0.454 | |
SSD0_CLK24M_23 | Default | d | 0.000 | |
SSD0_CLKREQ0_L | Default | d | - | |
SSD0_CLKREQ3_L | Default | d | 0.483 | |
SSD0_OCARINA_FORCE_EN | Default | d | 0.571 | |
SSD0_OCARINA_IREF | Default | d | 0.750 | |
SSD0_OCARINA_NAND_VCC_DET | Default | d | 0.763 | |
SSD0_OCARINA_PFN | Default | t | ok | |
SSD0_OCARINA_PFN | Default | v | 1.80 | |
SSD0_OCARINA_POK2 | Default | d | 0.000 | |
SSD0_OCARINA_TCAL | Default | d | 0.777 | |
SSD0_OCARINA_TDEV1 | Default | d | 0.773 | |
SSD0_OCARINA_TDEV2 | Default | d | 0.771 | |
SSD0_OCARINA_VDD_LDO | Default | d | 0.369 | |
SSD0_OCARINA_VREF | Default | d | 0.772 | |
SSD0_OCARINA_WP_L | Default | v | 1.80 | |
SSD0_S4E0_PCIE_RESREF | Default | d | 0.788 | |
SSD0_S4E0_SWD_UID0 | Default | d | 0.499 | |
SSD0_S4E0_SWD_UID1 | Default | d | 0.498 | |
SSD0_S4E0_UART_TX | Default | d | 0.499 | |
SSD0_S4E0_VPP | Default | d | 0.571 | |
SSD0_S4E0_ZQ_L | Default | d | 0.302 | |
SSD0_S4E3_DROOP_L | Default | d | 0.524 | |
SSD0_S4E3_JTAG_TDO | Default | d | - | |
SSD0_S4E3_PCIE_RESREF | Default | d | 0.790 | |
SSD0_S4E3_SWD_UID0 | Default | d | 0.517 | |
SSD0_S4E3_SWD_UID1 | Default | d | 0.517 | |
SSD0_S4E3_UART_TX | Default | d | 0.517 | |
SSD0_S4E3_ZQ_L | Default | d | 0.301 | |
SSD0_S4E_BOOT2 | Default | d | 0.446 | |
SSD0_STG01_ADDR | Default | d | 0.572 | |
SSD0_TPS62180_FB | Default | d | 1.422 | |
SSD0_TPS62180_FB_R | Default | d | 0.418 | |
SSD0_TPS62180_SS | Default | d | 0.540 | |
SSD0_VR_P2V5_EN | Default | d | 0.647 | |
SSD0_VR_P2V5_PGOOD | Default | d | 0.565 | |
SSD1_CLK24M_01 | Default | d | 0.490 | |
SSD1_OCARINA_FORCE_EN | Default | d | 0.569 | |
SSD1_OCARINA_IREF | Default | d | 0.750 | |
SSD1_OCARINA_PGOOD | Default | d | 0.761 | |
SSD1_OCARINA_POK2 | Default | d | 0.000 | |
SSD1_OCARINA_TCAL | Default | d | 0.776 | |
SSD1_OCARINA_TDEV1 | Default | d | 0.777 | |
SSD1_OCARINA_TDEV2 | Default | d | 0.776 | |
SSD1_OCARINA_VDD_LDO | Default | d | 0.369 | |
SSD1_OCARINA_VREF | Default | d | 0.771 | |
SSD1_S4E0_JTAG_TDI | Default | d | 0.508 | |
SSD1_S4E0_UART_TX | Default | d | 0.495 | |
SSD1_S4E1_UART_TX | Default | d | OL | |
SSD1_TPS62180_FB | Default | d | 1.417 | |
SSD1_TPS62180_FB_R | Default | d | 0.438 | |
SSD1_TPS62180_SS | Default | d | 0.539 | |
SSD1_VR_P2V5_EN | Default | d | 0.650 | |
SSD1_VR_P2V5_EN_R | Default | d | 0.650 | |
SSD1_VR_P2V5_PGOOD | Default | d | 0.562 | |
SSD_PMU_RESET_L | Default | t | ok | |
SSD_PMU_RESET_L | Default | v | 1.80 | |
SSTATE_BLUE | Default | d | OL | |
SSTATE_BLUE_R | Default | d | OL | |
SSTATE_GREEN | Default | d | OL | |
SSTATE_GREEN_R | Default | d | OL | |
SSTATE_RED | Default | d | OL | |
SSTATE_RED_R | Default | d | OL | |
SVID_PWROK | Default | d | 0.528 | |
SVID_PWROK_CONN | Default | d | OL | |
SWD_SOC_SWCLK | Default | d | 0.464 | |
SWD_SOC_SWDIO | Default | d | 0.464 | |
SYS_DETECT | Default | d | OL | |
SYS_DETECT_L | Default | d | 0.515 | |
TBTTHMSNS_T_D1_N | Default | d | 0.000 | |
TBTTHMSNS_T_D1_P | Default | d | 0.620 | |
TBTTHMSNS_X_D1_N | Default | d | 0.000 | |
TBTTHMSNS_X_D1_P | Default | d | 0.633 | |
TBT_POC_RESET | Default | d | 0.540 | |
TBT_PWR_EN | Default | d | 0.542 | |
TBT_TA_USB2_MXCTL | Default | d | 0.602 | |
TBT_TA_USB2_RBIAS | Default | d | 0.202 | |
TBT_TB_USB2_MXCTL | Default | d | 0.601 | |
TBT_TB_USB2_RBIAS | Default | d | 0.000 | |
TBT_T_BATLOW_L | Default | d | 0.604 | |
TBT_T_CIO_PWR_EN | Default | d | 0.517 | |
TBT_T_CLKREQ_L | Default | d | 0.811 | |
TBT_T_CLKREQ_R_L | Default | d | 0.602 | |
TBT_T_HDMI_DDC_CLK | Default | d | 0.602 | |
TBT_T_HDMI_DDC_DATA | Default | d | 0.563 | |
TBT_T_PCI_RESET_L | Default | d | 0.551 | |
TBT_T_PLUG_EVENT_L | Default | d | 0.542 | |
TBT_T_PWR_EN_U8295 | Default | d | 0.544 | |
TBT_T_RBIAS | Default | d | 0.781 | |
TBT_T_ROM_HOLD_L | Default | d | 0.680 | |
TBT_T_ROM_WP_L | Default | d | 0.560 | |
TBT_T_RSENSE | Default | d | 0.000 | |
TBT_T_SPI_CLK | Default | d | 0.540 | |
TBT_T_SPI_CLK_DBG | Default | d | 0.602 | |
TBT_T_SPI_CS_L | Default | d | 0.560 | |
TBT_T_SPI_MISO | Default | d | 0.560 | |
TBT_T_SPI_MOSI | Default | d | 0.560 | |
TBT_T_TEST_EN | Default | d | 0.101 | |
TBT_T_TEST_PWR_GOOD | Default | d | 0.101 | |
TBT_T_TMU_CLK_IN | Default | d | 0.601 | |
TBT_T_TMU_CLK_OUT | Default | d | 0.604 | |
TBT_T_USB_PWR_EN | Default | d | 0.554 | |
TBT_T_XTAL25M_IN | Default | d | 0.836 | |
TBT_T_XTAL25M_OUT | Default | d | 0.782 | |
TBT_WAKE_3V3_L | Default | d | 0.535 | |
TBT_X_CIO_PWR_EN | Default | d | 0.540 | |
TBT_X_HDMI_DDC_CLK | Default | d | 0.609 | |
TBT_X_HDMI_DDC_DATA | Default | d | 0.574 | |
TBT_X_PCIE_BIAS | Default | d | 0.790 | |
TBT_X_PCI_RESET_L | Default | d | 0.554 | |
TBT_X_PLUG_EVENT_L | Default | d | 0.564 | |
TBT_X_PWR_EN_U8297 | Default | d | 0.541 | |
TBT_X_RBIAS | Default | d | 0.780 | |
TBT_X_ROM_HOLD_L | Default | d | 0.681 | |
TBT_X_ROM_WP_L | Default | d | 0.566 | |
TBT_X_RSENSE | Default | d | 0.000 | |
TBT_X_RTD3_PWR_EN | Default | d | 0.609 | |
TBT_X_SPI_ARK_CLK | Default | d | - | |
TBT_X_SPI_CLK | Default | d | 0.548 | |
TBT_X_SPI_CS_L | Default | d | 0.570 | |
TBT_X_SPI_DBG_CLK | Default | d | OL | |
TBT_X_SPI_DBG_CS_L | Default | d | OL | |
TBT_X_SPI_DBG_MISO | Default | d | OL | |
TBT_X_SPI_DBG_MOSI | Default | d | OL | |
TBT_X_SPI_MISO | Default | d | 0.571 | |
TBT_X_SPI_MOSI | Default | d | 0.574 | |
TBT_X_TMU_CLK_IN | Default | d | 0.611 | |
TBT_X_USB_PWR_EN | Default | d | 0.552 | |
TBT_X_XTAL25M_IN | Default | d | 0.835 | |
TBT_X_XTAL25M_OUT | Default | d | 0.786 | |
TPAD_KBD_WAKE_L | Default | d | 0.494 | |
TPAD_SPI_EN | Default | d | 0.490 | |
TPAD_SPI_INT_L | Default | d | 0.493 | |
TP_BMON_IOUT | Default | d | OL | |
TP_BT_GPIO_4 | Default | d | 0.712 | |
TP_CPU_RSVD_TP75 | Default | d | 0.337 | |
TP_CPU_RSVD_TP76 | Default | d | 0.236 | |
TP_CPU_RSVD_TP_BT2 | Default | d | 0.341 | |
TP_CPU_RSVD_TP_D1 | Default | d | 0.236 | |
TP_DFR_TOUCH_PANEL_DETECT | Default | d | OL | |
TP_DFR_TOUCH_ROM_WC | Default | d | OL | |
TP_DFR_TOUCH_RSVD | Default | d | OL | |
TP_GPU_A1_DETECT | Default | d | OL | |
TP_GPU_BAMACO_EN | Default | d | 0.404 | |
TP_HDA_RST | Default | d | 0.821 | |
TP_HDA_SDI1 | Default | d | 0.822 | |
TP_HDA_SDO | Default | d | 0.822 | |
TP_ISNS_SKPRLN | Default | d | OL | |
TP_ISNS_SKPRLP | Default | d | OL | |
TP_JTAG_SOC_TDI | Default | d | 0.497 | |
TP_JTAG_SOC_TDO | Default | d | 0.494 | |
TP_PCH_STRP_TOPBLK_SWP_L | Default | d | 0.828 | |
TP_PCH_TP1_F22 | Default | d | 0.785 | |
TP_PCH_TP3_B24 | Default | d | 0.837 | |
TP_SOC_TST_CLKOUT | Default | d | 0.486 | |
TP_SSD0_S4E0_ANI0_VREF | Default | d | 0.776 | |
TP_SSD0_S4E0_ANI1_VREF | Default | d | 0.775 | |
TP_SSD0_S4E1_ANI0_VREF | Default | d | 0.774 | |
TP_SSD0_S4E1_ANI1_VREF | Default | d | 0.774 | |
TP_SSD0_S4E2_ANI1_VREF | Default | d | 0.776 | |
TP_SSD0_S4E3_ANI0_VREF | Default | d | 0.770 | |
TP_SSD0_S4E3_ANI1_VREF | Default | d | 0.774 | |
TP_UPC_TA_GPIO10 | Default | d | 0.693 | |
TP_UPC_TA_GPIO9 | Default | d | 0.691 | |
TP_UPC_TB_GPIO10 | Default | d | 0.691 | |
TP_UPC_TB_GPIO9 | Default | d | 0.687 | |
TP_USBC_PP20V_TA | Default | d | OL | |
TP_USBC_PP20V_TB | Default | d | OL | |
TP_USBC_PP20V_XA | Default | d | OL | |
TP_USBC_PP20V_XB | Default | d | OL | |
TP_USBC_TB_RESET_L | Default | d | 0.641 | |
TP_USBC_XA_RESET_L | Default | d | 0.678 | |
TSNS_T1_DX1_N | Default | d | 0.000 | |
TSNS_T1_DX1_P | Default | d | 0.647 | |
TSNS_T1_DX2_N | Default | d | 0.000 | |
TSNS_T1_DX2_P | Default | d | 0.649 | |
TSNS_T1_DX5_N | Default | d | 0.000 | |
TSNS_T1_DX5_P | Default | d | 0.650 | |
TSNS_T1_DX7_N | Default | d | 0.000 | |
TSNS_T1_DX7_P | Default | d | 0.648 | |
U4800_PIN4 | Default | d | 0.687 | |
U6801_PWR_EN | Default | d | 0.300 | |
UART_BT_BUF_CTS_L | Default | d | 0.481 | |
UART_BT_BUF_D2R | Default | d | 0.449 | |
UART_BT_BUF_R2D | Default | d | 0.481 | |
UART_BT_BUF_RTS_L | Default | d | 0.448 | |
UART_BT_LH_D2R | Default | d | 0.487 | |
UART_SE_D2R | Default | d | 0.480 | |
UART_SE_D2R_CTS_L | Default | d | 0.479 | |
UART_SE_R2D | Default | d | 0.455 | |
UART_SE_R2D_RTS_L | Default | d | 0.455 | |
UART_WLAN_D2R | Default | d | 0.489 | |
UART_WLAN_D2R_CTS_L | Default | d | 0.488 | |
UNCONNECTED_75 | Default | d | - | |
UPC_DBG_T | Default | d | 0.545 | |
UPC_I2C_INT_L | Default | d | 0.457 | |
UPC_PMU_RESET | Default | d | 0.540 | |
UPC_TA_DBG0 | Default | d | 0.677 | |
UPC_TA_DBG1 | Default | d | 0.667 | |
UPC_TA_FAULT_L | Default | d | 0.625 | |
UPC_TA_GPIO1 | Default | d | 0.637 | |
UPC_TA_GPIO7 | Default | d | 0.690 | |
UPC_TA_R_OSC | Default | d | 0.458 | |
UPC_TA_SER_DBG | Default | d | 0.628 | |
UPC_TA_SPI_CLK | Default | d | 0.549 | |
UPC_TA_SPI_CS_L | Default | d | 0.685 | |
UPC_TA_SPI_MISO | Default | d | 0.569 | |
UPC_TA_SPI_MOSI | Default | d | 0.573 | |
UPC_TA_SS | Default | d | 0.557 | |
UPC_TA_SWD_CLK | Default | d | 0.571 | |
UPC_TA_SWD_DATA | Default | d | 0.677 | |
UPC_TA_UART_RX | Default | d | 0.531 | |
UPC_TA_UART_TX | Default | d | 0.530 | |
UPC_TB_FAULT_L | Default | d | 0.627 | |
UPC_TB_GPIO1 | Default | d | 0.634 | |
UPC_TB_GPIO7 | Default | d | 0.691 | |
UPC_TB_R_OSC | Default | d | 0.452 | |
UPC_TB_SER_DBG | Default | d | 0.633 | |
UPC_TB_SS | Default | d | 0.555 | |
UPC_TB_SWD_CLK | Default | d | 0.569 | |
UPC_TB_SWD_DATA | Default | d | 0.673 | |
UPC_T_5V_EN | Default | d | 0.590 | |
UPC_T_5V_EN_R | Default | d | 0.566 | |
UPC_T_SPI_CLK | Default | d | 0.568 | |
UPC_T_SPI_CS_L | Default | d | 0.591 | |
UPC_T_SPI_MISO | Default | d | 0.592 | |
UPC_T_SPI_MOSI | Default | d | 0.595 | |
UPC_XA_DBG_PD | Default | d | 0.663 | |
UPC_XA_FAULT_L | Default | d | 0.690 | |
UPC_XA_R_OSC | Default | d | 0.474 | |
UPC_XA_SER_DBG | Default | d | 0.638 | |
UPC_XA_SWD_CLK | Default | d | 0.607 | |
UPC_XA_SWD_DATA | Default | d | 0.718 | |
UPC_XA_UART_RX | Default | d | 0.535 | |
UPC_XA_UART_TX | Default | d | 0.535 | |
UPC_XB_DBG4 | Default | d | 0.464 | |
UPC_XB_DBG5 | Default | d | 0.464 | |
UPC_XB_FAULT_L | Default | d | 0.655 | |
UPC_XB_GPIO1 | Default | d | 0.634 | |
UPC_XB_GPIO10 | Default | d | 0.688 | |
UPC_XB_GPIO4 | Default | d | 0.640 | |
UPC_XB_GPIO9 | Default | d | 0.684 | |
UPC_XB_R_OSC | Default | d | 0.454 | |
UPC_XB_SER_DBG | Default | d | 0.640 | |
UPC_XB_SPI_CLK | Default | d | 0.555 | |
UPC_XB_SPI_CS_L | Default | d | 0.577 | |
UPC_XB_SPI_MISO | Default | d | 0.579 | |
UPC_XB_SPI_MOSI | Default | d | 0.581 | |
UPC_XB_SS | Default | d | 0.557 | |
UPC_XB_SWD_CLK | Default | d | 0.570 | |
UPC_XB_SWD_DATA | Default | d | 0.670 | |
UPC_X_5V_EN | Default | d | 0.588 | |
UPC_X_5V_EN_R | Default | d | 0.533 | |
UPC_X_SPI_CLK | Default | d | 0.576 | |
UPC_X_SPI_MOSI | Default | d | 0.566 | |
USB3_EXTA_D2R_N | Default | d | 0.327 | |
USB3_EXTA_D2R_P | Default | d | 0.322 | |
USB3_EXTA_R2D_C_N | Default | d | 0.314 | |
USB3_EXTA_R2D_C_P | Default | d | 0.314 | |
USB3_EXTA_R2D_N | Default | d | 0.682 | |
USB3_EXTA_R2D_P | Default | d | 0.668 | |
USB3_TEST2_D2R_N | Default | d | 0.328 | |
USB3_TEST2_D2R_P | Default | d | 0.327 | |
USB3_TEST2_R2D_N | Default | d | 0.308 | |
USB3_TEST2_R2D_P | Default | d | 0.309 | |
USB3_TEST_D2R_N | Default | d | 0.325 | |
USB3_TEST_D2R_P | Default | d | 0.325 | |
USB3_TEST_R2D_N | Default | d | 0.309 | |
USB3_TEST_R2D_P | Default | d | 0.309 | |
USBC_TA_CC1 | Default | d | 0.590 | |
USBC_TA_CC2 | Default | d | 0.594 | |
USBC_TA_D2R_CR_N<1> | Default | d | OL | |
USBC_TA_D2R_CR_N<2> | Default | d | OL | |
USBC_TA_D2R_CR_P<1> | Default | d | OL | |
USBC_TA_D2R_CR_P<2> | Default | d | OL | |
USBC_TA_R2D_N<1> | Default | d | OL | |
USBC_TA_R2D_N<2> | Default | d | OL | |
USBC_TA_R2D_P<1> | Default | d | OL | |
USBC_TA_R2D_P<2> | Default | d | OL | |
USBC_TA_SBU1 | Default | d | 0.661 | |
USBC_TA_SBU2 | Default | d | 0.660 | |
USBC_TA_USB_BOT_N | Default | d | 0.766 | |
USBC_TA_USB_BOT_P | Default | d | 0.770 | |
USBC_TA_USB_TOP_N | Default | d | 0.768 | |
USBC_TA_USB_TOP_P | Default | d | 0.770 | |
USBC_TB_CC1 | Default | d | 0.590 | |
USBC_TB_CC2 | Default | d | 0.590 | |
USBC_TB_D2R_CR_N<1> | Default | d | OL | |
USBC_TB_D2R_CR_N<2> | Default | d | OL | |
USBC_TB_D2R_CR_P<1> | Default | d | OL | |
USBC_TB_D2R_CR_P<2> | Default | d | OL | |
USBC_TB_R2D_N<2> | Default | d | OL | |
USBC_TB_R2D_P<1> | Default | d | OL | |
USBC_TB_R2D_P<2> | Default | d | OL | |
USBC_TB_SBU1 | Default | d | 0.660 | |
USBC_TB_SBU2 | Default | d | 0.660 | |
USBC_TB_USB_BOT_N | Default | d | 0.766 | |
USBC_TB_USB_BOT_P | Default | d | 0.770 | |
USBC_TB_USB_TOP_N | Default | d | 0.768 | |
USBC_TB_USB_TOP_P | Default | d | 0.770 | |
USBC_T_RESET_L | Default | d | 0.630 | |
USBC_XA_CC1 | Default | d | 0.595 | |
USBC_XA_CC2 | Default | d | 0.594 | |
USBC_XA_D2R_CR_N<1> | Default | d | OL | |
USBC_XA_D2R_CR_P<1> | Default | d | 0.773 | |
USBC_XA_D2R_CR_P<2> | Default | d | OL | |
USBC_XA_R2D_N<1> | Default | d | 0.663 | |
USBC_XA_R2D_N<2> | Default | d | OL | |
USBC_XA_R2D_P<1> | Default | d | 0.663 | |
USBC_XA_R2D_P<2> | Default | d | OL | |
USBC_XA_SBU1 | Default | d | 0.662 | |
USBC_XA_SBU2 | Default | d | OL | |
USBC_XA_USB_BOT_N | Default | d | 0.770 | |
USBC_XA_USB_BOT_P | Default | d | 0.772 | |
USBC_XA_USB_TOP_N | Default | d | OL | |
USBC_XA_USB_TOP_P | Default | d | OL | |
USBC_XB_AUXLSX2 | Default | d | - | |
USBC_XB_CC1 | Default | d | 0.590 | |
USBC_XB_CC2 | Default | d | 0.566 | |
USBC_XB_D2R_CR_N<1> | Default | d | OL | |
USBC_XB_D2R_CR_N<2> | Default | d | 0.771 | |
USBC_XB_D2R_CR_P<1> | Default | d | OL | |
USBC_XB_D2R_CR_P<2> | Default | d | 0.773 | |
USBC_XB_R2D_N<1> | Default | d | OL | |
USBC_XB_R2D_N<2> | Default | d | 0.600 | |
USBC_XB_R2D_P<1> | Default | d | OL | |
USBC_XB_R2D_P<2> | Default | d | - | |
USBC_XB_SBU1 | Default | d | OL | |
USBC_XB_SBU2 | Default | d | 0.669 | |
USBC_XB_USB_BOT_N | Default | d | 0.770 | |
USBC_XB_USB_BOT_P | Default | d | 0.771 | |
USBC_XB_USB_TOP_N | Default | d | OL | |
USBC_XB_USB_TOP_P | Default | d | OL | |
USBC_X_RESET_L | Default | d | 0.637 | |
USB_SOC_N | Default | d | 0.722 | |
USB_SOC_P | Default | d | 0.721 | |
USB_UPC_PCH_TA_F_N | Default | d | 0.436 | |
USB_UPC_PCH_TA_F_P | Default | d | 0.438 | |
USB_UPC_PCH_TA_N | Default | d | 0.486 | |
USB_UPC_PCH_TA_P | Default | d | 0.488 | |
USB_UPC_PCH_TB_F_N | Default | d | 0.440 | |
USB_UPC_PCH_TB_F_P | Default | d | 0.440 | |
USB_UPC_PCH_TB_N | Default | d | 0.487 | |
USB_UPC_PCH_TB_P | Default | d | 0.493 | |
USB_UPC_PCH_XA_F_N | Default | d | 0.489 | |
USB_UPC_PCH_XA_F_P | Default | d | 0.490 | |
USB_UPC_PCH_XA_N | Default | d | 0.489 | |
USB_UPC_PCH_XA_P | Default | d | 0.490 | |
USB_UPC_PCH_XB_N | Default | d | 0.493 | |
USB_UPC_PCH_XB_P | Default | d | 0.491 | |
USB_UPC_XB_F_N | Default | d | 0.442 | |
USB_UPC_XB_F_P | Default | d | 0.445 | |
USFF_MEM_OK | Default | d | 0.815 | |
UVP_DIS_L | Default | d | 0.555 | |
VR0V9_IND_TBT_T | Default | d | 0.288 | |
VR0V9_IND_TBT_T | Default | r | 286.000 | |
VR0V9_IND_TBT_X | Default | d | 0.320 | |
VR0V9_IND_TBT_X | Default | r | 312.000R | |
VSNS_PP0V82_SLPDDR_NEG | Default | d | 0.000 | |
VSNS_PP0V82_SLPDDR_POS | Default | d | 0.049 | |
VSNS_PP0V82_SLPDDR_POS | Default | r | 49.000R | |
VSNS_PP1V05_PRIM_NEG | Default | d | 0.000 | |
VSNS_PP1V05_PRIM_NEG | Default | r | 0.800R | |
VSNS_PP1V05_PRIM_POS | Default | d | 0.099 | |
VSNS_PP1V05_PRIM_POS | Default | r | 98.000R | |
VSNS_PP1V2_S3_CPUDDR_NEG | Default | d | 0.000 | |
VSNS_PP1V2_S3_CPUDDR_NEG | Default | r | 0.900R | |
VSNS_PP1V2_S3_CPUDDR_POS | Default | d | 0.220 | |
VSNS_PP1V2_S3_NEG | Default | d | 0.000 | |
VSNS_PP1V2_S3_POS | Default | d | 0.220 | |
VSNS_PP1V8_S0_GPU_REG_NEG | Default | d | 0.000 | |
VSNS_PP1V8_S0_GPU_REG_POS | Default | d | 0.186 | |
VSNS_PP1V8_SLPS2R_NEG | Default | d | 0.000 | |
VSNS_PP1V8_SLPS2R_POS | Default | d | 0.407 | |
VSNS_PP2V5_NAND_SSD0_NEG | Default | d | 0.000 | |
VSNS_PP2V5_NAND_SSD0_POS | Default | d | 0.408 | |
VSNS_PP2V5_NAND_SSD1_NEG | Default | d | 0.000 | |
VSNS_PP2V5_NAND_SSD1_POS | Default | d | 0.430 | |
VSNS_PP3V3_G3H_RTC_X_NEG | Default | d | 0.000 | |
VSNS_PP3V3_G3H_RTC_X_POS | Default | d | 0.419 | |
VSNS_PP3V3_G3H_T_NEG | Default | d | 0.000 | |
VSNS_PP3V3_G3H_T_POS | Default | d | 0.378 | |
VSNS_PP5V_G3S_NEG | Default | d | 0.000 | |
VSNS_PP5V_G3S_POS | Default | d | 0.403 | |
VSNS_PPBUS_HS_CPU_NEG | Default | d | 0.000 | |
VSNS_PPBUS_HS_CPU_POS | Default | d | 0.413 | |
VSNS_PPBUS_HS_OTH5V_NEG | Default | d | 0.000 | |
VSNS_PPBUS_HS_OTH5V_POS | Default | d | 0.414 | |
VSNS_PPVCCGT_S0_CPU_NEG | Default | d | 0.000 | |
VSNS_PPVCCGT_S0_CPU_POS | Default | d | 0.006 | |
VSNS_PPVCCIO_S0_CPU_NEG | Default | d | 0.000 | |
VSNS_PPVCCIO_S0_CPU_NEG | Default | r | 1.000R | |
VSNS_PPVCCIO_S0_CPU_POS | Default | d | 0.069 | |
VSNS_PPVCCIO_S0_CPU_POS | Default | r | 68.700R | |
VSNS_PPVCCPRIMCORE_PRIM_REG_NEG | Default | d | 0.000 | |
VSNS_PPVCCPRIMCORE_PRIM_REG_POS | Default | d | 0.103 | |
VSNS_PPVCCSA_S0_CPU_NEG | Default | d | 0.000 | |
VSNS_PPVCCSA_S0_CPU_POS | Default | d | 0.020 | |
VSNS_PPVCC_S0_CPU_NEG | Default | d | 0.000 | |
VSNS_PPVCC_S0_CPU_POS | Default | d | 0.002 | |
VSNS_PPVDDCPU_AWAKE_NEG | Default | d | 0.000 | |
VSNS_PPVDDCPU_AWAKE_POS | Default | d | 0.030 | |
VSNS_PPVDDCPU_AWAKE_POS | Default | r | 29.000R | |
VSNS_PPVIN_S0_CPUVR_VIN_NEG | Default | d | 0.000 | |
VSNS_PPVIN_S0_CPUVR_VIN_POS | Default | d | 0.423 | |
WIFI_SROM_ORG | Default | d | OL | |
WLANBT_PCIE_WAKE_L | Default | d | 0.527 | |
WLAN_AUDIO_SYNC | Default | d | 0.642 | |
WLAN_AUDIO_SYNC_LS3V3 | Default | d | 0.639 | |
WLAN_HOST_WAKE | Default | d | 0.489 | |
WLAN_JTAG_SEL | Default | d | 0.722 | |
WLAN_JTAG_TCK | Default | d | 0.742 | |
WLAN_JTAG_TDI | Default | d | 0.488 | |
WLAN_JTAG_TDO | Default | d | 0.740 | |
WLAN_JTAG_TMS | Default | d | 0.744 | |
WLAN_JTAG_TRST_L | Default | d | 0.739 | |
WLAN_SROM_STRAP | Default | d | 0.728 | |
XDP_BPM_L<0> | Default | d | 0.285 | |
XDP_BPM_L<1> | Default | d | 0.284 | |
XDP_BPM_L<2> | Default | d | 0.283 | |
XDP_BPM_L<3> | Default | d | 0.283 | |
XDP_CPU_TCK | Default | d | 0.052 | |
XDP_CPU_TCK | Default | r | 51.700R | |
XDP_CPU_TDO | Default | d | 0.218 | |
XDP_JTAG_ISP_TCK | Default | d | 0.569 | |
XDP_JTAG_ISP_TDI | Default | d | 0.567 | |
XDP_JTAG_ISP_TDO | Default | d | 0.570 | |
XDP_PCH_OBSDATA_A0 | Default | d | 0.823 | |
XDP_PCH_OBSDATA_A1 | Default | d | 0.823 | |
XDP_PCH_OBSDATA_A2 | Default | d | 0.824 | |
XDP_PCH_OBSDATA_A3 | Default | d | 0.824 | |
XDP_PCH_OBSDATA_B0 | Default | d | 0.824 | |
XDP_PCH_OBSDATA_B1 | Default | d | 0.824 | |
XDP_PCH_OBSDATA_B2 | Default | d | 0.824 | |
XDP_PCH_OBSDATA_B3 | Default | d | 0.824 | |
XDP_PCH_OBSDATA_D0 | Default | d | 0.824 | |
XDP_PCH_OBSDATA_D1 | Default | d | 0.824 | |
XDP_PCH_OBSFN_C0 | Default | d | 0.824 | |
XDP_USB_EXTA_OC_L | Default | d | 0.695 | |
XDP_USB_EXTB_OC_L | Default | d | 0.671 | |
XDP_USB_EXTC_OC_L | Default | d | 0.626 | |
XDP_USB_EXTD_OC_L | Default | d | 0.631 | |